diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
| commit | 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce (patch) | |
| tree | 8dc7be3b13f98b2f6d082dc7424335d9ddfe764d /tests/quick | |
| parent | 71a02f624e9c406ad37a1ed7030f98a36da6e59f (diff) | |
| download | gem5-62b6ff22ec1f90014b1d0fc778014bdb38cc09ce.tar.xz | |
stats: update for snoop filter tweak
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
Diffstat (limited to 'tests/quick')
108 files changed, 6868 insertions, 23625 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 90f1f17e3..8d5fa3758 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869357988000 # Number of ticks simulated -final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1869357999000 # Number of ticks simulated +final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1670594 # Simulator instruction rate (inst/s) -host_op_rate 1670593 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48045239456 # Simulator tick rate (ticks/s) -host_mem_usage 332628 # Number of bytes of host memory used -host_seconds 38.91 # Real time elapsed on the host +host_inst_rate 1770526 # Simulator instruction rate (inst/s) +host_op_rate 1770526 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50919239991 # Simulator tick rate (ticks/s) +host_mem_usage 331076 # Number of bytes of host memory used +host_seconds 36.71 # Real time elapsed on the host sim_insts 64999904 # Number of instructions simulated sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -49,7 +49,7 @@ system.physmem.bw_total::cpu0.data 35592763 # To system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40657621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40657620 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses @@ -83,7 +83,7 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3738722771 # number of cpu cycles simulated +system.cpu0.numCycles 3738722793 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -101,12 +101,12 @@ system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # nu system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1853222732000 99.14% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869357791500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -172,7 +172,7 @@ system.cpu0.kern.mode_switch_good::kernel 0.177764 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1868349163500 99.95% 99.95% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed @@ -191,7 +191,7 @@ system.cpu0.num_fp_register_writes 98967 # nu system.cpu0.num_mem_refs 12536107 # number of memory refs system.cpu0.num_load_insts 7783754 # Number of load instructions system.cpu0.num_store_insts 4752353 # Number of store instructions -system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles +system.cpu0.num_idle_cycles 3689239810.666409 # Number of idle cycles system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles @@ -231,13 +231,13 @@ system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Cl system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 49485886 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1781371 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1781367 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.187330 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187330 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -245,32 +245,32 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits +system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 4360085 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132849 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 132849 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10428966 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10428966 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10428966 # number of overall hits -system.cpu0.dcache.overall_hits::total 10428966 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 10428970 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10428970 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10428970 # number of overall hits +system.cpu0.dcache.overall_hits::total 10428970 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 236538 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 236538 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6921 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 6921 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796607 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796607 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796607 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796607 # number of overall misses +system.cpu0.dcache.demand_misses::cpu0.data 1796603 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1796603 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1796603 # number of overall misses +system.cpu0.dcache.overall_misses::total 1796603 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) @@ -301,8 +301,8 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks -system.cpu0.dcache.writebacks::total 633127 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 633126 # number of writebacks +system.cpu0.dcache.writebacks::total 633126 # number of writebacks system.cpu0.icache.tags.replacements 618292 # number of replacements system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. @@ -383,7 +383,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3738296587 # number of cpu cycles simulated +system.cpu1.numCycles 3738296609 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -399,11 +399,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1856123501500 99.30% 99.30% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869146939500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -457,7 +457,7 @@ system.cpu1.kern.mode_switch_good::idle 0.177356 # fr system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102413500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed system.cpu1.committedInsts 15522159 # Number of instructions committed system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed @@ -474,8 +474,8 @@ system.cpu1.num_fp_register_writes 104129 # nu system.cpu1.num_mem_refs 4961786 # number of memory refs system.cpu1.num_load_insts 2849090 # Number of load instructions system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles -system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles +system.cpu1.num_idle_cycles 3722773671.474783 # Number of idle cycles +system.cpu1.num_busy_cycles 15522937.525217 # Number of busy cycles system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles system.cpu1.Branches 2214163 # Number of branches fetched @@ -515,12 +515,12 @@ system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Cl system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::total 15525875 # Class of executed instruction system.cpu1.dcache.tags.replacements 201757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use +system.cpu1.dcache.tags.tagsinuse 497.601962 # Cycle average of tags in use system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601962 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id @@ -590,7 +590,7 @@ system.cpu1.icache.tags.tagsinuse 453.133719 # Cy system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.warmup_cycle 1859777195500 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy @@ -679,7 +679,7 @@ system.iocache.tags.tagsinuse 0.434096 # Cy system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 1685787164517 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy @@ -721,16 +721,16 @@ system.iocache.avg_blocked_cycles::no_targets nan system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.l2c.tags.replacements 999922 # number of replacements -system.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use -system.l2c.tags.total_refs 4259784 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65337.856710 # Cycle average of tags in use +system.l2c.tags.total_refs 4259780 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 1064972 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.999902 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 3.999899 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55997.404251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4860.296117 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4190.275222 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.171528 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.709605 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 55997.404382 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.296070 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4190.275138 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.171519 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.709600 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.854453 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.074162 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.063939 # Average percentage of cache occupancy @@ -744,37 +744,37 @@ system.l2c.tags.age_task_id_blocks_1024::2 6047 # system.l2c.tags.age_task_id_blocks_1024::3 5933 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 49031 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46377222 # Number of tag accesses -system.l2c.tags.data_accesses 46377222 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 777663 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 777663 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 721478 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 721478 # number of WritebackClean hits +system.l2c.tags.tag_accesses 46377199 # Number of tag accesses +system.l2c.tags.data_accesses 46377199 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 777662 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 777662 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 721480 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 604 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 111476 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 56605 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168080 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168081 # number of ReadExReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626719 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 129011 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755730 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 626716 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 129010 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 755726 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738194 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738192 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910410 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185615 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910407 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits -system.l2c.overall_hits::cpu0.data 738194 # number of overall hits +system.l2c.overall_hits::cpu0.data 738192 # number of overall hits system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits -system.l2c.overall_hits::cpu1.data 185616 # number of overall hits -system.l2c.overall_hits::total 1910410 # number of overall hits +system.l2c.overall_hits::cpu1.data 185615 # number of overall hits +system.l2c.overall_hits::total 1910407 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 2989 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 2147 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 5136 # number of UpgradeReq misses @@ -800,57 +800,57 @@ system.l2c.overall_misses::cpu0.data 1040486 # nu system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses system.l2c.overall_misses::cpu1.data 12101 # number of overall misses system.l2c.overall_misses::total 1066093 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 777663 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 777663 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 721478 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 721478 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 777662 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 777662 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 721480 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 721480 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 3119 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 2751 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 5870 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 1209 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2332 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 225347 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 293018 # number of ReadExReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1553334 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1683380 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 1553331 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 130045 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1683376 # number of ReadSharedReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778680 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1778678 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2976503 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 197716 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2976500 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778680 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1778678 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2976503 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 197716 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2976500 # number of overall (read+write) accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.958320 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780443 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.874957 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963606 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975067 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.969125 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505316 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505314 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.163526 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426381 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.426380 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596533 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596534 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551064 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551065 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584976 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584977 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.358170 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584976 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584977 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.358170 # miss rate for overall accesses @@ -862,6 +862,12 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.writebacks::writebacks 80923 # number of writebacks system.l2c.writebacks::total 80923 # number of writebacks +system.membus.snoop_filter.tot_requests 2182334 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1076327 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 430 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 7449 # Transaction distribution system.membus.trans_dist::ReadResp 948784 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution @@ -871,17 +877,17 @@ system.membus.trans_dist::CleanEvict 918012 # Tr system.membus.trans_dist::UpgradeReq 19594 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 14154 # Transaction distribution system.membus.trans_dist::UpgradeResp 8111 # Transaction distribution -system.membus.trans_dist::ReadExReq 125245 # Transaction distribution +system.membus.trans_dist::ReadExReq 125244 # Transaction distribution system.membus.trans_dist::ReadExResp 124222 # Transaction distribution system.membus.trans_dist::ReadSharedReq 941335 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3216468 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172393 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3216467 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3341629 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3341628 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363264 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 73449426 # Cumulative packet size per connected master and slave (bytes) @@ -889,61 +895,61 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 76118162 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2204372 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 2204371 # Request fanout histogram +system.membus.snoop_fanout::mean 0.000517 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.022725 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2204372 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2203232 99.95% 99.95% # Request fanout histogram +system.membus.snoop_fanout::1 1139 0.05% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2204372 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 6035855 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3018704 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 374458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 2204371 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 6035847 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 3018700 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 777663 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 777662 # Transaction distribution system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1205465 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1205462 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 19613 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 14226 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 33839 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1724580 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450127 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684385 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9133717 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9133705 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766779 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766459 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23358423 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 307065426 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1083516 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7141244 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.105534 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.307488 # Request fanout histogram +system.toL2Bus.pkt_size::total 307065106 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1000943 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7058663 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.106768 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.309067 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6388144 89.45% 89.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 752560 10.54% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6305567 89.33% 89.33% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 752556 10.66% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7141244 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7058663 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 84bdf9ee5..1cd81f116 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829331993500 # Number of ticks simulated final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1840131 # Simulator instruction rate (inst/s) -host_op_rate 1840130 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56067507873 # Simulator tick rate (ticks/s) -host_mem_usage 330836 # Number of bytes of host memory used -host_seconds 32.63 # Real time elapsed on the host +host_inst_rate 1838030 # Simulator instruction rate (inst/s) +host_op_rate 1838029 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56003449171 # Simulator tick rate (ticks/s) +host_mem_usage 325188 # Number of bytes of host memory used +host_seconds 32.66 # Real time elapsed on the host sim_insts 60038469 # Number of instructions simulated sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e58364a4b..d99331f2d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.982593 # Number of seconds simulated -sim_ticks 1982592736000 # Number of ticks simulated -final_tick 1982592736000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.963613 # Number of seconds simulated +sim_ticks 1963612574000 # Number of ticks simulated +final_tick 1963612574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1178528 # Simulator instruction rate (inst/s) -host_op_rate 1178528 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38301918928 # Simulator tick rate (ticks/s) -host_mem_usage 332884 # Number of bytes of host memory used -host_seconds 51.76 # Real time elapsed on the host -sim_insts 61003209 # Number of instructions simulated -sim_ops 61003209 # Number of ops (including micro ops) simulated +host_inst_rate 993881 # Simulator instruction rate (inst/s) +host_op_rate 993880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32036346352 # Simulator tick rate (ticks/s) +host_mem_usage 331076 # Number of bytes of host memory used +host_seconds 61.29 # Real time elapsed on the host +sim_insts 60918165 # Number of instructions simulated +sim_ops 60918165 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 800192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24686016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 59328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 523328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 830784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24731648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 28416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 436224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26069824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 800192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 59328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 859520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7739392 # Number of bytes written to this memory -system.physmem.bytes_written::total 7739392 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385719 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 927 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8177 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26028032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 830784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 28416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 859200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7709248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7709248 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 444 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6816 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407341 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120928 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120928 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 403609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12451380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 263961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13149359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 403609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3903672 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3903672 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3903672 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 403609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12451380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 263961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17053031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407341 # Number of read requests accepted -system.physmem.writeReqs 120928 # Number of write requests accepted -system.physmem.readBursts 407341 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120928 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26061824 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8000 # Total number of bytes read from write queue -system.physmem.bytesWritten 7737600 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26069824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7739392 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 125 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 406688 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120457 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120457 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 423090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12594973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13255177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 423090 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 437561 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3926053 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3926053 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3926053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 423090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12594973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17181230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406688 # Number of read requests accepted +system.physmem.writeReqs 120457 # Number of write requests accepted +system.physmem.readBursts 406688 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120457 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26019904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7707200 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26028032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7709248 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25226 # Per bank write bursts -system.physmem.perBankRdBursts::1 25379 # Per bank write bursts -system.physmem.perBankRdBursts::2 25423 # Per bank write bursts -system.physmem.perBankRdBursts::3 24855 # Per bank write bursts -system.physmem.perBankRdBursts::4 25157 # Per bank write bursts -system.physmem.perBankRdBursts::5 25423 # Per bank write bursts -system.physmem.perBankRdBursts::6 25497 # Per bank write bursts -system.physmem.perBankRdBursts::7 25338 # Per bank write bursts -system.physmem.perBankRdBursts::8 25239 # Per bank write bursts -system.physmem.perBankRdBursts::9 25589 # Per bank write bursts -system.physmem.perBankRdBursts::10 25733 # Per bank write bursts -system.physmem.perBankRdBursts::11 25917 # Per bank write bursts -system.physmem.perBankRdBursts::12 25947 # Per bank write bursts -system.physmem.perBankRdBursts::13 25572 # Per bank write bursts -system.physmem.perBankRdBursts::14 25277 # Per bank write bursts -system.physmem.perBankRdBursts::15 25644 # Per bank write bursts -system.physmem.perBankWrBursts::0 7850 # Per bank write bursts -system.physmem.perBankWrBursts::1 7778 # Per bank write bursts -system.physmem.perBankWrBursts::2 7471 # Per bank write bursts -system.physmem.perBankWrBursts::3 6886 # Per bank write bursts -system.physmem.perBankWrBursts::4 7104 # Per bank write bursts -system.physmem.perBankWrBursts::5 7345 # Per bank write bursts -system.physmem.perBankWrBursts::6 7431 # Per bank write bursts -system.physmem.perBankWrBursts::7 7144 # Per bank write bursts -system.physmem.perBankWrBursts::8 7161 # Per bank write bursts -system.physmem.perBankWrBursts::9 7315 # Per bank write bursts -system.physmem.perBankWrBursts::10 7729 # Per bank write bursts -system.physmem.perBankWrBursts::11 8150 # Per bank write bursts -system.physmem.perBankWrBursts::12 8256 # Per bank write bursts -system.physmem.perBankWrBursts::13 7924 # Per bank write bursts -system.physmem.perBankWrBursts::14 7541 # Per bank write bursts -system.physmem.perBankWrBursts::15 7815 # Per bank write bursts +system.physmem.perBankRdBursts::0 25130 # Per bank write bursts +system.physmem.perBankRdBursts::1 25381 # Per bank write bursts +system.physmem.perBankRdBursts::2 25483 # Per bank write bursts +system.physmem.perBankRdBursts::3 24909 # Per bank write bursts +system.physmem.perBankRdBursts::4 25165 # Per bank write bursts +system.physmem.perBankRdBursts::5 25252 # Per bank write bursts +system.physmem.perBankRdBursts::6 25797 # Per bank write bursts +system.physmem.perBankRdBursts::7 25541 # Per bank write bursts +system.physmem.perBankRdBursts::8 25672 # Per bank write bursts +system.physmem.perBankRdBursts::9 25333 # Per bank write bursts +system.physmem.perBankRdBursts::10 25279 # Per bank write bursts +system.physmem.perBankRdBursts::11 25593 # Per bank write bursts +system.physmem.perBankRdBursts::12 25647 # Per bank write bursts +system.physmem.perBankRdBursts::13 25645 # Per bank write bursts +system.physmem.perBankRdBursts::14 25712 # Per bank write bursts +system.physmem.perBankRdBursts::15 25022 # Per bank write bursts +system.physmem.perBankWrBursts::0 7825 # Per bank write bursts +system.physmem.perBankWrBursts::1 7603 # Per bank write bursts +system.physmem.perBankWrBursts::2 7492 # Per bank write bursts +system.physmem.perBankWrBursts::3 6933 # Per bank write bursts +system.physmem.perBankWrBursts::4 7149 # Per bank write bursts +system.physmem.perBankWrBursts::5 7135 # Per bank write bursts +system.physmem.perBankWrBursts::6 7628 # Per bank write bursts +system.physmem.perBankWrBursts::7 7255 # Per bank write bursts +system.physmem.perBankWrBursts::8 7538 # Per bank write bursts +system.physmem.perBankWrBursts::9 7229 # Per bank write bursts +system.physmem.perBankWrBursts::10 7235 # Per bank write bursts +system.physmem.perBankWrBursts::11 7425 # Per bank write bursts +system.physmem.perBankWrBursts::12 7840 # Per bank write bursts +system.physmem.perBankWrBursts::13 8302 # Per bank write bursts +system.physmem.perBankWrBursts::14 8309 # Per bank write bursts +system.physmem.perBankWrBursts::15 7527 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 1982585344500 # Total gap between requests +system.physmem.numWrRetry 17 # Number of times write queue was full causing retry +system.physmem.totGap 1963565980500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407341 # Read request sizes (log2) +system.physmem.readPktSize::6 406688 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120928 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407136 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120457 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406481 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -158,176 +158,179 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67562 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 500.272698 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 302.933598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 404.928891 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16219 24.01% 24.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12429 18.40% 42.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5206 7.71% 50.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3267 4.84% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2499 3.70% 58.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4251 6.29% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1505 2.23% 67.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2122 3.14% 70.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20064 29.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67562 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5401 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.393816 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2870.561720 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5398 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 507.991867 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 305.024910 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.812380 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15899 23.95% 23.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12177 18.34% 42.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5415 8.16% 50.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3379 5.09% 55.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2311 3.48% 59.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2006 3.02% 62.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1513 2.28% 64.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1280 1.93% 66.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22413 33.76% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66393 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.397255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2872.179140 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5389 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5401 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.384744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.196926 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.269218 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4796 88.80% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 29 0.54% 89.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 16 0.30% 89.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 48 0.89% 90.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 211 3.91% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.26% 94.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 16 0.30% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 27 0.50% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 197 3.65% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 3 0.06% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 2 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 3 0.06% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.07% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 5 0.09% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.04% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 9 0.17% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5401 # Writes before turning the bus around for reads -system.physmem.totQLat 2785960750 # Total ticks spent queuing -system.physmem.totMemAccLat 10421260750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2036080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6841.48 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5392 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5392 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.334013 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.995867 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.838616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4788 88.80% 88.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 33 0.61% 89.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 252 4.67% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 18 0.33% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 6 0.11% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 13 0.24% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 10 0.19% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 1 0.02% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 18 0.33% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 18 0.33% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 190 3.52% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.06% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 7 0.13% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 2 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 6 0.11% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 2 0.04% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.06% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 13 0.24% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5392 # Writes before turning the bus around for reads +system.physmem.totQLat 2148968000 # Total ticks spent queuing +system.physmem.totMemAccLat 9771986750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2032805000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5285.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25591.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24035.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.26 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing -system.physmem.readRowHits 363789 # Number of row buffer hits during reads -system.physmem.writeRowHits 96765 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.02 # Row buffer hit rate for writes -system.physmem.avgGap 3752984.45 # Average gap between requests -system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243704160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132973500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577924400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 382378320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72905362650 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1125601770750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1330337220900 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.009839 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1872255893500 # Time in different power states -system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states +system.physmem.avgWrQLen 24.84 # Average write queue length when enqueuing +system.physmem.readRowHits 364299 # Number of row buffer hits during reads +system.physmem.writeRowHits 96294 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.94 # Row buffer hit rate for writes +system.physmem.avgGap 3724906.77 # Average gap between requests +system.physmem.pageHitRate 87.40 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248179680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135415500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1580732400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382449600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 66024340605 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1120248020250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316872375875 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.639531 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1863393486000 # Time in different power states +system.physmem_0.memoryStateTime::REF 65569140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 44130839000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34644235250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 267064560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145719750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1598360400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 401053680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73884851505 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124742561750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1330532718765 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.108451 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1870830292750 # Time in different power states -system.physmem_1.memoryStateTime::REF 66203020000 # Time in different power states +system.physmem_1.actEnergy 253751400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 138455625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1590443400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 397904400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128253237840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66573650745 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119766169250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316973612660 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.691088 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1862592163500 # Time in different power states +system.physmem_1.memoryStateTime::REF 65569140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45556426000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35445557750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7416468 # DTB read hits -system.cpu0.dtb.read_misses 7442 # DTB read misses +system.cpu0.dtb.read_hits 7494168 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 490672 # DTB read accesses -system.cpu0.dtb.write_hits 5004426 # DTB write hits -system.cpu0.dtb.write_misses 812 # DTB write misses +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 5065702 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations -system.cpu0.dtb.write_accesses 187451 # DTB write accesses -system.cpu0.dtb.data_hits 12420894 # DTB hits -system.cpu0.dtb.data_misses 8254 # DTB misses +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.data_hits 12559870 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations -system.cpu0.dtb.data_accesses 678123 # DTB accesses -system.cpu0.itb.fetch_hits 3482357 # ITB hits +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3501177 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3486228 # ITB accesses +system.cpu0.itb.fetch_accesses 3505048 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -340,36 +343,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3964851876 # number of cpu cycles simulated +system.cpu0.numCycles 3925790590 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162795 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80935 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139406 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54983 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 112945 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1904797058500 96.08% 96.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94101500 0.00% 96.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 790644500 0.04% 96.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 326474000 0.02% 96.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 76417629500 3.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1982425908000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6796 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164911 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56822 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1974 1.40% 41.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 422 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82045 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141394 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56288 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1974 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 422 0.37% 51.29% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55866 48.71% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114681 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1901241129000 96.86% 96.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93739000 0.00% 96.86% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 789776000 0.04% 96.90% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 316619500 0.02% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60454001500 3.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962895265000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990602 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679348 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810188 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.680919 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811074 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -401,352 +404,352 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 524 0.36% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132536 89.80% 92.24% # number of callpals executed -system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rti 4325 2.93% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 504 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3063 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134533 89.85% 92.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6700 4.47% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147596 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6863 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches +system.cpu0.kern.callpal::total 149727 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6886 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1283 -system.cpu0.kern.mode_good::user 1283 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186944 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186175 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.315001 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1977682468000 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3900182500 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313908 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1959142459500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3540793500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3025 # number of times the context was actually changed -system.cpu0.committedInsts 47316464 # Number of instructions committed -system.cpu0.committedOps 47316464 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43886764 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses -system.cpu0.num_func_calls 1185664 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5565449 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43886764 # number of integer instructions -system.cpu0.num_fp_insts 206939 # number of float instructions -system.cpu0.num_int_register_reads 60334858 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32718698 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 102286 # number of times the floating registers were written -system.cpu0.num_mem_refs 12460790 # number of memory refs -system.cpu0.num_load_insts 7443408 # Number of load instructions -system.cpu0.num_store_insts 5017382 # Number of store instructions -system.cpu0.num_idle_cycles 3699967048.966084 # Number of idle cycles -system.cpu0.num_busy_cycles 264884827.033916 # Number of busy cycles -system.cpu0.not_idle_fraction 0.066808 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.933192 # Percentage of idle cycles -system.cpu0.Branches 7133745 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2703031 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31175440 65.88% 71.59% # Class of executed instruction -system.cpu0.op_class::IntMult 51698 0.11% 71.70% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction -system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::MemRead 7616501 16.09% 87.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 5023484 10.61% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 727686 1.54% 100.00% # Class of executed instruction +system.cpu0.kern.swap_context 3064 # number of times the context was actually changed +system.cpu0.committedInsts 47755591 # Number of instructions committed +system.cpu0.committedOps 47755591 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44289668 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210363 # Number of float alu accesses +system.cpu0.num_func_calls 1202061 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5613734 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44289668 # number of integer instructions +system.cpu0.num_fp_insts 210363 # number of float instructions +system.cpu0.num_int_register_reads 60881629 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33006420 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102169 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104020 # number of times the floating registers were written +system.cpu0.num_mem_refs 12600044 # number of memory refs +system.cpu0.num_load_insts 7521304 # Number of load instructions +system.cpu0.num_store_insts 5078740 # Number of store instructions +system.cpu0.num_idle_cycles 3699854946.150013 # Number of idle cycles +system.cpu0.num_busy_cycles 225935643.849987 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057552 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942448 # Percentage of idle cycles +system.cpu0.Branches 7206590 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2726655 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31439878 65.82% 71.53% # Class of executed instruction +system.cpu0.op_class::IntMult 52896 0.11% 71.64% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.64% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25705 0.05% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.70% # Class of executed instruction +system.cpu0.op_class::MemRead 7696642 16.11% 87.81% # Class of executed instruction +system.cpu0.op_class::MemWrite 5084839 10.65% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 735920 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47325062 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1172723 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.333527 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11236927 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1173142 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.578488 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333527 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50908342 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50908342 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6342787 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6342787 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4601077 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4601077 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138129 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138129 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145434 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145434 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10943864 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10943864 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10943864 # number of overall hits -system.cpu0.dcache.overall_hits::total 10943864 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 934179 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 934179 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249076 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249076 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13578 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13578 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5739 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5739 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1183255 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1183255 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1183255 # number of overall misses -system.cpu0.dcache.overall_misses::total 1183255 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42885164500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42885164500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16793601000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16793601000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151515500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 151515500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 94785500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 94785500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59678765500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 59678765500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59678765500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 59678765500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7276966 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7276966 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4850153 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4850153 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151707 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151707 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151173 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151173 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12127119 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12127119 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12127119 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12127119 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128375 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128375 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051354 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051354 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089501 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089501 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037963 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037963 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097571 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097571 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097571 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097571 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45906.795700 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.795700 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67423.601632 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67423.601632 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11158.896745 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11158.896745 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16516.030667 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16516.030667 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50436.098305 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50436.098305 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50436.098305 # average overall miss latency +system.cpu0.op_class::total 47764191 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1179864 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.229406 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11369687 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1180280 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.633042 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 114940500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.229406 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986776 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986776 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 369 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51471495 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51471495 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6411173 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6411173 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4657733 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4657733 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 143918 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 143918 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 147952 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 147952 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11068906 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11068906 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11068906 # number of overall hits +system.cpu0.dcache.overall_hits::total 11068906 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 937797 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 937797 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251494 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251494 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13653 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13653 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5444 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5444 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1189291 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1189291 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1189291 # number of overall misses +system.cpu0.dcache.overall_misses::total 1189291 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29158420500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 29158420500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10960256500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10960256500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150265500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150265500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 47401000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 47401000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 40118677000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 40118677000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 40118677000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 40118677000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7348970 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7348970 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4909227 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4909227 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157571 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157571 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153396 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153396 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12258197 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12258197 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12258197 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12258197 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127609 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127609 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051229 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051229 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086647 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086647 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035490 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035490 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097020 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097020 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097020 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097020 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31092.465107 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31092.465107 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43580.588404 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43580.588404 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11006.042628 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11006.042628 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8707.016899 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8707.016899 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33733.272176 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33733.272176 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33733.272176 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 672790 # number of writebacks -system.cpu0.dcache.writebacks::total 672790 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934179 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 934179 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249076 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 249076 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13578 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13578 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183255 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1183255 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183255 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1183255 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7083 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7083 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10783 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10783 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17866 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17866 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41950985500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41950985500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16544525000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16544525000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 137937500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137937500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 89046500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 89046500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58495510500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 58495510500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58495510500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 58495510500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566902000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1566902000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1566902000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128375 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128375 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051354 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051354 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089501 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089501 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037963 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037963 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097571 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097571 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097571 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.795700 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.795700 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66423.601632 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66423.601632 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10158.896745 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10158.896745 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15516.030667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15516.030667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49436.098305 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221220.104476 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221220.104476 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87703.011306 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87703.011306 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 686545 # number of replacements -system.cpu0.icache.tags.tagsinuse 506.490868 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 46637883 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 687057 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.880661 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490868 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.989240 # Average percentage of cache occupancy +system.cpu0.dcache.writebacks::writebacks 678308 # number of writebacks +system.cpu0.dcache.writebacks::total 678308 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 937797 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 937797 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251494 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251494 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13653 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13653 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5444 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5444 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1189291 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1189291 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1189291 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1189291 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10837 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10837 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17947 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17947 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28220623500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28220623500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10708762500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10708762500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136612500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136612500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41957000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41957000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38929386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38929386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38929386000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38929386000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1578468500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1578468500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1578468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1578468500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127609 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127609 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051229 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086647 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086647 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035490 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097020 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097020 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097020 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30092.465107 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30092.465107 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42580.588404 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42580.588404 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10006.042628 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10006.042628 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7707.016899 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7707.016899 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32733.272176 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222006.821378 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222006.821378 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87951.663231 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87951.663231 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 698162 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.148952 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47065399 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 698674 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.363891 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42439448500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.148952 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992478 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992478 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48012241 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48012241 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 46637883 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46637883 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46637883 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46637883 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46637883 # number of overall hits -system.cpu0.icache.overall_hits::total 46637883 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687179 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687179 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687179 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687179 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687179 # number of overall misses -system.cpu0.icache.overall_misses::total 687179 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10623000500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10623000500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10623000500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10623000500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10623000500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10623000500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47325062 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47325062 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47325062 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47325062 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47325062 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47325062 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014520 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014520 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014520 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014520 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014520 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014520 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15458.854971 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15458.854971 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15458.854971 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15458.854971 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15458.854971 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48462983 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48462983 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47065399 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47065399 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47065399 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47065399 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47065399 # number of overall hits +system.cpu0.icache.overall_hits::total 47065399 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 698792 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 698792 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 698792 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 698792 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 698792 # number of overall misses +system.cpu0.icache.overall_misses::total 698792 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10197257500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10197257500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10197257500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10197257500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10197257500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10197257500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47764191 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47764191 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47764191 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47764191 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47764191 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47764191 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014630 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014630 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014630 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014630 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014630 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014630 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14592.693534 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14592.693534 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14592.693534 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14592.693534 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14592.693534 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 686545 # number of writebacks -system.cpu0.icache.writebacks::total 686545 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687179 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687179 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687179 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687179 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687179 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687179 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9935821500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9935821500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9935821500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9935821500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9935821500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9935821500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014520 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014520 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14458.854971 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14458.854971 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14458.854971 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 698162 # number of writebacks +system.cpu0.icache.writebacks::total 698162 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 698792 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 698792 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 698792 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 698792 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 698792 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9498465500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9498465500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9498465500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9498465500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9498465500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9498465500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014630 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014630 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014630 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014630 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13592.693534 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13592.693534 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13592.693534 # average overall mshr miss latency system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2511191 # DTB read hits -system.cpu1.dtb.read_misses 2993 # DTB read misses +system.cpu1.dtb.read_hits 2421538 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 239364 # DTB read accesses -system.cpu1.dtb.write_hits 1830032 # DTB write hits -system.cpu1.dtb.write_misses 342 # DTB write misses +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.write_hits 1759460 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations -system.cpu1.dtb.write_accesses 105248 # DTB write accesses -system.cpu1.dtb.data_hits 4341223 # DTB hits -system.cpu1.dtb.data_misses 3335 # DTB misses +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.data_hits 4180998 # DTB hits +system.cpu1.dtb.data_misses 3333 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations -system.cpu1.dtb.data_accesses 344612 # DTB accesses -system.cpu1.itb.fetch_hits 1990291 # ITB hits +system.cpu1.dtb.data_accesses 344610 # DTB accesses +system.cpu1.itb.fetch_hits 1965348 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991507 # ITB accesses +system.cpu1.itb.fetch_accesses 1966564 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -759,32 +762,32 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3965185472 # number of cpu cycles simulated +system.cpu1.numCycles 3927225148 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2869 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 81049 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27547 38.53% 38.53% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41462 57.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71504 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26679 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26155 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55329 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1912239584500 96.45% 96.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731206500 0.04% 96.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 374509500 0.02% 96.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 69246698500 3.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1982591999000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968490 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78631 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26567 38.35% 38.35% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1968 2.84% 41.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 504 0.73% 41.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40242 58.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69281 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25724 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1968 3.68% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 504 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25220 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53416 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1910368546000 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 730956000 0.04% 97.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 356511000 0.02% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 52155834000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1963611847000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968269 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630819 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.773789 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.626708 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771005 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -800,334 +803,342 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wripir 422 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2066 2.79% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2001 2.80% 3.39% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65182 88.12% 91.52% # number of callpals executed -system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed -system.cpu1.kern.callpal::rti 3826 5.17% 99.76% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed +system.cpu1.kern.callpal::swpipl 63030 88.06% 91.46% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3778 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73972 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2115 # number of protection mode switches +system.cpu1.kern.callpal::total 71579 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2069 # number of protection mode switches system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 912 +system.cpu1.kern.mode_switch::idle 2878 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 892 system.cpu1.kern.mode_good::user 464 -system.cpu1.kern.mode_good::idle 448 -system.cpu1.kern.mode_switch_good::kernel 0.431206 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 428 +system.cpu1.kern.mode_switch_good::kernel 0.431126 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153372 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 19469811000 0.98% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1729387000 0.09% 1.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1961392799000 98.93% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2067 # number of times the context was actually changed -system.cpu1.committedInsts 13686745 # Number of instructions committed -system.cpu1.committedOps 13686745 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12624358 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses -system.cpu1.num_func_calls 430170 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1359717 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12624358 # number of integer instructions -system.cpu1.num_fp_insts 178612 # number of float instructions -system.cpu1.num_int_register_reads 17383561 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9260404 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written -system.cpu1.num_mem_refs 4365379 # number of memory refs -system.cpu1.num_load_insts 2525846 # Number of load instructions -system.cpu1.num_store_insts 1839533 # Number of store instructions -system.cpu1.num_idle_cycles 3912234287.998026 # Number of idle cycles -system.cpu1.num_busy_cycles 52951184.001973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013354 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986646 # Percentage of idle cycles -system.cpu1.Branches 1950147 # Number of branches fetched -system.cpu1.op_class::No_OpClass 733822 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 8101444 59.18% 64.54% # Class of executed instruction -system.cpu1.op_class::IntMult 23186 0.17% 64.71% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14372 0.10% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.01% 64.83% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.83% # Class of executed instruction -system.cpu1.op_class::MemRead 2600523 19.00% 83.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 1840557 13.44% 97.27% # Class of executed instruction -system.cpu1.op_class::IprAccess 374219 2.73% 100.00% # Class of executed instruction +system.cpu1.kern.mode_switch_good::idle 0.148714 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329699 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17834392500 0.91% 0.91% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1709021000 0.09% 1.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1944068431500 99.00% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2002 # number of times the context was actually changed +system.cpu1.committedInsts 13162574 # Number of instructions committed +system.cpu1.committedOps 13162574 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12139381 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 173446 # Number of float alu accesses +system.cpu1.num_func_calls 411749 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1304648 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12139381 # number of integer instructions +system.cpu1.num_fp_insts 173446 # number of float instructions +system.cpu1.num_int_register_reads 16710166 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8908141 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90735 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92616 # number of times the floating registers were written +system.cpu1.num_mem_refs 4204594 # number of memory refs +system.cpu1.num_load_insts 2435865 # Number of load instructions +system.cpu1.num_store_insts 1768729 # Number of store instructions +system.cpu1.num_idle_cycles 3877736087.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49489060.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012602 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987398 # Percentage of idle cycles +system.cpu1.Branches 1871255 # Number of branches fetched +system.cpu1.op_class::No_OpClass 705493 5.36% 5.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 7781042 59.10% 64.46% # Class of executed instruction +system.cpu1.op_class::IntMult 21322 0.16% 64.62% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.62% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14181 0.11% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::MemRead 2507774 19.05% 83.79% # Class of executed instruction +system.cpu1.op_class::MemWrite 1769717 13.44% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 364421 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13690109 # Class of executed instruction -system.cpu1.dcache.tags.replacements 173692 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.984896 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4164965 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 174204 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.908550 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90321767000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.984896 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941377 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.941377 # Average percentage of cache occupancy +system.cpu1.op_class::total 13165936 # Class of executed instruction +system.cpu1.dcache.tags.replacements 166516 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.373615 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4012325 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 167028 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.021871 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 70707818000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.373615 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949948 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949948 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17608650 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17608650 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2339562 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2339562 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1707213 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1707213 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50427 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50427 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53080 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 53080 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4046775 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4046775 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4046775 # number of overall hits -system.cpu1.dcache.overall_hits::total 4046775 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 123491 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 123491 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 65586 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 65586 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9255 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9255 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6109 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6109 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 189077 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 189077 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 189077 # number of overall misses -system.cpu1.dcache.overall_misses::total 189077 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1555586500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1555586500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1871475500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1871475500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84845000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84845000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 96965500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 96965500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 3427062000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 3427062000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 3427062000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 3427062000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2463053 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2463053 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1772799 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1772799 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59682 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 59682 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59189 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59189 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4235852 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4235852 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4235852 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4235852 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050137 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050137 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036996 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036996 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155072 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155072 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103212 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103212 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044637 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044637 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044637 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044637 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12596.760088 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12596.760088 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28534.679657 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28534.679657 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9167.477039 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9167.477039 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15872.565068 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15872.565068 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18125.218826 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18125.218826 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18125.218826 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 16958396 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16958396 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2257201 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2257201 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1642023 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1642023 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48215 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48215 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50821 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50821 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3899224 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3899224 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3899224 # number of overall hits +system.cpu1.dcache.overall_hits::total 3899224 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118432 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118432 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62660 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62660 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8936 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8936 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5856 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5856 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 181092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 181092 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 181092 # number of overall misses +system.cpu1.dcache.overall_misses::total 181092 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1454494000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1454494000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1265962000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1265962000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 82083000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 82083000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49296000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49296000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2720456000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2720456000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2720456000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2720456000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2375633 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2375633 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1704683 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1704683 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57151 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57151 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56677 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4080316 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4080316 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4080316 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4080316 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049853 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049853 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036758 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036758 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156358 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156358 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103322 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103322 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044382 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044382 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044382 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044382 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12281.258444 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12281.258444 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20203.670603 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20203.670603 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.653536 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.653536 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8418.032787 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8418.032787 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15022.507897 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15022.507897 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15022.507897 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 119726 # number of writebacks -system.cpu1.dcache.writebacks::total 119726 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123491 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123491 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65586 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 65586 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9255 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9255 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6109 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6109 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 189077 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 189077 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 189077 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 189077 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3348 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3466 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1432095500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1432095500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1805889500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1805889500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75590000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75590000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 90856500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 90856500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3237985000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3237985000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3237985000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3237985000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 25051000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 25051000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050137 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050137 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036996 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036996 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155072 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155072 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103212 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044637 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044637 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11596.760088 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11596.760088 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27534.679657 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27534.679657 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8167.477039 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8167.477039 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14872.565068 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14872.565068 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17125.218826 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7227.639931 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7227.639931 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 331529 # number of replacements -system.cpu1.icache.tags.tagsinuse 442.932822 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13358029 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 332041 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.230059 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932822 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.865103 # Average percentage of cache occupancy +system.cpu1.dcache.writebacks::writebacks 114398 # number of writebacks +system.cpu1.dcache.writebacks::total 114398 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118432 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118432 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62660 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62660 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8936 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8936 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5856 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5856 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 181092 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 181092 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 181092 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 181092 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 89 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 89 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3221 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3221 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3310 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3310 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1336062000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1336062000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1203302000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1203302000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73147000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73147000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43441000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43441000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539364000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2539364000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539364000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2539364000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 20174000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 20174000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 20174000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 20174000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049853 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049853 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036758 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036758 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.156358 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.156358 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103322 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103322 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044382 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044382 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044382 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11281.258444 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11281.258444 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19203.670603 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19203.670603 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.653536 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.653536 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7418.203552 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7418.203552 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14022.507897 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 226674.157303 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 226674.157303 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 6094.864048 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 6094.864048 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 316153 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.936315 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12849230 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 316665 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.576729 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1962762014000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.936315 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870969 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870969 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 403 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14022191 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14022191 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13358029 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13358029 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13358029 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13358029 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13358029 # number of overall hits -system.cpu1.icache.overall_hits::total 13358029 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 332081 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 332081 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 332081 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 332081 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 332081 # number of overall misses -system.cpu1.icache.overall_misses::total 332081 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4540351000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4540351000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4540351000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4540351000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4540351000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4540351000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13690110 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13690110 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13690110 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13690110 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13690110 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13690110 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024257 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024257 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024257 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024257 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024257 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024257 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13672.420283 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13672.420283 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13672.420283 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13672.420283 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13672.420283 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13482644 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13482644 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12849230 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12849230 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12849230 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12849230 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12849230 # number of overall hits +system.cpu1.icache.overall_hits::total 12849230 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316707 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316707 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316707 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316707 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316707 # number of overall misses +system.cpu1.icache.overall_misses::total 316707 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4252859000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4252859000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4252859000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4252859000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4252859000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4252859000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13165937 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13165937 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13165937 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13165937 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13165937 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13165937 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024055 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024055 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024055 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024055 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024055 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024055 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13428.370702 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13428.370702 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13428.370702 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13428.370702 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13428.370702 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 331529 # number of writebacks -system.cpu1.icache.writebacks::total 331529 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332081 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 332081 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 332081 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 332081 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 332081 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 332081 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4208270000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4208270000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4208270000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4208270000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4208270000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4208270000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024257 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024257 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024257 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024257 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12672.420283 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12672.420283 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12672.420283 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 316153 # number of writebacks +system.cpu1.icache.writebacks::total 316153 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316707 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316707 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316707 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316707 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316707 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316707 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3936152000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3936152000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3936152000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3936152000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3936152000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3936152000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024055 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024055 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024055 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024055 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12428.370702 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12428.370702 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12428.370702 # average overall mshr miss latency system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1140,98 +1151,98 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 55683 # Transaction distribution -system.iobus.trans_dist::WriteResp 55683 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14050 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55610 # Transaction distribution +system.iobus.trans_dist::WriteResp 55610 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 188 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18150 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42664 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56200 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42514 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 171 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9075 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82454 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744078 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 15116500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 81882 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743498 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 14957500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 764000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 183000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15844000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15839500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6055500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6056000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215674412 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 216128057 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28533000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28456000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41948000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.566860 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.569299 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1775103309000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.566860 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035429 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035429 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756488432000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569299 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035581 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035581 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses -system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses -system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245146529 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5245146529 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 5267103412 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5267103412 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 5267103412 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5267103412 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses +system.iocache.demand_misses::total 41726 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses +system.iocache.overall_misses::total 41726 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21854883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21854883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858321174 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4858321174 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 4880176057 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4880176057 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 4880176057 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4880176057 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1240,38 +1251,38 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126230.904144 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126230.904144 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126227.704172 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126227.704172 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126227.704172 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125602.775862 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125602.775862 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116921.476078 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 116921.476078 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 116957.677635 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 116957.677635 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 116957.677635 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165739741 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3165739741 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 3178946624 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3178946624 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 3178946624 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3178946624 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13154883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13154883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778324656 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2778324656 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 2791479539 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2791479539 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 2791479539 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2791479539 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1280,206 +1291,206 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76187.421568 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76187.421568 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76184.403959 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76184.403959 # average overall mshr miss latency -system.l2c.tags.replacements 342136 # number of replacements -system.l2c.tags.tagsinuse 65163.366749 # Cycle average of tags in use -system.l2c.tags.total_refs 3685387 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407142 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.051847 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54851.977847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4799.733629 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5353.675533 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 118.645951 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 39.333789 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.836975 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073238 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.081691 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.001810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994314 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6298 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52712 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35906899 # Number of tag accesses -system.l2c.tags.data_accesses 35906899 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 792516 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 792516 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 746948 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 746948 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 548 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 731 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 41 # number of SCUpgradeReq hits +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75602.775862 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75602.775862 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66863.800924 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66863.800924 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66900.242990 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 66900.242990 # average overall mshr miss latency +system.l2c.tags.replacements 341504 # number of replacements +system.l2c.tags.tagsinuse 65213.029486 # Cycle average of tags in use +system.l2c.tags.total_refs 3680110 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406507 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.053005 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9200946000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55179.216512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4842.215722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5040.815485 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 110.867276 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 39.914491 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.841968 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073886 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076917 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001692 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000609 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995072 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1114 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5002 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6095 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52608 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35882279 # Number of tag accesses +system.l2c.tags.data_accesses 35882279 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 792706 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 792706 # 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mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.957601 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974843 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.966163 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480857 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139589 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.415692 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013177 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291674 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002963 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260158 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.330332 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.048180 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172961 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018195 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.330332 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002791 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.048180 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172961 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68754.374159 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68857.615894 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68793.478261 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68479.481641 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68922.043011 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68701.239224 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117149.547708 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121705.725657 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117441.691706 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121166.009010 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113991.494713 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 115926.035503 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113993.899770 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121152.163481 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.886116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121352.751888 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121467.924650 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 115267.622116 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208714.810109 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208568.601583 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82745.270346 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 6801.933064 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 70406.080068 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 7201 # Transaction distribution -system.membus.trans_dist::ReadResp 292681 # Transaction distribution -system.membus.trans_dist::WriteReq 14131 # Transaction distribution -system.membus.trans_dist::WriteResp 14131 # Transaction distribution -system.membus.trans_dist::WritebackDirty 120928 # Transaction distribution -system.membus.trans_dist::CleanEvict 262098 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16893 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11783 # Transaction distribution +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943838 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.764342 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868265 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.964554 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.969222 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477532 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122275 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412814 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013220 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290494 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002169 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260322 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172959 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328946 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.041840 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19888.643319 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19810.046189 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19859.512091 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19527.839644 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19963.768116 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 19745.682451 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67032.075080 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72564.937035 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67330.623506 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72072.327821 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63225.105930 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72462.025316 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63233.157887 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72049.033202 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64361.273819 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72753.380631 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72561.364968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64752.759230 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209502.039381 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 214168.539326 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.730518 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82997.687636 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 5758.610272 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 70970.527356 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 859272 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 411340 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 7199 # Transaction distribution +system.membus.trans_dist::ReadResp 292676 # Transaction distribution +system.membus.trans_dist::WriteReq 14058 # Transaction distribution +system.membus.trans_dist::WriteResp 14058 # Transaction distribution +system.membus.trans_dist::WritebackDirty 120457 # Transaction distribution +system.membus.trans_dist::CleanEvict 261938 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16120 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11242 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 123156 # Transaction distribution -system.membus.trans_dist::ReadExResp 122284 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285480 # Transaction distribution +system.membus.trans_dist::ReadExReq 122469 # Transaction distribution +system.membus.trans_dist::ReadExResp 121633 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285477 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42664 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1185794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1228458 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1311895 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82454 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31150976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31233430 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42514 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1182508 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1225022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83435 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83435 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1308457 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81882 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31079040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31160922 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33891670 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22771 # Total snoops (count) -system.membus.snoop_fanout::samples 883231 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 33819162 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21640 # Total snoops (count) +system.membus.snoop_fanout::samples 498117 # Request fanout histogram +system.membus.snoop_fanout::mean 0.001313 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.036211 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 883231 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 497463 99.87% 99.87% # Request fanout histogram +system.membus.snoop_fanout::1 654 0.13% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 883231 # Request fanout histogram -system.membus.reqLayer0.occupancy 40519500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 498117 # Request fanout histogram +system.membus.reqLayer0.occupancy 40353000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1327558723 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1324238537 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2178214500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2174676250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 898617 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 893117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4790762 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2395545 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 361654 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1242 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1182 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4780466 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2390280 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 355276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 975 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 915 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7201 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107124 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14131 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14131 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 913453 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1018074 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 816802 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17061 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11848 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297601 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297601 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019260 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1080678 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2060877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3585353 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 995690 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 558897 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7200817 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 87916672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118008584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 42470976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18601102 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266997334 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 484769 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2873172 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.136988 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.344078 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2101675 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14058 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14058 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 871643 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1014315 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 816241 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16314 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11299 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27613 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297840 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297840 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1015499 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1078979 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 227 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2095725 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3605435 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 949566 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 535407 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7186133 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 89403712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118812032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40502976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17791322 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266510042 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 398828 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2782920 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.138526 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.345713 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2479819 86.31% 86.31% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 393117 13.68% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2397661 86.16% 86.16% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 385012 13.83% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 245 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2873172 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4223704496 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2782920 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4214914494 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 296383 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1031139756 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1048435504 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1802215285 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1811762602 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 499214310 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 476230655 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 293827886 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 281513896 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index b4533a137..2fb77dfab 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.941276 # Nu sim_ticks 1941275996000 # Number of ticks simulated final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1048317 # Simulator instruction rate (inst/s) -host_op_rate 1048317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36222399744 # Simulator tick rate (ticks/s) -host_mem_usage 330588 # Number of bytes of host memory used -host_seconds 53.59 # Real time elapsed on the host +host_inst_rate 855166 # Simulator instruction rate (inst/s) +host_op_rate 855166 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29548473540 # Simulator tick rate (ticks/s) +host_mem_usage 325188 # Number of bytes of host memory used +host_seconds 65.70 # Real time elapsed on the host sim_insts 56182685 # Number of instructions simulated sim_ops 56182685 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index b93cd163b..85c0f1360 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1211130 # Simulator instruction rate (inst/s) -host_op_rate 1474356 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23615387886 # Simulator tick rate (ticks/s) -host_mem_usage 581436 # Number of bytes of host memory used -host_seconds 117.88 # Real time elapsed on the host +host_inst_rate 1008697 # Simulator instruction rate (inst/s) +host_op_rate 1227927 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19668230366 # Simulator tick rate (ticks/s) +host_mem_usage 576064 # Number of bytes of host memory used +host_seconds 141.54 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 4464ff885..9e43d8fd4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.802883 # Number of seconds simulated -sim_ticks 2802882879000 # Number of ticks simulated -final_tick 2802882879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2802882797500 # Number of ticks simulated +final_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1338296 # Simulator instruction rate (inst/s) -host_op_rate 1630694 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25547394462 # Simulator tick rate (ticks/s) -host_mem_usage 592020 # Number of bytes of host memory used -host_seconds 109.71 # Real time elapsed on the host -sim_insts 146828562 # Number of instructions simulated -sim_ops 178908371 # Number of ops (including micro ops) simulated +host_inst_rate 797664 # Simulator instruction rate (inst/s) +host_op_rate 971941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15227033289 # Simulator tick rate (ticks/s) +host_mem_usage 590380 # Number of bytes of host memory used +host_seconds 184.07 # Real time elapsed on the host +sim_insts 146828219 # Number of instructions simulated +sim_ops 178907974 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1109732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9413156 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 152660 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1082192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081872 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11759340 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1109732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 152660 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1262392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8477312 # Number of bytes written to this memory +system.physmem.bytes_read::total 11758444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1109284 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1263160 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8475520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8494876 # Number of bytes written to this memory +system.physmem.bytes_written::total 8493084 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147579 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16924 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132458 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192873 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132430 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136849 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136821 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 395925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3358384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 395765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3357904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385985 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4195445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 395925 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54465 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 450391 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3024497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4195125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 395765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 450665 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3023858 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3030764 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3024497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3030125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3023858 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 395925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3364636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 395765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3364156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7226208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -138,9 +138,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339777 # DTB read hits +system.cpu0.dtb.read_hits 20339693 # DTB read hits system.cpu0.dtb.read_misses 6871 # DTB read misses -system.cpu0.dtb.write_hits 16391027 # DTB write hits +system.cpu0.dtb.write_hits 16391003 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -151,12 +151,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346648 # DTB read accesses -system.cpu0.dtb.write_accesses 16392120 # DTB write accesses +system.cpu0.dtb.read_accesses 20346564 # DTB read accesses +system.cpu0.dtb.write_accesses 16392096 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36730804 # DTB hits +system.cpu0.dtb.hits 36730696 # DTB hits system.cpu0.dtb.misses 7964 # DTB misses -system.cpu0.dtb.accesses 36738768 # DTB accesses +system.cpu0.dtb.accesses 36738660 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -204,7 +204,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 97439598 # ITB inst hits +system.cpu0.itb.inst_hits 97439155 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -221,39 +221,39 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97442956 # ITB inst accesses -system.cpu0.itb.hits 97439598 # DTB hits +system.cpu0.itb.inst_accesses 97442513 # ITB inst accesses +system.cpu0.itb.hits 97439155 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97442956 # DTB accesses -system.cpu0.numCycles 5605767724 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442513 # DTB accesses +system.cpu0.numCycles 5605767562 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed -system.cpu0.committedInsts 95427136 # Number of instructions committed -system.cpu0.committedOps 115560651 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100762921 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1966 # number of quiesce instructions executed +system.cpu0.committedInsts 95426725 # Number of instructions committed +system.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000357 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204240 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100762921 # number of integer instructions +system.cpu0.num_func_calls 8000241 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204192 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762477 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182457857 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69135716 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182456959 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135393 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349972220 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907498 # number of times the CC registers were written -system.cpu0.num_mem_refs 37873797 # number of memory refs -system.cpu0.num_load_insts 20597358 # Number of load instructions -system.cpu0.num_store_insts 17276439 # Number of store instructions -system.cpu0.num_idle_cycles 5488182951.223861 # Number of idle cycles -system.cpu0.num_busy_cycles 117584772.776139 # Number of busy cycles +system.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907357 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873679 # number of memory refs +system.cpu0.num_load_insts 20597264 # Number of load instructions +system.cpu0.num_store_insts 17276415 # Number of store instructions +system.cpu0.num_idle_cycles 5488183302.205065 # Number of idle cycles +system.cpu0.num_busy_cycles 117584259.794936 # Number of busy cycles system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941714 # Number of branches fetched +system.cpu0.Branches 21941548 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78887557 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887162 67.49% 67.50% # Class of executed instruction system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction @@ -282,18 +282,18 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597358 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276439 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116882349 # Class of executed instruction -system.cpu0.dcache.tags.replacements 693475 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853481 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932424 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.776797 # Average number of references to valid blocks. +system.cpu0.op_class::total 116881836 # Class of executed instruction +system.cpu0.dcache.tags.replacements 693478 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932313 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.776413 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853481 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -301,60 +301,60 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113882 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113882 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108626 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108626 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690357 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690357 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798983 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798983 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145063 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145063 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373096 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373096 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295789 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295789 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.tags.tag_accesses 74113669 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113669 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108530 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108530 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690319 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690319 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798849 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798849 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35144934 # number of overall hits +system.cpu0.dcache.overall_hits::total 35144934 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295799 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668885 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668885 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769207 # number of overall misses -system.cpu0.dcache.overall_misses::total 769207 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481722 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986146 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986146 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467868 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467868 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914270 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914270 # number of overall (read+write) accesses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18431 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18431 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses +system.cpu0.dcache.overall_misses::total 769220 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481630 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481630 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986118 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986118 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35467748 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467748 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914154 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914154 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224730 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224730 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048315 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048315 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses @@ -365,13 +365,13 @@ system.cpu0.dcache.blocked::no_mshrs 0 # nu system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 693475 # number of writebacks -system.cpu0.dcache.writebacks::total 693475 # number of writebacks -system.cpu0.icache.tags.replacements 1109624 # number of replacements +system.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks +system.cpu0.dcache.writebacks::total 693478 # number of writebacks +system.cpu0.icache.tags.replacements 1109639 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96331795 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1110136 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.774769 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110151 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.773184 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy @@ -381,26 +381,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195994025 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195994025 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96331795 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96331795 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96331795 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96331795 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96331795 # number of overall hits -system.cpu0.icache.overall_hits::total 96331795 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1110145 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1110145 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1110145 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1110145 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1110145 # number of overall misses -system.cpu0.icache.overall_misses::total 1110145 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441940 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97441940 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97441940 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97441940 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97441940 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97441940 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331337 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331337 # number of overall hits +system.cpu0.icache.overall_hits::total 96331337 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110160 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1110160 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1110160 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1110160 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1110160 # number of overall misses +system.cpu0.icache.overall_misses::total 1110160 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441497 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441497 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441497 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441497 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441497 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441497 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses @@ -413,185 +413,186 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1109624 # number of writebacks -system.cpu0.icache.writebacks::total 1109624 # number of writebacks +system.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks +system.cpu0.icache.writebacks::total 1109639 # number of writebacks system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 249486 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16123.886747 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2730668 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 265599 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.281168 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 249747 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 265865 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.267963 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 16122.057477 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.758477 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070793 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.984012 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000107 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984124 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16108 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 16129.097151 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.376905 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076379 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.984442 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984592 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16110 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5529 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7406 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2667 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983154 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 59695806 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 59695806 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10175 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4509 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14684 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 510631 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 510631 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1264603 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1264603 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94360 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94360 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068362 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1068362 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352230 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 352230 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10175 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4509 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1068362 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446590 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1529636 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10175 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4509 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1068362 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446590 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1529636 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 118 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 334 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26269 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26269 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175160 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175160 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41783 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 41783 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127928 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 127928 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 118 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 41783 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303088 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 345205 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 118 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 41783 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303088 # number of overall misses -system.cpu0.l2cache.overall_misses::total 345205 # number of overall misses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5562 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7431 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2624 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 510228 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 510228 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1265023 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1265023 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94248 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94248 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068491 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1068491 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352197 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 352197 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10179 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4500 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1068491 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446445 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1529615 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10179 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4500 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1068491 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446445 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1529615 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 212 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 127 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 339 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26279 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26279 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18431 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18431 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175272 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175272 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41669 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 41669 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127964 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 127964 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 212 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 127 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 41669 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303236 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 345244 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 212 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 127 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 41669 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303236 # number of overall misses +system.cpu0.l2cache.overall_misses::total 345244 # number of overall misses system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10391 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 15018 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510631 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 510631 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1264603 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1264603 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26269 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26269 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510228 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 510228 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1265023 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1265023 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26279 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26279 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18431 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18431 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269520 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269520 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110145 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1110145 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480158 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 480158 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110160 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1110160 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480161 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 480161 # number of ReadSharedReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10391 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1110145 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1874841 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110160 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749681 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1874859 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10391 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1110145 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1874841 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025502 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.022240 # miss rate for ReadReq accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110160 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749681 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1874859 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027448 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.022573 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649896 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649896 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037637 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037637 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266429 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266429 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025502 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037637 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404291 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.184125 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025502 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037637 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404291 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.184125 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650312 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650312 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037534 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037534 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266502 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266502 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027448 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037534 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404487 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.184144 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027448 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037534 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404487 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.184144 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l2cache.writebacks::writebacks 193020 # number of writebacks -system.cpu0.l2cache.writebacks::total 193020 # number of writebacks -system.cpu0.toL2Bus.snoop_filter.tot_requests 3720001 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860202 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 218277 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215192 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3085 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.l2cache.writebacks::writebacks 193031 # number of writebacks +system.cpu0.l2cache.writebacks::total 193031 # number of writebacks +system.cpu0.toL2Bus.snoop_filter.tot_requests 3720034 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860217 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 510631 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1292468 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26269 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 510228 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1292889 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26279 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18431 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44710 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269520 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269520 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110145 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480158 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347958 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402091 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110160 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480161 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348003 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402094 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5791673 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142101304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552324 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5791721 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142103224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552708 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 234736876 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 623160 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4317939 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.067042 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.252935 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 234739180 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 623521 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4318336 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.067052 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.252886 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4031542 93.37% 93.37% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 283312 6.56% 99.93% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3085 0.07% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031799 93.36% 93.36% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 283523 6.57% 99.93% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3014 0.07% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4317939 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -641,9 +642,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173929 # DTB read hits +system.cpu1.dtb.read_hits 12173945 # DTB read hits system.cpu1.dtb.read_misses 2853 # DTB read misses -system.cpu1.dtb.write_hits 7587213 # DTB write hits +system.cpu1.dtb.write_hits 7587221 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -654,12 +655,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176782 # DTB read accesses -system.cpu1.dtb.write_accesses 7587719 # DTB write accesses +system.cpu1.dtb.read_accesses 12176798 # DTB read accesses +system.cpu1.dtb.write_accesses 7587727 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761142 # DTB hits +system.cpu1.dtb.hits 19761166 # DTB hits system.cpu1.dtb.misses 3359 # DTB misses -system.cpu1.dtb.accesses 19764501 # DTB accesses +system.cpu1.dtb.accesses 19764525 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -707,7 +708,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 53671686 # ITB inst hits +system.cpu1.itb.inst_hits 53671758 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -724,39 +725,39 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673420 # ITB inst accesses -system.cpu1.itb.hits 53671686 # DTB hits +system.cpu1.itb.inst_accesses 53673492 # ITB inst accesses +system.cpu1.itb.hits 53671758 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673420 # DTB accesses -system.cpu1.numCycles 5605296633 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673492 # DTB accesses +system.cpu1.numCycles 5605296470 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed -system.cpu1.committedInsts 51401426 # Number of instructions committed -system.cpu1.committedOps 63347720 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984340 # Number of integer alu accesses +system.cpu1.committedInsts 51401494 # Number of instructions committed +system.cpu1.committedOps 63347804 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984416 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170857 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967107 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984340 # number of integer instructions +system.cpu1.num_func_calls 9170873 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967115 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984416 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110674879 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298438 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110675031 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298494 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196268976 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894428 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026400 # number of memory refs -system.cpu1.num_load_insts 12289552 # Number of load instructions -system.cpu1.num_store_insts 7736848 # Number of store instructions -system.cpu1.num_idle_cycles 5539683011.597479 # Number of idle cycles -system.cpu1.num_busy_cycles 65613621.402521 # Number of busy cycles +system.cpu1.num_cc_register_reads 196269240 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894452 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026424 # number of memory refs +system.cpu1.num_load_insts 12289568 # Number of load instructions +system.cpu1.num_store_insts 7736856 # Number of store instructions +system.cpu1.num_idle_cycles 5539682760.605002 # Number of idle cycles +system.cpu1.num_busy_cycles 65613709.394997 # Number of busy cycles system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217504 # Number of branches fetched +system.cpu1.Branches 15217528 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401392 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401456 69.36% 69.36% # Class of executed instruction system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction @@ -785,80 +786,80 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289552 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736848 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289568 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736856 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459571 # Class of executed instruction +system.cpu1.op_class::total 65459659 # Class of executed instruction system.cpu1.dcache.tags.replacements 191946 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503521 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.422366 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.422491 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736015 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39752021 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39752021 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858700 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858700 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397505 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397505 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397520 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72417 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72417 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256205 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256205 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306305 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306305 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72399 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72399 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256236 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256236 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306336 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306336 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136638 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136638 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92461 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92461 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92454 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92454 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22562 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22562 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229099 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229099 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses -system.cpu1.dcache.overall_misses::total 259817 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995338 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995338 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489966 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489966 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22580 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22580 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259810 # number of overall misses +system.cpu1.dcache.overall_misses::total 259810 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995354 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995354 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489974 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489974 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485304 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485304 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566122 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566122 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 19485328 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485328 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566146 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566146 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012344 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.012344 # miss rate for WriteReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237547 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237547 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237737 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237737 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -871,9 +872,9 @@ system.cpu1.dcache.writebacks::writebacks 191946 # n system.cpu1.dcache.writebacks::total 191946 # number of writebacks system.cpu1.icache.tags.replacements 523401 # number of replacements system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148863 # Total number of references to valid blocks. +system.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.445971 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.446108 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy @@ -882,26 +883,26 @@ system.cpu1.icache.tags.occ_task_id_blocks::1024 512 system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107869465 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107869465 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148863 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148863 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148863 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148863 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148863 # number of overall hits -system.cpu1.icache.overall_hits::total 53148863 # number of overall hits +system.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148935 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148935 # number of overall hits +system.cpu1.icache.overall_hits::total 53148935 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 523913 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 523913 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 523913 # number of overall misses system.cpu1.icache.overall_misses::total 523913 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672776 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672776 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672776 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672776 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672776 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672776 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672848 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672848 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672848 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672848 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672848 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672848 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses @@ -922,88 +923,88 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 47378 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15226.816500 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1184475 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62425 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 18.974369 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 47503 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62526 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 18.950469 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 15223.544149 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 1.255151 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.017200 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.929171 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000077 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 15227.338556 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 0.619660 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015081 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.929403 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000038 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.929371 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15027 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::total 0.929564 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15005 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9441 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5060 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.917175 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24501973 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24501973 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3627 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1923 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 5550 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 121108 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 121108 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 583081 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 583081 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19862 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19862 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510444 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 510444 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99124 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 99124 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3627 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1923 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510444 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 118986 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634980 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3627 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1923 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510444 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 118986 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634980 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 268 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 606 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22562 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22562 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43753 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43753 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13469 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13469 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73550 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 73550 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 268 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13469 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117303 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131378 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 268 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13469 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117303 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131378 # number of overall misses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9469 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5007 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 121092 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 121092 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 583097 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 583097 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19779 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19779 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510372 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 510372 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99144 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 99144 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1918 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510372 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 118923 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634834 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1918 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510372 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 118923 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634834 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 273 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 617 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28839 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28839 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22580 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22580 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43836 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43836 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13541 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 13541 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73530 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73530 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 273 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13541 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117366 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131524 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 273 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13541 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117366 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131524 # number of overall misses system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121108 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 121108 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 583081 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 583081 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22562 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22562 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 121092 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 121092 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 583097 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 583097 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28839 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28839 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22580 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22580 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523913 # number of ReadCleanReq accesses(hits+misses) @@ -1020,78 +1021,78 @@ system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 system.cpu1.l2cache.overall_accesses::cpu1.inst 523913 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236289 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 766358 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.122319 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.098441 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124601 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.100227 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.687778 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.687778 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025708 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025708 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425947 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425947 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.122319 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025708 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496439 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171432 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.122319 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025708 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496439 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171432 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689083 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689083 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025846 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025846 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425831 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425831 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124601 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025846 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496705 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171622 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124601 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025846 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496705 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171622 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l2cache.writebacks::writebacks 32706 # number of writebacks -system.cpu1.l2cache.writebacks::total 32706 # number of writebacks -system.cpu1.toL2Bus.snoop_filter.tot_requests 1533509 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773310 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.writebacks::writebacks 32790 # number of writebacks +system.cpu1.l2cache.writebacks::total 32790 # number of writebacks +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533520 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773321 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 166217 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164146 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2071 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 121108 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 594239 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22562 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51408 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 121092 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 594255 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28839 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22580 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523913 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172674 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571581 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778800 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778822 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2369077 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2369099 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67028804 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27426222 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size::total 94492418 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 347790 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1820349 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.108308 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.314409 # Request fanout histogram +system.cpu1.toL2Bus.snoops 347973 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1820541 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.108229 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.314122 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1625261 89.28% 89.28% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 193017 10.60% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2071 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1625468 89.28% 89.28% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 193110 10.61% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1963 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1820349 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1143,12 +1144,12 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 246641287009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1188,225 +1189,231 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.l2c.tags.replacements 107729 # number of replacements -system.l2c.tags.tagsinuse 62410.633039 # Cycle average of tags in use -system.l2c.tags.total_refs 243914 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168410 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.448334 # Average number of references to valid blocks. +system.l2c.tags.replacements 107745 # number of replacements +system.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use +system.l2c.tags.total_refs 243993 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168404 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.448855 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48132.772899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010469 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48109.911781 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010811 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030814 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7764.318269 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4071.663088 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1666.007629 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 770.829870 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.734448 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 7778.233869 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4058.534945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1666.123091 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 768.911224 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.734099 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.118474 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.062129 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025421 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011762 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.952311 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.118686 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.061928 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025423 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011733 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.951946 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60675 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60653 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1869 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45497 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45523 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.925827 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5179303 # Number of tag accesses -system.l2c.tags.data_accesses 5179303 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 225726 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 225726 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 564 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 115 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 679 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 81 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 38 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 119 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3040 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16940 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 77 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 58 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 25005 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76077 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 34 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11094 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11733 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 124113 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 77 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 58 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 25005 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89977 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11094 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14773 # number of demand (read+write) hits -system.l2c.demand_hits::total 141053 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 77 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 58 # number of overall hits -system.l2c.overall_hits::cpu0.inst 25005 # number of overall hits -system.l2c.overall_hits::cpu0.data 89977 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11094 # number of overall hits -system.l2c.overall_hits::cpu1.data 14773 # number of overall hits -system.l2c.overall_hits::total 141053 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9970 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3255 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13225 # number of UpgradeReq misses +system.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5181909 # Number of tag accesses +system.l2c.tags.data_accesses 5181909 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 103 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 660 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 84 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 42 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 126 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 14022 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3121 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17143 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 71 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 67 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 24898 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76097 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 38 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11147 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11696 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 124060 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 67 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 24898 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 90119 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11147 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14817 # number of demand (read+write) hits +system.l2c.demand_hits::total 141203 # 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miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.835112 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.898855 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028986 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402481 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128258 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176796 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.088031 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.202494 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.028986 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.402481 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.621116 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.176796 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.533367 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.565595 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.028986 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.402481 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.621116 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.176796 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.533367 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.565595 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 96268 # number of writebacks -system.l2c.writebacks::total 96268 # number of writebacks +system.l2c.writebacks::writebacks 96240 # number of writebacks +system.l2c.writebacks::total 96240 # number of writebacks +system.membus.snoop_filter.tot_requests 462691 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 248163 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 43996 # Transaction distribution -system.membus.trans_dist::ReadResp 75724 # Transaction distribution +system.membus.trans_dist::ReadResp 75748 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::WritebackDirty 132458 # Transaction distribution -system.membus.trans_dist::CleanEvict 8718 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60357 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40887 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15566 # Transaction distribution -system.membus.trans_dist::ReadExReq 152312 # Transaction distribution -system.membus.trans_dist::ReadExResp 151914 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31728 # Transaction distribution +system.membus.trans_dist::WritebackDirty 132430 # Transaction distribution +system.membus.trans_dist::CleanEvict 8725 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60386 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40885 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15565 # Transaction distribution +system.membus.trans_dist::ReadExReq 152277 # Transaction distribution +system.membus.trans_dist::ReadExResp 151876 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31752 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 738406 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617002 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 738386 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 847800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 847780 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17954824 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18144606 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17952136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18141918 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20476894 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20474206 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 537526 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 537521 # Request fanout histogram +system.membus.snoop_fanout::mean 0.010364 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.101276 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 537526 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 531950 98.96% 98.96% # Request fanout histogram +system.membus.snoop_fanout::1 5571 1.04% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 537526 # Request fanout histogram +system.membus.snoop_fanout::total 537521 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1448,41 +1455,41 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 862694 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 444199 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 128774 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 9862 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 9376 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 486 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 301670 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 225726 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 64248 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60580 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41006 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213448 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213448 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 257670 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1161849 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1585074 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34444668 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10399858 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 44844526 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 180900 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1118187 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.282688 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.451270 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 225821 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 64447 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60576 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41011 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101587 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213650 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213650 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 257660 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162060 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423694 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1585754 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34449020 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10413874 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44862894 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 113289 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1051063 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.300803 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.459644 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 802575 71.77% 71.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 315126 28.18% 99.96% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 486 0.04% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 735400 69.97% 69.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 315163 29.99% 99.95% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 500 0.05% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1118187 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1051063 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index d5c7e4211..491924c10 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783855 # Nu sim_ticks 2783854535000 # Number of ticks simulated final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1225194 # Simulator instruction rate (inst/s) -host_op_rate 1491477 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23889629831 # Simulator tick rate (ticks/s) -host_mem_usage 578692 # Number of bytes of host memory used -host_seconds 116.53 # Real time elapsed on the host +host_inst_rate 888036 # Simulator instruction rate (inst/s) +host_op_rate 1081042 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17315504636 # Simulator tick rate (ticks/s) +host_mem_usage 573724 # Number of bytes of host memory used +host_seconds 160.77 # Real time elapsed on the host sim_insts 142771651 # Number of instructions simulated sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 28d366488..89a189084 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,155 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.871806 # Number of seconds simulated -sim_ticks 2871806231000 # Number of ticks simulated -final_tick 2871806231000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.869789 # Number of seconds simulated +sim_ticks 2869788970000 # Number of ticks simulated +final_tick 2869788970000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 717242 # Simulator instruction rate (inst/s) -host_op_rate 867543 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15665668571 # Simulator tick rate (ticks/s) -host_mem_usage 616200 # Number of bytes of host memory used -host_seconds 183.32 # Real time elapsed on the host -sim_insts 131483712 # Number of instructions simulated -sim_ops 159036662 # Number of ops (including micro ops) simulated +host_inst_rate 543935 # Simulator instruction rate (inst/s) +host_op_rate 657921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11865725522 # Simulator tick rate (ticks/s) +host_mem_usage 611884 # Number of bytes of host memory used +host_seconds 241.86 # Real time elapsed on the host +sim_insts 131553572 # Number of instructions simulated +sim_ops 159121620 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1158756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1268260 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8634112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 543380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 351296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1162532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1281572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8557696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 146452 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 567572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 385664 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12108656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1158756 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151380 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1310136 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8536192 # Number of bytes written to this memory +system.physmem.bytes_read::total 12103024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1162532 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 146452 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1308984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8649280 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8553756 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8666844 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26559 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20336 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2520 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8511 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5489 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26618 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20544 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133714 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6026 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198346 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 133378 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198258 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 135145 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 137769 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 139536 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 403494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 441625 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3006509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52712 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 189212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 122326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4216390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 403494 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52712 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 456206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2972412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 405093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 446574 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2981995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 197775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 134388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4217392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 405093 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 456126 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3013908 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6106 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2978528 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2972412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3020028 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3013908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 403494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 447727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3006509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52712 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 189226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 122326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7194919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198346 # Number of read requests accepted -system.physmem.writeReqs 137769 # Number of write requests accepted -system.physmem.readBursts 198346 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 137769 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12684736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 8566272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12108656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8553756 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu0.inst 405093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 452680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2981995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 197789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 134388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7237420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198258 # Number of read requests accepted +system.physmem.writeReqs 139536 # Number of write requests accepted +system.physmem.readBursts 198258 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 139536 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12678976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue +system.physmem.bytesWritten 8679232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12103024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8666844 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11680 # Per bank write bursts -system.physmem.perBankRdBursts::1 11729 # Per bank write bursts -system.physmem.perBankRdBursts::2 12020 # Per bank write bursts -system.physmem.perBankRdBursts::3 11779 # Per bank write bursts -system.physmem.perBankRdBursts::4 20245 # Per bank write bursts -system.physmem.perBankRdBursts::5 11824 # Per bank write bursts -system.physmem.perBankRdBursts::6 12521 # Per bank write bursts -system.physmem.perBankRdBursts::7 12818 # Per bank write bursts -system.physmem.perBankRdBursts::8 12201 # Per bank write bursts -system.physmem.perBankRdBursts::9 12749 # Per bank write bursts -system.physmem.perBankRdBursts::10 11883 # Per bank write bursts -system.physmem.perBankRdBursts::11 11375 # Per bank write bursts -system.physmem.perBankRdBursts::12 11512 # Per bank write bursts -system.physmem.perBankRdBursts::13 11780 # Per bank write bursts -system.physmem.perBankRdBursts::14 10986 # Per bank write bursts -system.physmem.perBankRdBursts::15 11097 # Per bank write bursts -system.physmem.perBankWrBursts::0 8306 # Per bank write bursts -system.physmem.perBankWrBursts::1 8598 # Per bank write bursts -system.physmem.perBankWrBursts::2 8866 # Per bank write bursts -system.physmem.perBankWrBursts::3 8386 # Per bank write bursts -system.physmem.perBankWrBursts::4 7973 # Per bank write bursts -system.physmem.perBankWrBursts::5 8273 # Per bank write bursts -system.physmem.perBankWrBursts::6 8936 # Per bank write bursts -system.physmem.perBankWrBursts::7 8926 # Per bank write bursts -system.physmem.perBankWrBursts::8 8615 # Per bank write bursts -system.physmem.perBankWrBursts::9 9047 # Per bank write bursts -system.physmem.perBankWrBursts::10 8395 # Per bank write bursts -system.physmem.perBankWrBursts::11 8237 # Per bank write bursts -system.physmem.perBankWrBursts::12 8245 # Per bank write bursts -system.physmem.perBankWrBursts::13 7999 # Per bank write bursts -system.physmem.perBankWrBursts::14 7661 # Per bank write bursts -system.physmem.perBankWrBursts::15 7385 # Per bank write bursts +system.physmem.perBankRdBursts::0 11529 # Per bank write bursts +system.physmem.perBankRdBursts::1 11853 # Per bank write bursts +system.physmem.perBankRdBursts::2 12105 # Per bank write bursts +system.physmem.perBankRdBursts::3 12154 # Per bank write bursts +system.physmem.perBankRdBursts::4 20931 # Per bank write bursts +system.physmem.perBankRdBursts::5 12788 # Per bank write bursts +system.physmem.perBankRdBursts::6 12012 # Per bank write bursts +system.physmem.perBankRdBursts::7 12170 # Per bank write bursts +system.physmem.perBankRdBursts::8 12327 # Per bank write bursts +system.physmem.perBankRdBursts::9 12530 # Per bank write bursts +system.physmem.perBankRdBursts::10 11492 # Per bank write bursts +system.physmem.perBankRdBursts::11 10989 # Per bank write bursts +system.physmem.perBankRdBursts::12 11634 # Per bank write bursts +system.physmem.perBankRdBursts::13 11866 # Per bank write bursts +system.physmem.perBankRdBursts::14 10750 # Per bank write bursts +system.physmem.perBankRdBursts::15 10979 # Per bank write bursts +system.physmem.perBankWrBursts::0 8343 # Per bank write bursts +system.physmem.perBankWrBursts::1 8774 # Per bank write bursts +system.physmem.perBankWrBursts::2 9050 # Per bank write bursts +system.physmem.perBankWrBursts::3 8765 # Per bank write bursts +system.physmem.perBankWrBursts::4 8633 # Per bank write bursts +system.physmem.perBankWrBursts::5 9228 # Per bank write bursts +system.physmem.perBankWrBursts::6 8690 # Per bank write bursts +system.physmem.perBankWrBursts::7 8516 # Per bank write bursts +system.physmem.perBankWrBursts::8 8766 # Per bank write bursts +system.physmem.perBankWrBursts::9 8956 # Per bank write bursts +system.physmem.perBankWrBursts::10 8280 # Per bank write bursts +system.physmem.perBankWrBursts::11 8060 # Per bank write bursts +system.physmem.perBankWrBursts::12 8431 # Per bank write bursts +system.physmem.perBankWrBursts::13 8106 # Per bank write bursts +system.physmem.perBankWrBursts::14 7529 # Per bank write bursts +system.physmem.perBankWrBursts::15 7486 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 23 # Number of times write queue was full causing retry -system.physmem.totGap 2871805791000 # Total gap between requests +system.physmem.numWrRetry 45 # Number of times write queue was full causing retry +system.physmem.totGap 2869788469000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188586 # Read request sizes (log2) +system.physmem.readPktSize::6 188498 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 133378 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 139268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3807 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 135145 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5461 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -180,159 +180,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 81 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87931 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.677497 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.342742 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.582310 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46815 53.24% 53.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17415 19.81% 73.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6112 6.95% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3386 3.85% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2470 2.81% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1473 1.68% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 853 0.97% 89.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 929 1.06% 90.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8478 9.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87931 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6424 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.852584 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 590.448326 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6422 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6424 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6424 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.835616 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.963518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.817635 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5349 83.27% 83.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 441 6.86% 90.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 73 1.14% 91.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 47 0.73% 92.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 38 0.59% 92.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.39% 92.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 52 0.81% 93.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 19 0.30% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 115 1.79% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.17% 96.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 10 0.16% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.16% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 81 1.26% 97.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.14% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 97.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 28 0.44% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 75 1.17% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.08% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.16% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.11% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6424 # Writes before turning the bus around for reads -system.physmem.totQLat 4482627455 # Total ticks spent queuing -system.physmem.totMemAccLat 8198858705 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 990995000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22616.80 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2819 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10382 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 89189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 239.470607 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.176312 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 302.792926 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47900 53.71% 53.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17682 19.83% 73.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5838 6.55% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3495 3.92% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2471 2.77% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1457 1.63% 88.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1048 1.18% 89.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 998 1.12% 90.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8300 9.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 89189 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6684 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.638989 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 578.089254 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6683 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6684 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.289198 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.751921 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.518584 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5662 84.71% 84.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 280 4.19% 88.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 70 1.05% 89.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 0.66% 90.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 285 4.26% 94.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 29 0.43% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 28 0.42% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 27 0.40% 96.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.25% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.15% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.07% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.13% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 159 2.38% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.03% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 11 0.16% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 9 0.13% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.09% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.07% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6684 # Writes before turning the bus around for reads +system.physmem.totQLat 4572923146 # Total ticks spent queuing +system.physmem.totMemAccLat 8287466896 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 990545000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23082.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41366.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41832.86 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing -system.physmem.readRowHits 165480 # Number of row buffer hits during reads -system.physmem.writeRowHits 78635 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.74 # Row buffer hit rate for writes -system.physmem.avgGap 8544116.72 # Average gap between requests -system.physmem.pageHitRate 73.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 342929160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 187114125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 816004800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 442350720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187572184800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85984866225 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647656379000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1923001828830 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.614852 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740877422516 # Time in different power states -system.physmem_0.memoryStateTime::REF 95895800000 # Time in different power states +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing +system.physmem.readRowHits 165757 # Number of row buffer hits during reads +system.physmem.writeRowHits 78775 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.08 # Row buffer hit rate for writes +system.physmem.avgGap 8495676.27 # Average gap between requests +system.physmem.pageHitRate 73.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 348221160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 190001625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 823219800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 453593520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 84729045645 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647547992750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1921532542260 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.573415 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740710561422 # Time in different power states +system.physmem_0.memoryStateTime::REF 95828460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35029624984 # Time in different power states +system.physmem_0.memoryStateTime::ACT 33249852578 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 321829200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 175601250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 729939600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 424984320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187572184800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85018582845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648503996000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1922747118015 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.526158 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742296701194 # Time in different power states -system.physmem_1.memoryStateTime::REF 95895800000 # Time in different power states +system.physmem_1.actEnergy 326047680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 177903000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 722022600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 425178720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187440467760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84061532610 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648133530500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1921286682870 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.487743 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2741691176386 # Time in different power states +system.physmem_1.memoryStateTime::REF 95828460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33613567806 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32266572364 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -388,56 +390,60 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 8733 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 8733 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1652 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7081 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 8733 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 8733 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 8733 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7215 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12160.221760 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11349.326630 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6137.175819 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7184 99.57% 99.57% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 27 0.37% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7215 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5610 77.75% 77.75% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1605 22.25% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7215 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8733 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 7943 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7943 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1501 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6442 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7943 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7943 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7943 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6549 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12300.885631 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11415.801761 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5728.954139 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6064 92.59% 92.59% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 441 6.73% 99.33% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 34 0.52% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6549 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1125817500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1125817500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1125817500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5087 77.68% 77.68% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1462 22.32% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6549 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7943 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8733 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7215 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7943 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6549 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7215 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 15948 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6549 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14492 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25746594 # DTB read hits -system.cpu0.dtb.read_misses 7520 # DTB read misses -system.cpu0.dtb.write_hits 19247313 # DTB write hits -system.cpu0.dtb.write_misses 1213 # DTB write misses +system.cpu0.dtb.read_hits 25156507 # DTB read hits +system.cpu0.dtb.read_misses 6829 # DTB read misses +system.cpu0.dtb.write_hits 18749940 # DTB write hits +system.cpu0.dtb.write_misses 1114 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3753 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3456 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1863 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1731 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25754114 # DTB read accesses -system.cpu0.dtb.write_accesses 19248526 # DTB write accesses +system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25163336 # DTB read accesses +system.cpu0.dtb.write_accesses 18751054 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 44993907 # DTB hits -system.cpu0.dtb.misses 8733 # DTB misses -system.cpu0.dtb.accesses 45002640 # DTB accesses +system.cpu0.dtb.hits 43906447 # DTB hits +system.cpu0.dtb.misses 7943 # DTB misses +system.cpu0.dtb.accesses 43914390 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -467,39 +473,42 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3674 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3674 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3354 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3674 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12667.119565 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11857.484982 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6117.849264 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2266 87.97% 87.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 279 10.83% 98.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 28 1.09% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2256 87.58% 87.58% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 320 12.42% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2576 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3349 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3349 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 299 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3050 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3349 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3349 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3349 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2333 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12856.622375 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 12024.130170 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5718.443506 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 360 15.43% 15.43% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1695 72.65% 88.08% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 216 9.26% 97.34% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.24% 98.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 29 1.24% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::122880-131071 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2333 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 1125441500 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1125441500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1125441500 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2034 87.18% 87.18% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 299 12.82% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2333 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3674 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3674 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3349 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3349 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 121577578 # ITB inst hits -system.cpu0.itb.inst_misses 3674 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2333 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2333 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5682 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 119016789 # ITB inst hits +system.cpu0.itb.inst_misses 3349 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -508,768 +517,763 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 121581252 # ITB inst accesses -system.cpu0.itb.hits 121577578 # DTB hits -system.cpu0.itb.misses 3674 # DTB misses -system.cpu0.itb.accesses 121581252 # DTB accesses -system.cpu0.numCycles 5743612462 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 119020138 # ITB inst accesses +system.cpu0.itb.hits 119016789 # DTB hits +system.cpu0.itb.misses 3349 # DTB misses +system.cpu0.itb.accesses 119020138 # DTB accesses +system.cpu0.numCycles 5739577940 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed -system.cpu0.committedInsts 117761026 # Number of instructions committed -system.cpu0.committedOps 142319020 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 125932364 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses -system.cpu0.num_func_calls 12772321 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16008283 # number of instructions that are conditional controls -system.cpu0.num_int_insts 125932364 # number of integer instructions -system.cpu0.num_fp_insts 11483 # number of float instructions -system.cpu0.num_int_register_reads 231711074 # number of times the integer registers were read -system.cpu0.num_int_register_writes 87448067 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 515452324 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 53494266 # number of times the CC registers were written -system.cpu0.num_mem_refs 46150372 # number of memory refs -system.cpu0.num_load_insts 26005626 # Number of load instructions -system.cpu0.num_store_insts 20144746 # Number of store instructions -system.cpu0.num_idle_cycles 5456042423.958100 # Number of idle cycles -system.cpu0.num_busy_cycles 287570038.041900 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050068 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949932 # Percentage of idle cycles -system.cpu0.Branches 29545974 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 99839256 68.33% 68.33% # Class of executed instruction -system.cpu0.op_class::IntMult 112113 0.08% 68.41% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8315 0.01% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::MemRead 26005626 17.80% 86.21% # Class of executed instruction -system.cpu0.op_class::MemWrite 20144746 13.79% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 1866 # number of quiesce instructions executed +system.cpu0.committedInsts 115352403 # Number of instructions committed +system.cpu0.committedOps 139380192 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123360698 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 9756 # Number of float alu accesses +system.cpu0.num_func_calls 12675179 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15700187 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123360698 # number of integer instructions +system.cpu0.num_fp_insts 9756 # number of float instructions +system.cpu0.num_int_register_reads 227087076 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85717148 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 7496 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 504942673 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52291767 # number of times the CC registers were written +system.cpu0.num_mem_refs 45042977 # number of memory refs +system.cpu0.num_load_insts 25408336 # Number of load instructions +system.cpu0.num_store_insts 19634641 # Number of store instructions +system.cpu0.num_idle_cycles 5464040817.996096 # Number of idle cycles +system.cpu0.num_busy_cycles 275537122.003904 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048007 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951993 # Percentage of idle cycles +system.cpu0.Branches 29113703 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 97981864 68.45% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 109763 0.08% 68.53% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8197 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::MemRead 25408336 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19634641 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146112371 # Class of executed instruction -system.cpu0.dcache.tags.replacements 733230 # number of replacements -system.cpu0.dcache.tags.tagsinuse 488.702331 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 44081285 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 733742 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 60.077364 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.702331 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954497 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.954497 # Average percentage of cache occupancy +system.cpu0.op_class::total 143145074 # Class of executed instruction +system.cpu0.dcache.tags.replacements 692159 # number of replacements +system.cpu0.dcache.tags.tagsinuse 489.914647 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43035504 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 692671 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.129790 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1151827000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 489.914647 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.956865 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.956865 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 90665231 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 90665231 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 24440591 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 24440591 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18493820 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18493820 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326163 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 326163 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374037 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374037 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371586 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 371586 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 42934411 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 42934411 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 43260574 # number of overall hits -system.cpu0.dcache.overall_hits::total 43260574 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 418663 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 418663 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 337563 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 337563 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133473 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 133473 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22401 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22401 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19896 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19896 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 756226 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 756226 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 889699 # number of overall misses -system.cpu0.dcache.overall_misses::total 889699 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5670544000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5670544000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6922080500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6922080500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 345375500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 345375500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 506120500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 506120500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1857000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1857000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 12592624500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 12592624500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 12592624500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 12592624500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24859254 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24859254 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18831383 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18831383 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459636 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 459636 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396438 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 396438 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391482 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 391482 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 43690637 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 43690637 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 44150273 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 44150273 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016841 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016841 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017926 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017926 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290388 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290388 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056506 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056506 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050822 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050822 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017309 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.017309 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020152 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.020152 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13544.411615 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13544.411615 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20506.040354 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20506.040354 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.860810 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.860810 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25438.304182 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25438.304182 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88449495 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88449495 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23895287 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23895287 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18018355 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18018355 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 319106 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 319106 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365501 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365501 # 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number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21584 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19801 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19801 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 721136 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 721136 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 848828 # number of overall misses +system.cpu0.dcache.overall_misses::total 848828 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5078700000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5078700000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5729362000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5729362000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329182500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 329182500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472585500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 472585500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1446500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1446500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10808062000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10808062000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10808062000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10808062000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24291383 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24291383 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18343395 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18343395 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446798 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446798 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387085 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387085 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382166 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42634778 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42634778 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43081576 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43081576 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016306 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016306 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017720 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017720 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285794 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285794 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055760 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055760 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051813 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051813 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016914 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016914 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019703 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019703 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12821.891663 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12821.891663 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17626.636722 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17626.636722 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15251.227761 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15251.227761 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23866.749154 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23866.749154 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16651.932756 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16651.932756 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14153.803140 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14153.803140 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14987.550199 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14987.550199 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12732.923513 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12732.923513 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 733230 # number of writebacks -system.cpu0.dcache.writebacks::total 733230 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25285 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25285 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15695 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15695 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25286 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25286 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25286 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25286 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 393378 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 393378 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337562 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 337562 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106333 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 106333 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6706 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6706 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19896 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19896 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 730940 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 730940 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 837273 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 837273 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31817 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31817 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60316 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60316 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4848200000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4848200000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6584514000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6584514000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1737943000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737943000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103994500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103994500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 486281500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 486281500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1800000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1800000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432714000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11432714000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13170657000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13170657000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628843000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628843000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628843000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628843000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015824 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015824 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017926 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017926 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231342 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231342 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016916 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016916 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050822 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050822 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016730 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016730 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018964 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018964 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12324.532638 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12324.532638 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19506.087771 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19506.087771 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16344.342772 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16344.342772 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15507.679690 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15507.679690 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24441.169079 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24441.169079 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 692159 # number of writebacks +system.cpu0.dcache.writebacks::total 692159 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25284 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25284 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15032 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15032 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25284 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25284 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25284 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25284 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 370812 # 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number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9717255000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9717255000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11332682000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11332682000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6628901000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6628901000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6628901000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6628901000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015265 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015265 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017720 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017720 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224894 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224894 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016927 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016927 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051813 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051813 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016321 # 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average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15078.678266 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22868.819757 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22868.819757 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15641.111446 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15641.111446 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15730.421260 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15730.421260 # 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Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 214 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 244302703 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 244302703 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 120430031 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 120430031 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 120430031 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 120430031 # 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number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11668210000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11668210000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11668210000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11668210000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11668210000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11668210000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 811416500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 811416500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 811416500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009279 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009279 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009279 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009279 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9486.096548 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9486.096548 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9486.096548 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89937.541565 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89937.541565 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89937.541565 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853175 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1853224 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 43 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 246453 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 273594 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16077.204583 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3064483 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 289692 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.578418 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 238416 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 266444 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16079.510665 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2925486 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 282538 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.354310 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14597.123435 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.512757 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.144663 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1477.423728 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.890938 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000153 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090175 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981275 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1029 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15061 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 254 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 333 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 432 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14606.769244 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.268403 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.133561 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1470.339456 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.891526 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000138 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.089742 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.981415 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1047 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 289 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 351 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 399 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3292 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7648 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3847 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062805 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.919250 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 62842008 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 62842008 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 11176 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4956 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 16132 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 502092 # 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number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4956 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1101688 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 650901 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1768721 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 11176 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4956 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1101688 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 650901 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1768721 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 156 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 75 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 231 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55191 # 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number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 162363000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 162363000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 41658000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 41658000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1712496 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1712496 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2783886000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2783886000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3283750500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3283750500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3241501500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3241501500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4297500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2025500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3283750500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6025387500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 9315461000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4297500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2025500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3283750500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6025387500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 9315461000 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11332 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5031 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 16363 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 502092 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 502092 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1349261 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1349261 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55192 # 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mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181580 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228797 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21372.294372 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77179.151703 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25500.788172 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25500.788172 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16968.067988 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16968.067988 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 137049.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 137049.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56538.614908 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.614908 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65605.366449 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28270.224035 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28270.224035 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44123.948519 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21548.076923 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21006.666667 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65605.366449 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36920.891101 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77179.151703 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63704.390920 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200329.807964 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185119.738485 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105675.003316 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109032.637226 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 3905427 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969134 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28903 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 319838 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316964 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2874 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 63699 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1766064 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 734457 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1378164 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 189732 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 311664 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 85807 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41981 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112714 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 301438 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 298033 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147547 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575765 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3263 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460164 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2683424 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12059 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27146 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6182793 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146888760 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101708758 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20124 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 45328 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 248662970 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 986506 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2981817 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.122538 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.330833 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.236165 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 18561.475410 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53108.869237 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19237.556274 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19237.556274 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15382.999141 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15382.999141 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 548749.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 548749.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40410.571936 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40410.571936 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 47359.606890 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23755.558388 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23755.558388 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33459.182830 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 18997.787611 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17857.142857 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 47359.606890 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28863.987186 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53108.869237 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45024.974490 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200495.423377 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174398.539717 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82437.541565 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105786.250104 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 102745.528819 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 3735263 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1883109 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27957 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 316049 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 311748 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 61613 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1692022 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28463 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28463 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 705040 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1319203 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 185302 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 307927 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87515 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42104 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112492 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 289204 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285566 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1104402 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 556293 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3323 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3330729 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2559536 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11112 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 24847 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5926224 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 141366200 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 96437860 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 18852 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 41848 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 237864760 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 984362 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2894410 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.124539 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.334666 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2619305 87.84% 87.84% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 359638 12.06% 99.90% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 2874 0.10% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2538244 87.69% 87.69% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 351865 12.16% 99.85% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4301 0.15% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2981817 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3886437494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2894410 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3716866999 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115091926 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114649584 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1730342500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1665625000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1266858980 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1205216982 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 15821984 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 14392485 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1300,65 +1304,64 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 2347 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2347 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 475 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1872 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2347 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2347 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2347 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1701 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11647.854203 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11021.395784 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4763.004778 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-4095 3 0.18% 0.18% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-8191 360 21.16% 21.34% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-12287 989 58.14% 79.48% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-16383 206 12.11% 91.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-20479 34 2.00% 93.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::20480-24575 60 3.53% 97.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-28671 28 1.65% 98.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::28672-32767 11 0.65% 99.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-36863 1 0.06% 99.47% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::36864-40959 2 0.12% 99.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.18% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.18% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-61439 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1701 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1226 72.08% 72.08% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 475 27.92% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1701 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2347 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 3352 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3352 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 656 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2696 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3352 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3352 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3352 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2582 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11816.227730 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11080.373538 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4768.875507 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 5 0.19% 0.19% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 626 24.24% 24.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1198 46.40% 70.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 544 21.07% 91.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 85 3.29% 95.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 56 2.17% 97.37% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 31 1.20% 98.57% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 20 0.77% 99.34% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-36863 3 0.12% 99.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 8 0.31% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-45055 3 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-53247 3 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2582 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -2078115828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -2078115828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -2078115828 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1934 74.90% 74.90% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 648 25.10% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2582 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3352 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2347 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1701 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3352 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2582 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1701 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 4048 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5934 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3334777 # DTB read hits -system.cpu1.dtb.read_misses 1951 # DTB read misses -system.cpu1.dtb.write_hits 2915290 # DTB write hits -system.cpu1.dtb.write_misses 396 # DTB write misses +system.cpu1.dtb.read_hits 3941258 # DTB read hits +system.cpu1.dtb.read_misses 2845 # DTB read misses +system.cpu1.dtb.write_hits 3419362 # DTB write hits +system.cpu1.dtb.write_misses 507 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2044 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 260 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 318 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3336728 # DTB read accesses -system.cpu1.dtb.write_accesses 2915686 # DTB write accesses +system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3944103 # DTB read accesses +system.cpu1.dtb.write_accesses 3419869 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6250067 # DTB hits -system.cpu1.dtb.misses 2347 # DTB misses -system.cpu1.dtb.accesses 6252414 # DTB accesses +system.cpu1.dtb.hits 7360620 # DTB hits +system.cpu1.dtb.misses 3352 # DTB misses +system.cpu1.dtb.accesses 7363972 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1388,44 +1391,45 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1376 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1376 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 134 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1242 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1376 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11302.540712 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5121.103483 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 113 13.80% 13.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 572 69.84% 83.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 87 10.62% 94.26% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 95.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 23 2.81% 98.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 99.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 4 0.49% 99.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1208095828 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 685 83.64% 83.64% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 134 16.36% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 819 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1746 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12335.140018 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11518.936586 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5605.729039 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 174 15.72% 15.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 657 59.35% 75.07% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 169 15.27% 90.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 52 4.70% 95.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 20 1.81% 96.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.45% 98.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.27% 98.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.90% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.18% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -2078939828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -2078939828 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -2078939828 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1376 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1376 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 13921759 # ITB inst hits -system.cpu1.itb.inst_misses 1376 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 16556610 # ITB inst hits +system.cpu1.itb.inst_misses 1746 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1434,642 +1438,640 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 883 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 13923135 # ITB inst accesses -system.cpu1.itb.hits 13921759 # DTB hits -system.cpu1.itb.misses 1376 # DTB misses -system.cpu1.itb.accesses 13923135 # DTB accesses -system.cpu1.numCycles 5742672703 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 16558356 # ITB inst accesses +system.cpu1.itb.hits 16556610 # DTB hits +system.cpu1.itb.misses 1746 # DTB misses +system.cpu1.itb.accesses 16558356 # DTB accesses +system.cpu1.numCycles 5738649789 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2702 # number of quiesce instructions executed -system.cpu1.committedInsts 13722686 # Number of instructions committed -system.cpu1.committedOps 16717642 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 15156242 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 915130 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1497977 # number of instructions that are conditional controls -system.cpu1.num_int_insts 15156242 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 27539507 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10698774 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 61342237 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 5194989 # number of times the CC registers were written -system.cpu1.num_mem_refs 6464220 # number of memory refs -system.cpu1.num_load_insts 3439445 # Number of load instructions -system.cpu1.num_store_insts 3024775 # Number of store instructions -system.cpu1.num_idle_cycles 5696078911.641530 # Number of idle cycles -system.cpu1.num_busy_cycles 46593791.358469 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008114 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991886 # Percentage of idle cycles -system.cpu1.Branches 2464409 # Number of branches fetched -system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 10544854 61.90% 61.90% # Class of executed instruction -system.cpu1.op_class::IntMult 24300 0.14% 62.04% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3186 0.02% 62.06% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.06% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.06% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.06% # Class of executed instruction -system.cpu1.op_class::MemRead 3439445 20.19% 82.25% # Class of executed instruction -system.cpu1.op_class::MemWrite 3024775 17.75% 100.00% # Class of executed instruction +system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed +system.cpu1.committedInsts 16201169 # Number of instructions committed +system.cpu1.committedOps 19741428 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17804295 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses +system.cpu1.num_func_calls 1029080 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1813608 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17804295 # number of integer instructions +system.cpu1.num_fp_insts 1857 # number of float instructions +system.cpu1.num_int_register_reads 32314180 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12487661 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 72166445 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6418557 # number of times the CC registers were written +system.cpu1.num_mem_refs 7593995 # number of memory refs +system.cpu1.num_load_insts 4052758 # Number of load instructions +system.cpu1.num_store_insts 3541237 # Number of store instructions +system.cpu1.num_idle_cycles 5686904242.264484 # Number of idle cycles +system.cpu1.num_busy_cycles 51745546.735515 # Number of busy cycles +system.cpu1.not_idle_fraction 0.009017 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.990983 # Percentage of idle cycles +system.cpu1.Branches 2921126 # Number of branches fetched +system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 12468405 62.06% 62.06% # Class of executed instruction +system.cpu1.op_class::IntMult 26465 0.13% 62.19% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3319 0.02% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.20% # Class of executed instruction +system.cpu1.op_class::MemRead 4052758 20.17% 82.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 3541237 17.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 17036584 # Class of executed instruction -system.cpu1.dcache.tags.replacements 148452 # number of replacements -system.cpu1.dcache.tags.tagsinuse 468.602887 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6022671 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 148794 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.476572 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106290860000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.602887 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.915240 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.915240 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 36 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.667969 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12680857 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12680857 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3066042 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3066042 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2748534 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2748534 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41898 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 41898 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69885 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 69885 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61599 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61599 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5814576 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5814576 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5856474 # number of overall hits -system.cpu1.dcache.overall_hits::total 5856474 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 112908 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 112908 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 79472 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 79472 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24389 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 24389 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16600 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16600 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23097 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23097 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 192380 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 192380 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 216769 # number of overall misses -system.cpu1.dcache.overall_misses::total 216769 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1761858500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1761858500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2707072000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2707072000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 321180000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 321180000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 626224500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 626224500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5032000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5032000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4468930500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4468930500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4468930500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4468930500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3178950 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3178950 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2828006 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2828006 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66287 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 66287 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86485 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 86485 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84696 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 84696 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6006956 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6006956 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6073243 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6073243 # number of overall (read+write) accesses +system.cpu1.op_class::total 20092250 # Class of executed instruction +system.cpu1.dcache.tags.replacements 186389 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.298921 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7093769 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 186755 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.984359 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 127433218000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.298921 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916599 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.916599 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 285 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14939866 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14939866 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3629400 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3629400 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3230955 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3230955 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48929 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48929 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78822 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78822 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70747 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70747 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6860355 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6860355 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6909284 # number of overall hits +system.cpu1.dcache.overall_hits::total 6909284 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133654 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133654 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 91683 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 91683 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30306 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30306 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17079 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17079 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23334 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23334 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 225337 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 225337 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255643 # number of overall misses +system.cpu1.dcache.overall_misses::total 255643 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1974580500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1974580500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2414638500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2414638500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320455500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 320455500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 569715000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 569715000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3416500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3416500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4389219000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4389219000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4389219000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4389219000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3763054 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3763054 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3322638 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3322638 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79235 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79235 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 95901 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 95901 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94081 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94081 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7085692 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7085692 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7164927 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7164927 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035517 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.035517 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028102 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.028102 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.367930 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.367930 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.191941 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.191941 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272705 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272705 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.032026 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.032026 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035692 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035692 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.372587 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15604.372587 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34063.217234 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34063.217234 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19348.192771 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19348.192771 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27112.806858 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27112.806858 # average StoreCondReq miss latency +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027593 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027593 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382482 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382482 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178090 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178090 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248020 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248020 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031802 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031802 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035680 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035680 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.822706 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.822706 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26336.818167 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26336.818167 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18763.130160 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18763.130160 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24415.659553 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24415.659553 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23229.704231 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23229.704231 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20616.095936 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20616.095936 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19478.465587 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19478.465587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17169.329886 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17169.329886 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 148452 # number of writebacks -system.cpu1.dcache.writebacks::total 148452 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 223 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11671 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11671 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 223 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 223 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 223 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112685 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 112685 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79472 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 79472 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23925 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23925 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4929 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4929 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23097 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23097 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 192157 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 192157 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 216082 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 216082 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3082 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3082 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5505 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5505 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1634927500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1634927500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2627600000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2627600000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 437401500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 437401500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 91610500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 91610500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 603174500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 603174500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4985000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4985000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4262527500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4262527500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4699929000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4699929000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439527500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439527500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 439527500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 439527500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035447 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028102 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028102 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360930 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360930 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056993 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056993 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272705 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272705 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031989 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031989 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035579 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035579 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14508.829924 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14508.829924 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33063.217234 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33063.217234 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18282.194357 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18282.194357 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18586.021505 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18586.021505 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26114.841754 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26114.841754 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 186389 # number of writebacks +system.cpu1.dcache.writebacks::total 186389 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 283 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 283 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12013 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12013 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 283 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 283 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 283 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 283 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133371 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133371 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91683 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91683 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29541 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29541 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5066 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5066 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23334 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23334 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225054 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225054 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254595 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254595 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3095 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3095 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2450 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2450 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5545 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5545 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1833975000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1833975000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2322955500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2322955500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 497374500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 497374500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87920500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87920500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 546440000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 546440000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3357500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3357500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4156930500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4156930500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4654305000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4654305000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 443417000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 443417000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 443417000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 443417000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035442 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035442 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027593 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027593 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.372828 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.372828 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.052825 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.052825 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248020 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248020 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031762 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031762 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035534 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035534 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13750.927863 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13750.927863 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25336.818167 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25336.818167 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16836.752310 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16836.752310 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17355.013818 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17355.013818 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23418.188052 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23418.188052 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22182.525227 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22182.525227 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21750.673355 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21750.673355 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142611.129137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142611.129137 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79841.507720 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79841.507720 # average overall mshr uncacheable latency -system.cpu1.icache.tags.replacements 463484 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.310914 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13457758 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463996 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 29.004039 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 106358922000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310914 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18470.813671 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18470.813671 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18281.211336 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18281.211336 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143268.820679 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143268.820679 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 79966.997295 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 79966.997295 # average overall mshr uncacheable latency +system.cpu1.icache.tags.replacements 505464 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.478732 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16050629 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 505976 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 31.722115 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 85269924000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.478732 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973591 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973591 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 28307504 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 28307504 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13457758 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13457758 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13457758 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13457758 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13457758 # number of overall hits -system.cpu1.icache.overall_hits::total 13457758 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463996 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463996 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463996 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463996 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463996 # number of overall misses -system.cpu1.icache.overall_misses::total 463996 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4214067500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4214067500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4214067500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4214067500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4214067500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4214067500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13921754 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13921754 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13921754 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13921754 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13921754 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13921754 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033329 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.033329 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033329 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.033329 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033329 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.033329 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9082.120320 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9082.120320 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9082.120320 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.120320 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9082.120320 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 33619186 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 33619186 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 16050629 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16050629 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16050629 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16050629 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16050629 # number of overall hits +system.cpu1.icache.overall_hits::total 16050629 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 505976 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 505976 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 505976 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 505976 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 505976 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8949.215971 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8949.215971 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8949.215971 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 463484 # number of writebacks -system.cpu1.icache.writebacks::total 463484 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463996 # 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number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 505976 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3982069500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3982069500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3982069500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3982069500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3982069500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3982069500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033329 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.033329 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.033329 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8582.120320 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.120320 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.120320 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.num_hwpf_issued 117918 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 117936 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4275100500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4275100500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4275100500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4275100500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4275100500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4275100500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15776500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15776500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15776500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15776500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030560 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030560 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030560 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030560 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8449.215971 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8449.215971 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8449.215971 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89132.768362 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89132.768362 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89132.768362 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.num_hwpf_issued 197600 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 197600 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 50208 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 31332 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14956.481117 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1042665 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 46454 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 22.445107 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58944 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 44688 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14938.485252 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1161636 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 59377 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 19.563737 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14460.199894 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.270812 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.044709 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 491.965701 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.882581 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000139 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.030027 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.912871 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 960 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14131 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 920 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 423 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1663 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12045 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.058594 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001892 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.862488 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21157161 # 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number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 298 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 646 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29049 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29049 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23092 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23092 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32133 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32133 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8776 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 8776 # 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number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 418310000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14449000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 418310000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 432759000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.092753 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2078,120 +2080,120 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.635821 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.635821 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018914 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451105 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451105 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.499625 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159462 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124642 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.166480 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018914 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.499625 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559981 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559981 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.405101 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405101 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.157091 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.077960 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.119194 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026187 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.446861 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191241 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14013.931889 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44184.581154 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19905.624978 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19905.624978 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18619.565217 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18619.565217 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 926400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 926400 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44732.064878 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44732.064878 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54263.616682 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16588.591834 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16588.591834 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28277.957107 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14073.275862 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13944.630872 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54263.616682 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25996.256868 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44184.581154 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30921.170050 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134498.053212 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134011.046333 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75299.364214 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 76864.132348 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1324952 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 669028 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10089 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 168501 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166697 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1804 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 10096 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 652859 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2423 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2423 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 119114 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 519969 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 86535 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 25223 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 70168 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84814 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57641 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 55180 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463996 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 214635 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391830 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722434 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4408 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7011 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2125683 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59359428 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24498524 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7160 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 83876280 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 355270 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 998881 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.185518 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.393336 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.190741 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14389.830508 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31243.236599 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16651.371664 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16651.371664 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15925.246464 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15925.246464 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 728625 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 728625 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32213.232541 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32213.232541 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34269.924528 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16231.608570 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16231.608570 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23030.875631 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14355.345912 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14430.147059 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34269.924528 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21631.488815 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31243.236599 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24479.662036 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135156.704362 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 132261.308068 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81632.768362 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75439.134355 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75630.723523 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1487204 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 751274 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11138 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 179165 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 176020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 3145 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 12644 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 724299 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 147816 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 578146 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 101473 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30088 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71412 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41204 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85825 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 69105 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66696 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 505976 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 245752 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 247 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1517770 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 838774 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5606 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 10127 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2372277 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 64732868 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29385740 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9128 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16316 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94144052 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 388756 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1114505 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.179300 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.390891 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 815375 81.63% 81.63% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 181702 18.19% 99.82% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1804 0.18% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 917819 82.35% 82.35% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 193541 17.37% 99.72% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 3145 0.28% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 998881 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1279425500 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79453408 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1114505 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1441037000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80111937 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 696171000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 759141000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 318356500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 375865500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 4219000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 6050495 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31021 # Transaction distribution -system.iobus.trans_dist::ReadResp 31021 # Transaction distribution -system.iobus.trans_dist::WriteReq 59425 # Transaction distribution -system.iobus.trans_dist::WriteResp 59425 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 59422 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2210,11 +2212,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2233,23 +2235,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48736000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48726000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 106000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 32500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 32000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 93000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 609000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 601500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2263,7 +2265,7 @@ system.iobus.reqLayer16.occupancy 48000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -2271,25 +2273,25 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6160500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6164000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32043500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32044500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187096722 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187734328 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36461 # number of replacements -system.iocache.tags.tagsinuse 14.380038 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.386648 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290749964000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.380038 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.898752 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.898752 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 289174340000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.386648 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899166 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899166 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2303,14 +2305,14 @@ system.iocache.demand_misses::realview.ide 36479 # system.iocache.demand_misses::total 36479 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36479 # number of overall misses system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32883377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32883377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4577110345 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4577110345 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4609993722 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4609993722 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4609993722 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4609993722 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 36421877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 36421877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4307524451 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4307524451 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4343946328 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4343946328 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4343946328 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4343946328 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2327,22 +2329,22 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128954.419608 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128954.419608 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126355.740531 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126355.740531 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126373.906138 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 126373.906138 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126373.906138 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 142830.890196 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 142830.890196 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118913.550436 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118913.550436 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119080.740371 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119080.740371 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119080.740371 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.142857 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses @@ -2351,14 +2353,14 @@ system.iocache.demand_mshr_misses::realview.ide 36479 system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20133377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20133377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764215832 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2764215832 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2784349209 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2784349209 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2784349209 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2784349209 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 23671877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 23671877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2493982137 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2493982137 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2517654014 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2517654014 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2517654014 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2517654014 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2367,540 +2369,546 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78954.419608 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78954.419608 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76308.961793 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76308.961793 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76327.454398 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76327.454398 # average overall mshr miss latency -system.l2c.tags.replacements 124374 # number of replacements -system.l2c.tags.tagsinuse 62971.222447 # Cycle average of tags in use -system.l2c.tags.total_refs 421293 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 188431 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.235795 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 92830.890196 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 92830.890196 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68848.888499 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68848.888499 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 69016.530442 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69016.530442 # average overall mshr miss latency +system.l2c.tags.replacements 126308 # number of replacements +system.l2c.tags.tagsinuse 63017.044477 # Cycle average of tags in use +system.l2c.tags.total_refs 424315 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 190178 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.231147 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13456.936548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.884029 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.161578 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7408.035333 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2772.307356 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35669.502662 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1440.723489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 421.652649 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1798.018803 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.205337 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000059 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.113038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042302 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544273 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021984 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.006434 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027436 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.960865 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32172 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31879 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 13637.426679 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.018602 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.043991 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7319.345128 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2841.087210 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35552.012227 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1437.607406 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 447.669169 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1777.834065 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.208091 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.111684 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.542481 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021936 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.006831 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027128 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.961564 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30519 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33346 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5261 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26614 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 165 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4688 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25665 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 368 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2433 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29060 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.490906 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.486435 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5838028 # Number of tag accesses -system.l2c.tags.data_accesses 5838028 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 257920 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 257920 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32259 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1955 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34214 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2096 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 941 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3037 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4136 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1368 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5504 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 86 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28311 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 47114 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47400 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 25 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 16 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 6412 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 5086 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3327 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 137845 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 86 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28311 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51250 # 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number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 16 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6412 # number of overall hits -system.l2c.overall_hits::cpu1.data 6454 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 3327 # number of overall hits -system.l2c.overall_hits::total 143349 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9332 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2240 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11572 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 606 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1282 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1888 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11165 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7705 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 18870 # 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number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34467 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1985 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 965 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2950 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3870 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1490 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5360 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 97 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 76 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 27673 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 45621 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45892 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 31 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 37 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 10962 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 9208 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5411 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 145008 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 97 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 76 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 27673 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49491 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 45892 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 31 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 37 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 10962 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 10698 # 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average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 25817.343173 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24925.170068 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25184.450402 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85677.383885 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72412.526460 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80185.860096 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 77665.707515 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80245.912383 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 85088.039022 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 77000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71834.999773 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 82167.770638 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 86888.475382 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73085.601405 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73167.041859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 99937.862429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84584.657278 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182495.203196 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117273.285899 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 153281.639181 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64437.486145 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96288.897187 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63632.768362 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65429.267412 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 90099.665315 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 512702 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 293222 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 588 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 44083 # Transaction distribution +system.membus.trans_dist::ReadResp 213856 # Transaction distribution +system.membus.trans_dist::WriteReq 30913 # Transaction distribution +system.membus.trans_dist::WriteResp 30913 # Transaction distribution +system.membus.trans_dist::WritebackDirty 135145 # Transaction distribution +system.membus.trans_dist::CleanEvict 15700 # Transaction distribution +system.membus.trans_dist::UpgradeReq 75854 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40085 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 39863 # Transaction distribution +system.membus.trans_dist::ReadExResp 19313 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 169773 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13764 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 651465 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773197 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846152 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 656506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 778196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72939 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72939 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 851135 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18344268 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18534678 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20852822 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 120859 # Total snoops (count) -system.membus.snoop_fanout::samples 582572 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18452748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18643092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20960212 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123593 # Total snoops (count) +system.membus.snoop_fanout::samples 436796 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011900 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.108438 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 582572 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 431598 98.81% 98.81% # Request fanout histogram +system.membus.snoop_fanout::1 5198 1.19% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 582572 # Request fanout histogram -system.membus.reqLayer0.occupancy 88269500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 436796 # Request fanout histogram +system.membus.reqLayer0.occupancy 88259500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11360500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11350000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 969988933 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 980369236 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1109172490 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1108695304 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1385877 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1346131 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2943,52 +2951,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 961097 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 519247 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 138785 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20683 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19864 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 819 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 44098 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 467805 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30922 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30922 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 391320 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 106223 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 107477 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42889 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 150366 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 104 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 104 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50473 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50473 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 423722 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241271 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253131 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1494402 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34264962 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3773844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 38038806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 438960 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 896783 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.336520 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.474448 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 980232 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 530887 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 150046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20267 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19482 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44086 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 477451 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30913 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30913 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 359949 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 109182 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 110235 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43035 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153270 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50915 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50915 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 433367 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4592 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224504 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 296079 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1520583 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 33710224 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4970948 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38681172 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 378680 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 843567 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.376795 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.486500 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 595817 66.44% 66.44% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 300147 33.47% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 819 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 526500 62.41% 62.41% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 316282 37.49% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 785 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 896783 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 864823852 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 843567 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 877207087 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360619 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 645977888 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 640962681 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 202227821 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 223907403 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index da0ada0fc..db033150d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.909587 # Nu sim_ticks 2909586837500 # Number of ticks simulated final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 812558 # Simulator instruction rate (inst/s) -host_op_rate 979692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21023218607 # Simulator tick rate (ticks/s) -host_mem_usage 578440 # Number of bytes of host memory used -host_seconds 138.40 # Real time elapsed on the host +host_inst_rate 581636 # Simulator instruction rate (inst/s) +host_op_rate 701272 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15048595995 # Simulator tick rate (ticks/s) +host_mem_usage 573724 # Number of bytes of host memory used +host_seconds 193.35 # Real time elapsed on the host sim_insts 112457033 # Number of instructions simulated sim_ops 135588117 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index 254a8cf36..bc56e0971 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,27 +1,27 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783855 # Number of seconds simulated -sim_ticks 2783854535000 # Number of ticks simulated -final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783854 # Number of seconds simulated +sim_ticks 2783853866500 # Number of ticks simulated +final_tick 2783853866500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1181524 # Simulator instruction rate (inst/s) -host_op_rate 1438316 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23038118447 # Simulator tick rate (ticks/s) -host_mem_usage 579724 # Number of bytes of host memory used -host_seconds 120.84 # Real time elapsed on the host -sim_insts 142771651 # Number of instructions simulated -sim_ops 173801592 # Number of ops (including micro ops) simulated +host_inst_rate 806647 # Simulator instruction rate (inst/s) +host_op_rate 981963 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15728650419 # Simulator tick rate (ticks/s) +host_mem_usage 576800 # Number of bytes of host memory used +host_seconds 176.99 # Real time elapsed on the host +sim_insts 142770436 # Number of instructions simulated +sim_ops 173800089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 724196 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4660000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4660192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 482816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5664516 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5664388 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11533000 # Number of bytes read from this memory +system.physmem.bytes_read::total 11533064 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 724196 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 482816 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory @@ -32,42 +32,42 @@ system.physmem.bytes_written::total 8858100 # Nu system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 19769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73331 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73334 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 7544 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88509 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88507 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189176 # Number of read requests responded to by this memory +system.physmem.num_reads::total 189177 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 138134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory system.physmem.num_writes::total 142515 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 260141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1673938 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 260142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1674007 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 173434 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2034774 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2034729 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142817 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260142 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 173434 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175661 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175661 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1680230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1680299 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 173434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2034777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2034732 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7324797 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -116,45 +116,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5703 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5703 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5703 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5703 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5703 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 5701 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5701 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5701 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5701 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5701 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3075 65.68% 65.68% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1607 34.32% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4682 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5703 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 3076 65.73% 65.73% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1604 34.27% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4680 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5701 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5703 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5701 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4680 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4682 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10385 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4680 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10381 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15997085 # DTB read hits -system.cpu0.dtb.read_misses 4809 # DTB read misses -system.cpu0.dtb.write_hits 11281852 # DTB write hits -system.cpu0.dtb.write_misses 894 # DTB write misses +system.cpu0.dtb.read_hits 15997245 # DTB read hits +system.cpu0.dtb.read_misses 4805 # DTB read misses +system.cpu0.dtb.write_hits 11281011 # DTB write hits +system.cpu0.dtb.write_misses 896 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3232 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3231 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 770 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 769 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16001894 # DTB read accesses -system.cpu0.dtb.write_accesses 11282746 # DTB write accesses +system.cpu0.dtb.read_accesses 16002050 # DTB read accesses +system.cpu0.dtb.write_accesses 11281907 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27278937 # DTB hits -system.cpu0.dtb.misses 5703 # DTB misses -system.cpu0.dtb.accesses 27284640 # DTB accesses +system.cpu0.dtb.hits 27278256 # DTB hits +system.cpu0.dtb.misses 5701 # DTB misses +system.cpu0.dtb.accesses 27283957 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -192,8 +192,8 @@ system.cpu0.itb.walker.walkWaitTime::total 2590 # system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1366 72.81% 72.81% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 510 27.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1367 72.87% 72.87% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 509 27.13% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 1876 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2590 # Table walker requests started/completed, data/inst @@ -202,7 +202,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1876 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1876 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 4466 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74797685 # ITB inst hits +system.cpu0.itb.inst_hits 74798476 # ITB inst hits system.cpu0.itb.inst_misses 2590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -219,40 +219,40 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74800275 # ITB inst accesses -system.cpu0.itb.hits 74797685 # DTB hits +system.cpu0.itb.inst_accesses 74801066 # ITB inst accesses +system.cpu0.itb.hits 74798476 # DTB hits system.cpu0.itb.misses 2590 # DTB misses -system.cpu0.itb.accesses 74800275 # DTB accesses -system.cpu0.numCycles 5536444787 # number of cpu cycles simulated +system.cpu0.itb.accesses 74801066 # DTB accesses +system.cpu0.numCycles 5536444785 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed -system.cpu0.committedInsts 72639178 # Number of instructions committed -system.cpu0.committedOps 87981810 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77492203 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5289 # Number of float alu accesses -system.cpu0.num_func_calls 8694463 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9459638 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77492203 # number of integer instructions -system.cpu0.num_fp_insts 5289 # number of float instructions -system.cpu0.num_int_register_reads 144072055 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54447583 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4067 # number of times the floating registers were read +system.cpu0.committedInsts 72639773 # Number of instructions committed +system.cpu0.committedOps 87981470 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77491639 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5273 # Number of float alu accesses +system.cpu0.num_func_calls 8694385 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9459738 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77491639 # number of integer instructions +system.cpu0.num_fp_insts 5273 # number of float instructions +system.cpu0.num_int_register_reads 144069521 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54447635 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4051 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268879809 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31833575 # number of times the CC registers were written -system.cpu0.num_mem_refs 27909868 # number of memory refs -system.cpu0.num_load_insts 16164638 # Number of load instructions -system.cpu0.num_store_insts 11745230 # Number of store instructions -system.cpu0.num_idle_cycles 5353616276.220466 # Number of idle cycles -system.cpu0.num_busy_cycles 182828510.779535 # Number of busy cycles -system.cpu0.not_idle_fraction 0.033023 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.966977 # Percentage of idle cycles -system.cpu0.Branches 18600800 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61776579 68.83% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59680 0.07% 68.90% # Class of executed instruction +system.cpu0.num_cc_register_reads 268878195 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31834253 # number of times the CC registers were written +system.cpu0.num_mem_refs 27909194 # number of memory refs +system.cpu0.num_load_insts 16164821 # Number of load instructions +system.cpu0.num_store_insts 11744373 # Number of store instructions +system.cpu0.num_idle_cycles 5353617701.078379 # Number of idle cycles +system.cpu0.num_busy_cycles 182827083.921621 # Number of busy cycles +system.cpu0.not_idle_fraction 0.033022 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.966978 # Percentage of idle cycles +system.cpu0.Branches 18600825 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2187 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 61776865 68.83% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59682 0.07% 68.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction @@ -276,24 +276,24 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4414 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4413 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16164638 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11745230 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16164821 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11744373 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89752729 # Class of executed instruction -system.cpu0.dcache.tags.replacements 819392 # number of replacements +system.cpu0.op_class::total 89752341 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819388 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53783791 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597669 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53783376 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819900 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597483 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830580 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166594 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929357 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830508 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166666 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929356 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070638 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -301,90 +301,90 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219234764 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219234764 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15305281 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14823482 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30128763 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10894769 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11445022 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185755 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209286 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395041 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234992 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222324 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 219233084 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219233084 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15305417 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14823075 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30128492 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10893994 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11445651 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339645 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185752 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209291 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395043 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234995 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222321 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 457316 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236691 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223431 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236694 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223428 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26200050 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26268504 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52468554 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26385805 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26477790 # number of overall hits -system.cpu0.dcache.overall_hits::total 52863595 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197438 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 198880 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396318 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137575 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 164088 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301663 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54345 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61721 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116066 # number of SoftPFReq misses +system.cpu0.dcache.demand_hits::cpu0.data 26199411 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26268726 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52468137 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26385163 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26478017 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863180 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197452 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 198861 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396313 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137507 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 164158 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301665 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54352 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61713 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 116065 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4663 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3966 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 335013 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 362968 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697981 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389358 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424689 # number of overall misses -system.cpu0.dcache.overall_misses::total 814047 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502719 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15022362 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11032344 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609110 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240100 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271007 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511107 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239655 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226290 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 334959 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 363019 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697978 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389311 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424732 # number of overall misses +system.cpu0.dcache.overall_misses::total 814043 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502869 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15021936 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30524805 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11031501 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609809 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641310 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240104 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271004 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511108 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239658 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226287 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236691 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223433 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236694 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223430 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26535063 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631472 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26775163 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26902479 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53677642 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26534370 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631745 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166115 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26774474 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26902749 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677223 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012736 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013239 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013238 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012470 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014134 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226343 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227747 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227087 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012465 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014140 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226369 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227720 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227085 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019457 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017526 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012624 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013631 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014542 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015786 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.015165 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014540 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015788 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -393,14 +393,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks system.cpu0.dcache.writebacks::total 682241 # number of writebacks -system.cpu0.icache.tags.replacements 1698998 # number of replacements +system.cpu0.icache.tags.replacements 1698997 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145341757 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 145340473 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699509 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.519096 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121661 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542018 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121595 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542085 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy @@ -410,43 +410,43 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148740789 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148740789 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73955506 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71386251 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145341757 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73955506 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71386251 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145341757 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73955506 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71386251 # number of overall hits -system.cpu0.icache.overall_hits::total 145341757 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844055 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855461 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699516 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844055 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855461 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699516 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844055 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855461 # number of overall misses -system.cpu0.icache.overall_misses::total 1699516 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74799561 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72241712 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74799561 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72241712 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74799561 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72241712 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011284 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011842 # miss rate for ReadReq accesses +system.cpu0.icache.tags.tag_accesses 148739503 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148739503 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73956240 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71384233 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145340473 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73956240 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71384233 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145340473 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73956240 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71384233 # number of overall hits +system.cpu0.icache.overall_hits::total 145340473 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844112 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855403 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699515 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844112 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855403 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699515 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844112 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855403 # number of overall misses +system.cpu0.icache.overall_misses::total 1699515 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74800352 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72239636 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147039988 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74800352 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72239636 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147039988 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74800352 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72239636 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147039988 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011285 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011841 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011284 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011285 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011841 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011285 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011841 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -454,8 +454,8 @@ system.cpu0.icache.blocked::no_mshrs 0 # nu system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1698998 # number of writebacks -system.cpu0.icache.writebacks::total 1698998 # number of writebacks +system.cpu0.icache.writebacks::writebacks 1698997 # number of writebacks +system.cpu0.icache.writebacks::total 1698997 # number of writebacks system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -485,45 +485,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6189 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6189 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 6189 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6189 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6189 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 6190 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6190 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 6190 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6190 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6190 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3697 73.27% 73.27% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::4K 3698 73.27% 73.27% # Table walker page sizes translated system.cpu1.dtb.walker.walkPageSizes::1M 1349 26.73% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5046 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6189 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::total 5047 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6190 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6189 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5046 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6190 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5047 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5046 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11235 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5047 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11237 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15527164 # DTB read hits -system.cpu1.dtb.read_misses 5392 # DTB read misses -system.cpu1.dtb.write_hits 11842009 # DTB write hits -system.cpu1.dtb.write_misses 797 # DTB write misses +system.cpu1.dtb.read_hits 15526731 # DTB read hits +system.cpu1.dtb.read_misses 5394 # DTB read misses +system.cpu1.dtb.write_hits 11842705 # DTB write hits +system.cpu1.dtb.write_misses 796 # DTB write misses system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3188 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3189 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 922 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15532556 # DTB read accesses -system.cpu1.dtb.write_accesses 11842806 # DTB write accesses +system.cpu1.dtb.read_accesses 15532125 # DTB read accesses +system.cpu1.dtb.write_accesses 11843501 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27369173 # DTB hits -system.cpu1.dtb.misses 6189 # DTB misses -system.cpu1.dtb.accesses 27375362 # DTB accesses +system.cpu1.dtb.hits 27369436 # DTB hits +system.cpu1.dtb.misses 6190 # DTB misses +system.cpu1.dtb.accesses 27375626 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -571,7 +571,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 5161 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 72239602 # ITB inst hits +system.cpu1.itb.inst_hits 72237526 # ITB inst hits system.cpu1.itb.inst_misses 3051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -588,40 +588,40 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72242653 # ITB inst accesses -system.cpu1.itb.hits 72239602 # DTB hits +system.cpu1.itb.inst_accesses 72240577 # ITB inst accesses +system.cpu1.itb.hits 72237526 # DTB hits system.cpu1.itb.misses 3051 # DTB misses -system.cpu1.itb.accesses 72242653 # DTB accesses -system.cpu1.numCycles 88015617 # number of cpu cycles simulated +system.cpu1.itb.accesses 72240577 # DTB accesses +system.cpu1.numCycles 88014282 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 70132473 # Number of instructions committed -system.cpu1.committedOps 85819782 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75669076 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6195 # Number of float alu accesses -system.cpu1.num_func_calls 8179499 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9270637 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75669076 # number of integer instructions -system.cpu1.num_fp_insts 6195 # number of float instructions -system.cpu1.num_int_register_reads 140985520 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52730881 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4705 # number of times the floating registers were read +system.cpu1.committedInsts 70130663 # Number of instructions committed +system.cpu1.committedOps 85818619 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75668279 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6211 # Number of float alu accesses +system.cpu1.num_func_calls 8179291 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9270395 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75668279 # number of integer instructions +system.cpu1.num_fp_insts 6211 # number of float instructions +system.cpu1.num_int_register_reads 140985352 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52729833 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4721 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261969734 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30530329 # number of times the CC registers were written -system.cpu1.num_mem_refs 28028748 # number of memory refs -system.cpu1.num_load_insts 15690947 # Number of load instructions -system.cpu1.num_store_insts 12337801 # Number of store instructions -system.cpu1.num_idle_cycles 85360941.513009 # Number of idle cycles -system.cpu1.num_busy_cycles 2654675.486991 # Number of busy cycles +system.cpu1.num_cc_register_reads 261966626 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30529225 # number of times the CC registers were written +system.cpu1.num_mem_refs 28028988 # number of memory refs +system.cpu1.num_load_insts 15690476 # Number of load instructions +system.cpu1.num_store_insts 12338512 # Number of store instructions +system.cpu1.num_idle_cycles 85359668.730648 # Number of idle cycles +system.cpu1.num_busy_cycles 2654613.269352 # Number of busy cycles system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles -system.cpu1.Branches 17796178 # Number of branches fetched -system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59375458 67.88% 67.88% # Class of executed instruction -system.cpu1.op_class::IntMult 57193 0.07% 67.95% # Class of executed instruction +system.cpu1.Branches 17795727 # Number of branches fetched +system.cpu1.op_class::No_OpClass 150 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 59374032 67.88% 67.88% # Class of executed instruction +system.cpu1.op_class::IntMult 57191 0.07% 67.95% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction @@ -645,15 +645,15 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4155 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4156 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction -system.cpu1.op_class::MemRead 15690947 17.94% 85.89% # Class of executed instruction -system.cpu1.op_class::MemWrite 12337801 14.11% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 15690476 17.94% 85.89% # Class of executed instruction +system.cpu1.op_class::MemWrite 12338512 14.11% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87465703 # Class of executed instruction +system.cpu1.op_class::total 87464517 # Class of executed instruction system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -705,12 +705,12 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909889 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 227409732009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.909889 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -750,20 +750,20 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.l2c.tags.replacements 109907 # number of replacements -system.l2c.tags.tagsinuse 65155.314985 # Cycle average of tags in use -system.l2c.tags.total_refs 4528037 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175188 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 25.846730 # Average number of references to valid blocks. +system.l2c.tags.replacements 109908 # number of replacements +system.l2c.tags.tagsinuse 65155.315514 # Cycle average of tags in use +system.l2c.tags.total_refs 4528029 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 175189 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 25.846537 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48764.087166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48764.089063 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5143.112513 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4734.411223 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5143.111803 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4734.405961 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4025.485555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2484.315404 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4025.485403 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2484.320162 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -783,155 +783,155 @@ system.l2c.tags.age_task_id_blocks_1024::3 10699 # system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40604434 # Number of tag accesses -system.l2c.tags.data_accesses 40604434 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4715 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2284 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4980 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2427 # number of ReadReq hits -system.l2c.ReadReq_hits::total 14406 # number of ReadReq hits +system.l2c.tags.tag_accesses 40604397 # Number of tag accesses +system.l2c.tags.data_accesses 40604397 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2285 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4983 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits +system.l2c.ReadReq_hits::total 14414 # number of ReadReq hits system.l2c.WritebackDirty_hits::writebacks 682241 # number of WritebackDirty hits system.l2c.WritebackDirty_hits::total 682241 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1666999 # number of WritebackClean hits +system.l2c.WritebackClean_hits::writebacks 1666994 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1666994 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72343 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78788 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151131 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 833292 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 847909 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 246688 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 258762 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 505450 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4715 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2284 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833292 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 319031 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4980 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2427 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847909 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337550 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352188 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4715 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2284 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833292 # number of overall hits -system.l2c.overall_hits::cpu0.data 319031 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4980 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2427 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847909 # number of overall hits -system.l2c.overall_hits::cpu1.data 337550 # number of overall hits -system.l2c.overall_hits::total 2352188 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 72274 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78858 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151132 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 833349 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 847851 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1681200 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 246710 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 258734 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 505444 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4717 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2285 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833349 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 318984 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4983 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 847851 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337592 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352190 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4717 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2285 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833349 # number of overall hits +system.l2c.overall_hits::cpu0.data 318984 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4983 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847851 # number of overall hits +system.l2c.overall_hits::cpu1.data 337592 # number of overall hits +system.l2c.overall_hits::total 2352190 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1250 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1478 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1248 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1480 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63970 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83806 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147776 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 63973 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83804 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 147777 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 10754 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 7544 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9758 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 5805 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9757 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 5806 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 15563 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 10754 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73728 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73730 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 7544 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89611 # number of demand (read+write) misses -system.l2c.demand_misses::total 181645 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89610 # number of demand (read+write) misses +system.l2c.demand_misses::total 181646 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.inst 10754 # number of overall misses -system.l2c.overall_misses::cpu0.data 73728 # number of overall misses +system.l2c.overall_misses::cpu0.data 73730 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu1.inst 7544 # number of overall misses -system.l2c.overall_misses::cpu1.data 89611 # number of overall misses -system.l2c.overall_misses::total 181645 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4720 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2285 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 4982 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2427 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 14414 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.data 89610 # number of overall misses +system.l2c.overall_misses::total 181646 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4722 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2286 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4985 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 14422 # number of ReadReq accesses(hits+misses) system.l2c.WritebackDirty_accesses::writebacks 682241 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 682241 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1666994 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1666994 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1260 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1496 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136313 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162594 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 844046 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 855453 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 256446 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 264567 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4720 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2285 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844046 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4982 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2427 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855453 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427161 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2533833 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4720 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2285 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844046 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4982 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2427 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855453 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427161 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2533833 # number of overall (read+write) accesses +system.l2c.ReadExReq_accesses::cpu0.data 136247 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162662 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 298909 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 844103 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 855395 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1699498 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 256467 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 264540 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 521007 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4722 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2286 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844103 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392714 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4985 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855395 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427202 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2533836 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4722 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2286 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844103 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392714 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4985 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855395 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427202 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2533836 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000438 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.000555 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990491 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989290 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990476 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989305 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.469288 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515431 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.469537 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.515203 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012741 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012740 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008819 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038051 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021942 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038044 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021948 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.029871 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000438 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012741 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187718 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012740 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187745 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.008819 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209783 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209760 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.071688 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000438 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012741 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187718 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012740 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187745 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.008819 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209783 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209760 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.071688 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -941,48 +941,54 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.writebacks::writebacks 101944 # number of writebacks system.l2c.writebacks::total 101944 # number of writebacks +system.membus.snoop_filter.tot_requests 367178 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 155396 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution system.membus.trans_dist::WritebackDirty 138134 # Transaction distribution -system.membus.trans_dist::CleanEvict 8203 # Transaction distribution +system.membus.trans_dist::CleanEvict 8204 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution -system.membus.trans_dist::ReadExReq 145997 # Transaction distribution -system.membus.trans_dist::ReadExResp 145997 # Transaction distribution +system.membus.trans_dist::ReadExReq 145998 # Transaction distribution +system.membus.trans_dist::ReadExResp 145998 # Transaction distribution system.membus.trans_dist::ReadSharedReq 34109 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506563 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 613923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506566 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 613926 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723281 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723284 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091708 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18254681 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18254745 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586201 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586265 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 434809 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::samples 434811 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012707 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.112006 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 434809 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 429286 98.73% 98.73% # Request fanout histogram +system.membus.snoop_fanout::1 5525 1.27% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 434809 # Request fanout histogram +system.membus.snoop_fanout::total 434811 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1024,47 +1030,47 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5060329 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2540912 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5060315 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540903 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 39264 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 71251 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291780 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 71253 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291775 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 682241 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 137151 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1698997 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 137147 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116074 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581970 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20766 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41562 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7760372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96321057 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41532 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83124 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 313986697 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 182969 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5322182 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.018547 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.134917 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 298909 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298909 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1699515 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 521007 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116071 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581958 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20768 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41564 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7760361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217540856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96320801 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313986321 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 115322 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5254527 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018786 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.135767 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5223474 98.15% 98.15% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 98708 1.85% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5155817 98.12% 98.12% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 98710 1.88% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5322182 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5254527 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index e91a37dbe..0b3858068 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909645 # Number of seconds simulated -sim_ticks 2909644861500 # Number of ticks simulated -final_tick 2909644861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903880 # Number of seconds simulated +sim_ticks 2903879904500 # Number of ticks simulated +final_tick 2903879904500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 753896 # Simulator instruction rate (inst/s) -host_op_rate 908960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19506336140 # Simulator tick rate (ticks/s) -host_mem_usage 580236 # Number of bytes of host memory used -host_seconds 149.16 # Real time elapsed on the host -sim_insts 112454211 # Number of instructions simulated -sim_ops 135584166 # Number of ops (including micro ops) simulated +host_inst_rate 558564 # Simulator instruction rate (inst/s) +host_op_rate 673462 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14421337908 # Simulator tick rate (ticks/s) +host_mem_usage 577056 # Number of bytes of host memory used +host_seconds 201.36 # Real time elapsed on the host +sim_insts 112472356 # Number of instructions simulated +sim_ops 135608165 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 522464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4660352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 557092 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4007584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 664132 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4241316 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 629760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4985028 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10089736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 522464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 664132 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7511872 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 8852 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 8672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7529396 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73321 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 10181064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 557092 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 629760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186852 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7592448 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::total 7609972 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17158 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 63137 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 13543 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 66287 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77892 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166625 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117373 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 2213 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 2168 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121754 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 179563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1601691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 168052 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118632 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123013 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 191844 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1380079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 110 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 228252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1457675 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 179563 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 228252 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407815 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2581714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 3042 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2587737 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2581714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 179563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1604733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 216868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1716678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3506021 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 191844 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 216868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 408712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2614587 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2620622 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2614587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 191844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1386111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 110 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 228252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1460655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6055424 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166625 # Number of read requests accepted -system.physmem.writeReqs 121754 # Number of write requests accepted -system.physmem.readBursts 166625 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121754 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10658176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5824 # Total number of bytes read from write queue -system.physmem.bytesWritten 7541376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10089736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7529396 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 91 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu1.inst 216868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1716681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6126643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168052 # Number of read requests accepted +system.physmem.writeReqs 123013 # Number of write requests accepted +system.physmem.readBursts 168052 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 123013 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10746816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue +system.physmem.bytesWritten 7623936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10181064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7609972 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10080 # Per bank write bursts -system.physmem.perBankRdBursts::1 9979 # Per bank write bursts -system.physmem.perBankRdBursts::2 10697 # Per bank write bursts -system.physmem.perBankRdBursts::3 10657 # Per bank write bursts -system.physmem.perBankRdBursts::4 18793 # Per bank write bursts -system.physmem.perBankRdBursts::5 9662 # Per bank write bursts -system.physmem.perBankRdBursts::6 9670 # Per bank write bursts -system.physmem.perBankRdBursts::7 10491 # Per bank write bursts -system.physmem.perBankRdBursts::8 9280 # Per bank write bursts -system.physmem.perBankRdBursts::9 9982 # Per bank write bursts -system.physmem.perBankRdBursts::10 9231 # Per bank write bursts -system.physmem.perBankRdBursts::11 8678 # Per bank write bursts -system.physmem.perBankRdBursts::12 9823 # Per bank write bursts -system.physmem.perBankRdBursts::13 10380 # Per bank write bursts -system.physmem.perBankRdBursts::14 9718 # Per bank write bursts -system.physmem.perBankRdBursts::15 9413 # Per bank write bursts -system.physmem.perBankWrBursts::0 7393 # Per bank write bursts -system.physmem.perBankWrBursts::1 7263 # Per bank write bursts -system.physmem.perBankWrBursts::2 8284 # Per bank write bursts -system.physmem.perBankWrBursts::3 8168 # Per bank write bursts -system.physmem.perBankWrBursts::4 7485 # Per bank write bursts -system.physmem.perBankWrBursts::5 7265 # Per bank write bursts -system.physmem.perBankWrBursts::6 7108 # Per bank write bursts -system.physmem.perBankWrBursts::7 7667 # Per bank write bursts -system.physmem.perBankWrBursts::8 7080 # Per bank write bursts -system.physmem.perBankWrBursts::9 7523 # Per bank write bursts -system.physmem.perBankWrBursts::10 6694 # Per bank write bursts -system.physmem.perBankWrBursts::11 6470 # Per bank write bursts -system.physmem.perBankWrBursts::12 7527 # Per bank write bursts -system.physmem.perBankWrBursts::13 7859 # Per bank write bursts -system.physmem.perBankWrBursts::14 7260 # Per bank write bursts -system.physmem.perBankWrBursts::15 6788 # Per bank write bursts +system.physmem.perBankRdBursts::0 9950 # Per bank write bursts +system.physmem.perBankRdBursts::1 9634 # Per bank write bursts +system.physmem.perBankRdBursts::2 10758 # Per bank write bursts +system.physmem.perBankRdBursts::3 10205 # Per bank write bursts +system.physmem.perBankRdBursts::4 18891 # Per bank write bursts +system.physmem.perBankRdBursts::5 10113 # Per bank write bursts +system.physmem.perBankRdBursts::6 10004 # Per bank write bursts +system.physmem.perBankRdBursts::7 10172 # Per bank write bursts +system.physmem.perBankRdBursts::8 9614 # Per bank write bursts +system.physmem.perBankRdBursts::9 10312 # Per bank write bursts +system.physmem.perBankRdBursts::10 9754 # Per bank write bursts +system.physmem.perBankRdBursts::11 9150 # Per bank write bursts +system.physmem.perBankRdBursts::12 10004 # Per bank write bursts +system.physmem.perBankRdBursts::13 10185 # Per bank write bursts +system.physmem.perBankRdBursts::14 9904 # Per bank write bursts +system.physmem.perBankRdBursts::15 9269 # Per bank write bursts +system.physmem.perBankWrBursts::0 7437 # Per bank write bursts +system.physmem.perBankWrBursts::1 7207 # Per bank write bursts +system.physmem.perBankWrBursts::2 8535 # Per bank write bursts +system.physmem.perBankWrBursts::3 7773 # Per bank write bursts +system.physmem.perBankWrBursts::4 7341 # Per bank write bursts +system.physmem.perBankWrBursts::5 7352 # Per bank write bursts +system.physmem.perBankWrBursts::6 7319 # Per bank write bursts +system.physmem.perBankWrBursts::7 7510 # Per bank write bursts +system.physmem.perBankWrBursts::8 7314 # Per bank write bursts +system.physmem.perBankWrBursts::9 7939 # Per bank write bursts +system.physmem.perBankWrBursts::10 7417 # Per bank write bursts +system.physmem.perBankWrBursts::11 7018 # Per bank write bursts +system.physmem.perBankWrBursts::12 7498 # Per bank write bursts +system.physmem.perBankWrBursts::13 7483 # Per bank write bursts +system.physmem.perBankWrBursts::14 7310 # Per bank write bursts +system.physmem.perBankWrBursts::15 6671 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 15 # Number of times write queue was full causing retry -system.physmem.totGap 2909644504500 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 2903879542500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157053 # Read request sizes (log2) +system.physmem.readPktSize::6 158480 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117373 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118632 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 521 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 249 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -161,179 +165,181 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5940 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 178 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58581 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.672197 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.145957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.231527 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21388 36.51% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14603 24.93% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5975 10.20% 71.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3225 5.51% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2561 4.37% 81.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1528 2.61% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1012 1.73% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1135 1.94% 87.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7154 12.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58581 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5570 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.894255 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 552.382236 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5567 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.04% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.602107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.973761 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.010341 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21606 36.77% 36.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14724 25.05% 61.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5582 9.50% 71.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3238 5.51% 76.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2495 4.25% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1555 2.65% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 968 1.65% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1073 1.83% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7526 12.81% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58767 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5814 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.881665 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 551.015664 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5812 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5570 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5570 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.155117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.796345 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 15.496905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 17 0.31% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 9 0.16% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.14% 0.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 13 0.23% 0.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4758 85.42% 86.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 105 1.89% 88.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 66 1.18% 89.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 70 1.26% 90.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 40 0.72% 91.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.31% 91.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 48 0.86% 92.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.18% 92.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 152 2.73% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 8 0.14% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.18% 95.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 62 1.11% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.16% 97.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.02% 97.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.48% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 105 1.89% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.04% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.07% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.13% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.09% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5570 # Writes before turning the bus around for reads -system.physmem.totQLat 1610742500 # Total ticks spent queuing -system.physmem.totMemAccLat 4733255000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832670000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9672.15 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5814 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5814 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.489164 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.609616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.405574 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 19 0.33% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 12 0.21% 0.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.07% 0.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 14 0.24% 0.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4869 83.75% 84.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 76 1.31% 85.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 108 1.86% 87.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 83 1.43% 89.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 296 5.09% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 49 0.84% 95.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.22% 95.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.19% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 16 0.28% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.10% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.10% 96.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 172 2.96% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.14% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.07% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 4 0.07% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 4 0.07% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 6 0.10% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.19% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5814 # Writes before turning the bus around for reads +system.physmem.totQLat 1475229250 # Total ticks spent queuing +system.physmem.totMemAccLat 4623710500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 839595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8785.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28422.15 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27535.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.25 # Average write queue length when enqueuing -system.physmem.readRowHits 136266 # Number of row buffer hits during reads -system.physmem.writeRowHits 89520 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes -system.physmem.avgGap 10089654.60 # Average gap between requests -system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 230678280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125866125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702226200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190043786400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90291916755 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666582969500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948370345100 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.624992 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772326098500 # Time in different power states -system.physmem_0.memoryStateTime::REF 97159400000 # Time in different power states +system.physmem.avgWrQLen 12.36 # Average write queue length when enqueuing +system.physmem.readRowHits 138207 # Number of row buffer hits during reads +system.physmem.writeRowHits 90068 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.61 # Row buffer hit rate for writes +system.physmem.avgGap 9976739.02 # Average gap between requests +system.physmem.pageHitRate 79.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 228947040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 124921500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 699870600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 391871520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189666943440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87330979935 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665718515750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1944162049785 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.506247 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770909332000 # Time in different power states +system.physmem_0.memoryStateTime::REF 96966740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40158524000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35998339250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 212194080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 115780500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 596731200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370662480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190043786400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88418921265 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668225948000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947984023925 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.492219 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775082980250 # Time in different power states -system.physmem_1.memoryStateTime::REF 97159400000 # Time in different power states +system.physmem_1.actEnergy 215331480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 117492375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 609889800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 380052000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189666943440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85596128505 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1667240315250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943826152850 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.390575 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2773463023000 # Time in different power states +system.physmem_1.memoryStateTime::REF 96966740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37402333250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33450042500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -383,59 +389,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6403 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6403 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1830 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4572 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6402 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6402 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6402 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5332 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 13399.287322 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11603.034588 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7407.871184 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 4008 75.17% 75.17% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1320 24.76% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5332 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 2989035968 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.330748 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.470482 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2000419000 66.93% 66.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 988616968 33.07% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 2989035968 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3528 66.18% 66.18% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1803 33.82% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5331 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6403 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 6844 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6844 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2237 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4607 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 6844 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6844 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6844 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5812 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12925.584997 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11265.166351 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6611.780154 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-8191 1551 26.69% 26.69% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::8192-16383 2959 50.91% 77.60% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-24575 1234 21.23% 98.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::24576-32767 66 1.14% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-90111 2 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5812 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 941563500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 941563500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 941563500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3596 61.87% 61.87% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2216 38.13% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5812 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6844 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6403 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5331 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6844 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5812 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5331 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 11734 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5812 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12656 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12042048 # DTB read hits -system.cpu0.dtb.read_misses 5594 # DTB read misses -system.cpu0.dtb.write_hits 9609454 # DTB write hits -system.cpu0.dtb.write_misses 809 # DTB write misses -system.cpu0.dtb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12196931 # DTB read hits +system.cpu0.dtb.read_misses 5939 # DTB read misses +system.cpu0.dtb.write_hits 9657394 # DTB write hits +system.cpu0.dtb.write_misses 905 # DTB write misses +system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3984 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4577 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 860 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 883 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12047642 # DTB read accesses -system.cpu0.dtb.write_accesses 9610263 # DTB write accesses +system.cpu0.dtb.perms_faults 223 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12202870 # DTB read accesses +system.cpu0.dtb.write_accesses 9658299 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21651502 # DTB hits -system.cpu0.dtb.misses 6403 # DTB misses -system.cpu0.dtb.accesses 21657905 # DTB accesses +system.cpu0.dtb.hits 21854325 # DTB hits +system.cpu0.dtb.misses 6844 # DTB misses +system.cpu0.dtb.accesses 21861169 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,512 +469,506 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3203 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3203 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 686 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2517 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3203 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3203 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3203 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2349 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 13262.452107 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11543.567684 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6519.168051 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::4096-6143 600 25.54% 25.54% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::10240-12287 662 28.18% 53.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::12288-14335 191 8.13% 61.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.48% 78.33% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.46% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::22528-24575 498 21.20% 99.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-26623 8 0.34% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2349 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1663 70.80% 70.80% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 686 29.20% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2349 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3527 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3527 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 843 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2684 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3527 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3527 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3527 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2692 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13515.230312 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11626.856178 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7003.990357 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 705 26.19% 26.19% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1285 47.73% 73.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 689 25.59% 99.52% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 12 0.45% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2692 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 941232000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 941232000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 941232000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1849 68.68% 68.68% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 843 31.32% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2692 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3203 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3203 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3527 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3527 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2349 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2349 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5552 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56738612 # ITB inst hits -system.cpu0.itb.inst_misses 3203 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2692 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2692 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6219 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 57466570 # ITB inst hits +system.cpu0.itb.inst_misses 3527 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 471 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2718 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56741815 # ITB inst accesses -system.cpu0.itb.hits 56738612 # DTB hits -system.cpu0.itb.misses 3203 # DTB misses -system.cpu0.itb.accesses 56741815 # DTB accesses -system.cpu0.numCycles 2910043779 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 57470097 # ITB inst accesses +system.cpu0.itb.hits 57466570 # DTB hits +system.cpu0.itb.misses 3527 # DTB misses +system.cpu0.itb.accesses 57470097 # DTB accesses +system.cpu0.numCycles 2904046767 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu0.committedInsts 55199902 # Number of instructions committed -system.cpu0.committedOps 66610456 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58846956 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5257 # Number of float alu accesses -system.cpu0.num_func_calls 4818664 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7556613 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58846956 # number of integer instructions -system.cpu0.num_fp_insts 5257 # number of float instructions -system.cpu0.num_int_register_reads 106933232 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40497320 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3778 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1482 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 240479401 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25666284 # number of times the CC registers were written -system.cpu0.num_mem_refs 22274939 # number of memory refs -system.cpu0.num_load_insts 12196843 # Number of load instructions -system.cpu0.num_store_insts 10078096 # Number of store instructions -system.cpu0.num_idle_cycles 2694635007.442764 # Number of idle cycles -system.cpu0.num_busy_cycles 215408771.557236 # Number of busy cycles -system.cpu0.not_idle_fraction 0.074023 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.925977 # Percentage of idle cycles -system.cpu0.Branches 12742817 # Number of branches fetched -system.cpu0.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 45792240 67.22% 67.22% # Class of executed instruction -system.cpu0.op_class::IntMult 56099 0.08% 67.30% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3963 0.01% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::MemRead 12196843 17.90% 85.21% # Class of executed instruction -system.cpu0.op_class::MemWrite 10078096 14.79% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed +system.cpu0.committedInsts 55929982 # Number of instructions committed +system.cpu0.committedOps 67277087 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59477787 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5777 # Number of float alu accesses +system.cpu0.num_func_calls 4936884 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7560751 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59477787 # number of integer instructions +system.cpu0.num_fp_insts 5777 # number of float instructions +system.cpu0.num_int_register_reads 108128339 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41101378 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4484 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1294 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 243146097 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25735731 # number of times the CC registers were written +system.cpu0.num_mem_refs 22502519 # number of memory refs +system.cpu0.num_load_insts 12359077 # Number of load instructions +system.cpu0.num_store_insts 10143442 # Number of store instructions +system.cpu0.num_idle_cycles 2686489862.931067 # Number of idle cycles +system.cpu0.num_busy_cycles 217556904.068932 # Number of busy cycles +system.cpu0.not_idle_fraction 0.074915 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.925085 # Percentage of idle cycles +system.cpu0.Branches 12907844 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46271329 67.22% 67.22% # Class of executed instruction +system.cpu0.op_class::IntMult 59336 0.09% 67.31% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4393 0.01% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.31% # Class of executed instruction +system.cpu0.op_class::MemRead 12359077 17.95% 85.27% # Class of executed instruction +system.cpu0.op_class::MemWrite 10143442 14.73% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68127374 # Class of executed instruction -system.cpu0.dcache.tags.replacements 819099 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.702232 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43234609 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819611 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.750157 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.298558 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.403674 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084567 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914851 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy +system.cpu0.op_class::total 68839780 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819212 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.827217 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43241766 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819724 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.751616 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1013369500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.161528 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.665688 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.607737 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.391925 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177105423 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177105423 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11354436 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11757578 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23112014 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9226475 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9597217 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18823692 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190286 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202415 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392701 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 213920 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 229309 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443229 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 221967 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 238239 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460206 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20580911 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21354795 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41935706 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20771197 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21557210 # number of overall hits -system.cpu0.dcache.overall_hits::total 42328407 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 199328 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 200534 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 399862 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 149618 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 149039 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298657 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58774 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59550 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118324 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10841 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11919 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22760 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 177132709 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177132709 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11490299 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11626239 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23116538 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9270780 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9555063 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18825843 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200211 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192673 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392884 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 225024 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 218448 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443472 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 232922 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 227346 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20761079 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21181302 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41942381 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20961290 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21373975 # number of overall hits +system.cpu0.dcache.overall_hits::total 42335265 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 199689 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 200118 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 399807 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 142721 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 155928 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298649 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 162000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12800137000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 12046217500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24846354500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13597399500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12864629500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26462029000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3048418500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3229696000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278114500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3048418500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3229696000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6278114500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017211 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016733 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016968 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015292 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015618 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231519 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223736 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227529 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017071 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019430 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018292 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2766355500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2792156000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5558511500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5618221000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6706526000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12324747000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 723870500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 803461500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1527332000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48171500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 60949500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109121000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 164000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 164000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8384576500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9498682000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 17883258500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9108447000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10302143500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 19410590500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2834492500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3446734000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6281226500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2834492500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3446734000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6281226500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017058 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016889 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016973 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015161 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016057 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015616 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218067 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.236746 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227346 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015855 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020807 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018301 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016649 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016086 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016363 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019176 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018562 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018864 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.755732 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14832.352133 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15176.477518 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64921.476694 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60912.499413 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62920.874113 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13826.480178 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13963.453959 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13895.526046 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13581.834767 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13506.614039 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.473956 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36732.498443 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34503.134899 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35616.754085 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33480.329007 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31550.673828 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32513.588065 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203227.900000 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200129.879787 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.278245 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 107376.488200 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106460.625639 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106903.374938 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 1695677 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.436645 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113855199 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1696189 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.124123 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 29075840500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 59.966796 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.469848 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117123 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879824 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016212 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016514 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018642 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019080 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13872.841110 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13979.302576 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13926.115452 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39365.061904 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43010.678074 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41268.473253 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12907.128720 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13366.742085 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13144.898100 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12880.080214 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12726.978492 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.114199 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 82000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24507.061664 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26707.047703 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25628.388013 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22873.361426 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24778.408066 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.432296 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196512.236550 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 206218.379801 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201722.220438 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95931.651267 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118119.739548 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 106956.365896 # average overall mshr uncacheable latency +system.cpu0.icache.tags.replacements 1697986 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.728403 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113871932 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1698498 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.042724 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 25838751500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 416.287276 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 94.441127 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.813061 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.184455 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997516 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117247589 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117247589 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 55898438 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 57956761 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113855199 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 55898438 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 57956761 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113855199 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 55898438 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 57956761 # 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mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014527 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.488887 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.488887 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12710.712747 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12853.130346 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.488887 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 76179.006872 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 76179.006872 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 76179.006872 # average overall mshr uncacheable latency system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1000,57 +998,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6953 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6953 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2221 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4731 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walks 6555 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6555 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1891 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4663 # Level at which table walker walks with short descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 6952 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6952 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6952 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5860 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13274.317406 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11562.470731 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7349.012526 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 5859 99.98% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5860 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 292297068 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean -4.609996 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1639785500 561.00% 561.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -1347488432 -461.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 292297068 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3658 62.43% 62.43% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 2201 37.57% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5859 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6953 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::samples 6554 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6554 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6554 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5423 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12314.493823 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10586.515921 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7100.180026 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 4356 80.32% 80.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 1063 19.60% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-98303 2 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-114687 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5423 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1582538528 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.367973 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.482254 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000207500 63.20% 63.20% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 582331028 36.80% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1582538528 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3557 65.60% 65.60% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1865 34.40% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5422 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6555 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6953 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5859 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6555 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5422 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5859 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12812 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5422 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11977 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12477429 # DTB read hits -system.cpu1.dtb.read_misses 5926 # DTB read misses -system.cpu1.dtb.write_hits 9996759 # DTB write hits -system.cpu1.dtb.write_misses 1027 # DTB write misses -system.cpu1.dtb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12327133 # DTB read hits +system.cpu1.dtb.read_misses 5631 # DTB read misses +system.cpu1.dtb.write_hits 9951025 # DTB write hits +system.cpu1.dtb.write_misses 924 # DTB write misses +system.cpu1.dtb.flush_tlb 2933 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4677 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4004 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 918 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 895 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12483355 # DTB read accesses -system.cpu1.dtb.write_accesses 9997786 # DTB write accesses +system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12332764 # DTB read accesses +system.cpu1.dtb.write_accesses 9951949 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22474188 # DTB hits -system.cpu1.dtb.misses 6953 # DTB misses -system.cpu1.dtb.accesses 22481141 # DTB accesses +system.cpu1.dtb.hits 22278158 # DTB hits +system.cpu1.dtb.misses 6555 # DTB misses +system.cpu1.dtb.accesses 22284713 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1080,119 +1082,121 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3501 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3501 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 842 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2659 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3501 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3501 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3501 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2700 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13966.111111 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12105.021463 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7193.126612 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1956 72.44% 72.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 743 27.52% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2700 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1858 68.81% 68.81% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 842 31.19% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2700 # Table walker page sizes translated +system.cpu1.itb.walker.walks 3197 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3197 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 694 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2503 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3197 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3197 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3197 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2377 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12629.995793 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10731.102955 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7036.590613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 768 32.31% 32.31% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1084 45.60% 77.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 512 21.54% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 12 0.50% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2377 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000178000 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000178000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000178000 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1683 70.80% 70.80% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 694 29.20% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2377 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3501 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3501 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3197 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3197 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2700 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2700 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 6201 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 58812782 # ITB inst hits -system.cpu1.itb.inst_misses 3501 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2377 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2377 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5574 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58103866 # ITB inst hits +system.cpu1.itb.inst_misses 3197 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2933 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 446 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2701 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2384 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 58816283 # ITB inst accesses -system.cpu1.itb.hits 58812782 # DTB hits -system.cpu1.itb.misses 3501 # DTB misses -system.cpu1.itb.accesses 58816283 # DTB accesses -system.cpu1.numCycles 2909245944 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58107063 # ITB inst accesses +system.cpu1.itb.hits 58103866 # DTB hits +system.cpu1.itb.misses 3197 # DTB misses +system.cpu1.itb.accesses 58107063 # DTB accesses +system.cpu1.numCycles 2903713042 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 57254309 # Number of instructions committed -system.cpu1.committedOps 68973710 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 61043070 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5904 # Number of float alu accesses -system.cpu1.num_func_calls 5072826 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7673629 # number of instructions that are conditional controls -system.cpu1.num_int_insts 61043070 # number of integer instructions -system.cpu1.num_fp_insts 5904 # number of float instructions -system.cpu1.num_int_register_reads 111123439 # number of times the integer registers were read -system.cpu1.num_int_register_writes 42146017 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4671 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1234 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 249248543 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26227592 # number of times the CC registers were written -system.cpu1.num_mem_refs 23131346 # number of memory refs -system.cpu1.num_load_insts 12645224 # Number of load instructions -system.cpu1.num_store_insts 10486122 # Number of store instructions -system.cpu1.num_idle_cycles 2689856281.302534 # Number of idle cycles -system.cpu1.num_busy_cycles 219389662.697466 # Number of busy cycles -system.cpu1.not_idle_fraction 0.075411 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.924589 # Percentage of idle cycles -system.cpu1.Branches 13172935 # Number of branches fetched -system.cpu1.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 47380499 67.13% 67.14% # Class of executed instruction -system.cpu1.op_class::IntMult 58319 0.08% 67.22% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4490 0.01% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::MemRead 12645224 17.92% 85.14% # Class of executed instruction -system.cpu1.op_class::MemWrite 10486122 14.86% 100.00% # Class of executed instruction +system.cpu1.committedInsts 56542374 # Number of instructions committed +system.cpu1.committedOps 68331078 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 60434186 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5384 # Number of float alu accesses +system.cpu1.num_func_calls 4958421 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7671718 # number of instructions that are conditional controls +system.cpu1.num_int_insts 60434186 # number of integer instructions +system.cpu1.num_fp_insts 5384 # number of float instructions +system.cpu1.num_int_register_reads 109968089 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41558580 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3965 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1422 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 246670954 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26165253 # number of times the CC registers were written +system.cpu1.num_mem_refs 22910809 # number of memory refs +system.cpu1.num_load_insts 12487681 # Number of load instructions +system.cpu1.num_store_insts 10423128 # Number of store instructions +system.cpu1.num_idle_cycles 2692724474.472886 # Number of idle cycles +system.cpu1.num_busy_cycles 210988567.527115 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072662 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927338 # Percentage of idle cycles +system.cpu1.Branches 13013850 # Number of branches fetched +system.cpu1.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 46919270 67.13% 67.13% # Class of executed instruction +system.cpu1.op_class::IntMult 55219 0.08% 67.21% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4062 0.01% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.22% # Class of executed instruction +system.cpu1.op_class::MemRead 12487681 17.87% 85.09% # Class of executed instruction +system.cpu1.op_class::MemWrite 10423128 14.91% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 70576858 # Class of executed instruction -system.iobus.trans_dist::ReadReq 30177 # Transaction distribution -system.iobus.trans_dist::ReadResp 30177 # Transaction distribution +system.cpu1.op_class::total 69889494 # Class of executed instruction +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) @@ -1215,9 +1219,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -1238,22 +1242,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 46333000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 337000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 95500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 644000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 643000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1273,56 +1277,56 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6284000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36457000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36462000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187070020 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187660851 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084263 # Cycle average of tags in use +system.iocache.tags.replacements 36424 # number of replacements +system.iocache.tags.tagsinuse 1.079319 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313834387000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084263 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067766 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067766 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309377087000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.079319 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067457 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067457 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328068 # Number of tag accesses -system.iocache.tags.data_accesses 328068 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 228 # number of ReadReq misses -system.iocache.ReadReq_misses::total 228 # number of ReadReq misses +system.iocache.tags.tag_accesses 328122 # Number of tag accesses +system.iocache.tags.data_accesses 328122 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses +system.iocache.ReadReq_misses::total 234 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36452 # number of demand (read+write) misses -system.iocache.demand_misses::total 36452 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36452 # number of overall misses -system.iocache.overall_misses::total 36452 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28181877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28181877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4548907143 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4548907143 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4577089020 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4577089020 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4577089020 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4577089020 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36458 # number of demand (read+write) misses +system.iocache.demand_misses::total 36458 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36458 # number of overall misses +system.iocache.overall_misses::total 36458 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28898377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28898377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4277821474 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4277821474 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4306719851 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4306719851 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4306719851 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4306719851 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36452 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36452 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36452 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36452 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36458 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36458 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36458 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36458 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -1331,14 +1335,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123604.723684 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123604.723684 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125577.162737 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125577.162737 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125564.825524 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125564.825524 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125564.825524 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125564.825524 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 123497.337607 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123497.337607 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118093.569843 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118093.569843 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118128.253086 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118128.253086 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118128.253086 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118128.253086 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1347,22 +1351,22 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 228 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36452 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36452 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36452 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36452 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16781877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16781877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736290629 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2736290629 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2753072506 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2753072506 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2753072506 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2753072506 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36458 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36458 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36458 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36458 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17198377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17198377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2464512228 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2464512228 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2481710605 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2481710605 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2481710605 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2481710605 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1371,494 +1375,520 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73604.723684 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73604.723684 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75538.058442 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75538.058442 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75525.965818 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75525.965818 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75525.965818 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75525.965818 # average overall mshr miss latency -system.l2c.tags.replacements 87562 # number of replacements -system.l2c.tags.tagsinuse 64865.213908 # Cycle average of tags in use -system.l2c.tags.total_refs 4551019 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 152797 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.784741 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73497.337607 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73497.337607 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68035.341983 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68035.341983 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68070.398952 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68070.398952 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68070.398952 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68070.398952 # average overall mshr miss latency +system.l2c.tags.replacements 88930 # number of replacements +system.l2c.tags.tagsinuse 64921.564367 # Cycle average of tags in use +system.l2c.tags.total_refs 4554585 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 154189 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.538975 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50199.163746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905024 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4089.871618 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2504.674114 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000605 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5610.944787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2455.815915 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062406 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.038218 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.085616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037473 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65231 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56202 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995346 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40564313 # Number of tag accesses -system.l2c.tags.data_accesses 40564313 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5816 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3025 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6360 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3489 # number of ReadReq hits -system.l2c.ReadReq_hits::total 18690 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 683901 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 683901 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1664900 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1664900 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 80918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 86062 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166980 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 832345 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 845838 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1678183 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 253790 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 257782 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 511572 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5816 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3025 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 832345 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 334708 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6360 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3489 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 845838 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 343844 # number of demand (read+write) hits -system.l2c.demand_hits::total 2375425 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5816 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3025 # number of overall hits -system.l2c.overall_hits::cpu0.inst 832345 # number of overall hits -system.l2c.overall_hits::cpu0.data 334708 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6360 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3489 # number of overall hits -system.l2c.overall_hits::cpu1.inst 845838 # number of overall hits -system.l2c.overall_hits::cpu1.data 343844 # number of overall hits -system.l2c.overall_hits::total 2375425 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses +system.l2c.tags.occ_blocks::writebacks 50439.038395 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.855329 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000489 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4115.597994 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2621.496048 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.860554 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.964520 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5480.404826 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2258.346213 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.769639 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062799 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.040001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.083624 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.034460 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990624 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65253 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6981 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56097 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.995682 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 40592424 # Number of tag accesses +system.l2c.tags.data_accesses 40592424 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6056 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3327 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5249 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2715 # number of ReadReq hits +system.l2c.ReadReq_hits::total 17347 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 683633 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 683633 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1666927 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1666927 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 83399 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 82059 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 165458 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 846260 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 834237 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1680497 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 253600 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 258179 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 511779 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6056 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3327 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 846260 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 336999 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5249 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2715 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 834237 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 340238 # number of demand (read+write) hits +system.l2c.demand_hits::total 2375081 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6056 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3327 # number of overall hits +system.l2c.overall_hits::cpu0.inst 846260 # number of overall hits +system.l2c.overall_hits::cpu0.data 336999 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5249 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2715 # number of overall hits +system.l2c.overall_hits::cpu1.inst 834237 # number of overall hits +system.l2c.overall_hits::cpu1.data 340238 # number of overall hits +system.l2c.overall_hits::total 2375081 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1389 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1353 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses +system.l2c.ReadReq_misses::total 10 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1330 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1405 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2735 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67296 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 61616 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128912 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 7811 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 10168 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 17979 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 6560 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 5611 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 12171 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7811 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73856 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu0.data 57981 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 72450 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130431 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 8141 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 9842 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 17983 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 5631 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 6454 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 12085 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 8141 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 63612 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 67227 # number of demand (read+write) misses -system.l2c.demand_misses::total 159070 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7811 # number of overall misses -system.l2c.overall_misses::cpu0.data 73856 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses +system.l2c.demand_misses::cpu1.inst 9842 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 78904 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 695720000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5319316000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10927757000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 574512000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2654142000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3237757500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6466411500 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 574512000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2654142000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3237757500 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.180770 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011878 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.163541 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062762 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.180770 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000471 # 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average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116739.144971 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117299.126850 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117006.799212 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120763.335002 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122962.271341 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121727.766886 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122393.147646 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117291.892331 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117668.756601 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 117843.801471 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117291.892331 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117668.756601 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 117843.801471 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190724.666667 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187626.471682 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172283.466135 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 100770.341670 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99809.341728 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 102125.551669 # average overall mshr uncacheable latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.410108 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468905 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.440811 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011660 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010588 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.021722 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.024388 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023069 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.158787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000368 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011660 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.188251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063302 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000495 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000300 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.158787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000952 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000368 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011660 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.188251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063302 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 76550 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19035.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19026.334520 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19030.895795 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 70500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 67402.907849 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 66857.688061 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67100.056735 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71046.961019 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74933.404369 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73671.599008 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74259.536616 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68069.515186 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67415.035993 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68081.895719 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73666.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71479.855055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68069.515186 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70688.884373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67415.035993 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68081.895719 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184008.735441 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193715.298552 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 161016.222610 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63679.006872 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 89827.799777 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 110958.104866 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 95446.596998 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 325066 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 134283 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 482 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70546 # Transaction distribution +system.membus.trans_dist::ReadResp 70472 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117373 # Transaction distribution -system.membus.trans_dist::CleanEvict 6607 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118632 # Transaction distribution +system.membus.trans_dist::CleanEvict 6722 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4502 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 127157 # Transaction distribution -system.membus.trans_dist::ReadExResp 127157 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30386 # Transaction distribution +system.membus.trans_dist::ReadExReq 128664 # Transaction distribution +system.membus.trans_dist::ReadExResp 128664 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30312 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 434320 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 541912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 614797 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438547 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 546139 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 619036 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15302012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15465365 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15473916 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15637269 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17782485 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 390010 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size::total 17954389 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 498 # Total snoops (count) +system.membus.snoop_fanout::samples 267453 # Request fanout histogram +system.membus.snoop_fanout::mean 0.018325 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.134123 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 390010 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 262552 98.17% 98.17% # Request fanout histogram +system.membus.snoop_fanout::1 4901 1.83% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 390010 # Request fanout histogram -system.membus.reqLayer0.occupancy 90443000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 267453 # Request fanout histogram +system.membus.reqLayer0.occupancy 90452000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1721000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1730500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 823181865 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 831225033 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 943214000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 950845250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1187123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1219623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -1901,60 +1931,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5053855 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2538047 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 38136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5058603 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540370 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38310 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 250 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 250 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 74697 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2294848 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 74739 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2297326 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 801289 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1695677 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 141805 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 766075 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1697986 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 142067 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2759 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295892 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295892 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1696195 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 523971 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5106078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581570 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18395 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34840 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7740883 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217113784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96423069 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26060 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 313611645 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 176532 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2781330 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021292 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144357 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295889 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295889 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1698504 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 524085 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4401 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5113014 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581913 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17955 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 33981 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7746863 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217409912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96413853 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 45252 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313893193 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 111017 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2716898 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021705 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.145719 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2722109 97.87% 97.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 59221 2.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2657927 97.83% 97.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 58971 2.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2781330 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4961202000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2716898 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4965685500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 389377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2553314500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2556778000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1275768500 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1275944496 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11880000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11911000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22657000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22668000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 422618199..5987f38c7 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu sim_ticks 5112151729000 # Number of ticks simulated final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1369712 # Simulator instruction rate (inst/s) -host_op_rate 2804100 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34999130987 # Simulator tick rate (ticks/s) -host_mem_usage 614748 # Number of bytes of host memory used -host_seconds 146.07 # Real time elapsed on the host +host_inst_rate 1314225 # Simulator instruction rate (inst/s) +host_op_rate 2690507 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33581335470 # Simulator tick rate (ticks/s) +host_mem_usage 609616 # Number of bytes of host memory used +host_seconds 152.23 # Real time elapsed on the host sim_insts 200067055 # Number of instructions simulated sim_ops 409581065 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 94a3f35b5..303fd9f5f 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.194946 # Nu sim_ticks 5194946000500 # Number of ticks simulated final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 910377 # Simulator instruction rate (inst/s) -host_op_rate 1754736 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36822413305 # Simulator tick rate (ticks/s) -host_mem_usage 616280 # Number of bytes of host memory used -host_seconds 141.08 # Real time elapsed on the host +host_inst_rate 930999 # Simulator instruction rate (inst/s) +host_op_rate 1794485 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37656529565 # Simulator tick rate (ticks/s) +host_mem_usage 609616 # Number of bytes of host memory used +host_seconds 137.96 # Real time elapsed on the host sim_insts 128436892 # Number of instructions simulated sim_ops 247560077 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index d62937167..ff7ec9f90 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu sim_ticks 200409271000 # Number of ticks simulated final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 7747436 # Simulator instruction rate (inst/s) -host_op_rate 7747432 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2964324473 # Simulator tick rate (ticks/s) -host_mem_usage 475456 # Number of bytes of host memory used -host_seconds 67.61 # Real time elapsed on the host +host_inst_rate 17114164 # Simulator instruction rate (inst/s) +host_op_rate 17114158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6548224120 # Simulator tick rate (ticks/s) +host_mem_usage 490760 # Number of bytes of host memory used +host_seconds 30.61 # Real time elapsed on the host sim_insts 523780905 # Number of instructions simulated sim_ops 523780905 # Number of ops (including micro ops) simulated drivesys.voltage_domain.voltage 1 # Voltage in Volts @@ -619,11 +619,11 @@ sim_seconds 0.000407 # Nu sim_ticks 407341500 # Number of ticks simulated final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3441354505 # Simulator instruction rate (inst/s) -host_op_rate 3440623178 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2674872126 # Simulator tick rate (ticks/s) -host_mem_usage 475456 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 9054438128 # Simulator instruction rate (inst/s) +host_op_rate 9052667837 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7037972394 # Simulator tick rate (ticks/s) +host_mem_usage 490760 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 523853183 # Number of instructions simulated sim_ops 523853183 # Number of ops (including micro ops) simulated drivesys.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index 0faba0dc5..6544ab634 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000037 # Nu sim_ticks 37494000 # Number of ticks simulated final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141195 # Simulator instruction rate (inst/s) -host_op_rate 141164 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 825166364 # Simulator tick rate (ticks/s) -host_mem_usage 252900 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 176621 # Simulator instruction rate (inst/s) +host_op_rate 176529 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1031613588 # Simulator tick rate (ticks/s) +host_mem_usage 248004 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6413 # Number of instructions simulated sim_ops 6413 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index c082db4f6..ead74abf4 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 22019000 # Number of ticks simulated final_tick 22019000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140516 # Simulator instruction rate (inst/s) -host_op_rate 140486 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 484379589 # Simulator tick rate (ticks/s) -host_mem_usage 253664 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 115969 # Simulator instruction rate (inst/s) +host_op_rate 115940 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 399737091 # Simulator tick rate (ticks/s) +host_mem_usage 249288 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6385 # Number of instructions simulated sim_ops 6385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index a9b70663c..9a58520d3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3214500 # Number of ticks simulated final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 21023 # Simulator instruction rate (inst/s) -host_op_rate 21020 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10551583 # Simulator tick rate (ticks/s) -host_mem_usage 216888 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host +host_inst_rate 1011674 # Simulator instruction rate (inst/s) +host_op_rate 1009913 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 506215370 # Simulator tick rate (ticks/s) +host_mem_usage 237756 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 7c6c13cf7..e07863c49 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu sim_ticks 121535 # Number of ticks simulated final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23854 # Simulator instruction rate (inst/s) -host_op_rate 23852 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 452710 # Simulator tick rate (ticks/s) -host_mem_usage 387364 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 71837 # Simulator instruction rate (inst/s) +host_op_rate 71828 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1363198 # Simulator tick rate (ticks/s) +host_mem_usage 407704 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 58f4afdee..86b91c7c5 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000109 # Nu sim_ticks 108878 # Number of ticks simulated final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 17471 # Simulator instruction rate (inst/s) -host_op_rate 17470 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 297052 # Simulator tick rate (ticks/s) -host_mem_usage 393472 # Number of bytes of host memory used -host_seconds 0.37 # Real time elapsed on the host +host_inst_rate 68389 # Simulator instruction rate (inst/s) +host_op_rate 68380 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1162621 # Simulator tick rate (ticks/s) +host_mem_usage 413676 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 5e0571904..bdd21635f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu sim_ticks 108253 # Number of ticks simulated final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 39556 # Simulator instruction rate (inst/s) -host_op_rate 39552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 668635 # Simulator tick rate (ticks/s) -host_mem_usage 388512 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 4411 # Simulator instruction rate (inst/s) +host_op_rate 4411 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 74577 # Simulator tick rate (ticks/s) +host_mem_usage 409256 # Number of bytes of host memory used +host_seconds 1.45 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index 7e8297657..463ba3cfb 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu sim_ticks 86770 # Number of ticks simulated final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 43915 # Simulator instruction rate (inst/s) -host_op_rate 43910 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 594975 # Simulator tick rate (ticks/s) -host_mem_usage 388108 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 99240 # Simulator instruction rate (inst/s) +host_op_rate 99218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1344283 # Simulator tick rate (ticks/s) +host_mem_usage 407932 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index 0d68fa8cb..d5526ad82 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu sim_ticks 107065 # Number of ticks simulated final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18652 # Simulator instruction rate (inst/s) -host_op_rate 18652 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 311861 # Simulator tick rate (ticks/s) -host_mem_usage 390536 # Number of bytes of host memory used -host_seconds 0.34 # Real time elapsed on the host +host_inst_rate 109103 # Simulator instruction rate (inst/s) +host_op_rate 109072 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1823360 # Simulator tick rate (ticks/s) +host_mem_usage 411068 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 1dfe1dcb3..4c1b7f48d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000036 # Nu sim_ticks 35682500 # Number of ticks simulated final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 421865 # Simulator instruction rate (inst/s) -host_op_rate 421312 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2345119890 # Simulator tick rate (ticks/s) -host_mem_usage 251096 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 581025 # Simulator instruction rate (inst/s) +host_op_rate 580437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3231677275 # Simulator tick rate (ticks/s) +host_mem_usage 247496 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6403 # Number of instructions simulated sim_ops 6403 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 165263111..f75116dfd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20320000 # Number of ticks simulated final_tick 20320000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183657 # Simulator instruction rate (inst/s) -host_op_rate 183501 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1441333472 # Simulator tick rate (ticks/s) -host_mem_usage 251592 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 154508 # Simulator instruction rate (inst/s) +host_op_rate 154391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1212791416 # Simulator tick rate (ticks/s) +host_mem_usage 246696 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 86178d83d..92634ef37 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 12409500 # Number of ticks simulated final_tick 12409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67215 # Simulator instruction rate (inst/s) -host_op_rate 67181 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 349098234 # Simulator tick rate (ticks/s) -host_mem_usage 252356 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 87055 # Simulator instruction rate (inst/s) +host_op_rate 87008 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 452104980 # Simulator tick rate (ticks/s) +host_mem_usage 247976 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index ff4b92b39..8171db450 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54662 # Simulator instruction rate (inst/s) -host_op_rate 54627 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27487977 # Simulator tick rate (ticks/s) -host_mem_usage 219680 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 461545 # Simulator instruction rate (inst/s) +host_op_rate 460635 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 231518490 # Simulator tick rate (ticks/s) +host_mem_usage 237472 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index a9f8176e1..cb06e619e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000046 # Nu sim_ticks 45733 # Number of ticks simulated final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 42490 # Simulator instruction rate (inst/s) -host_op_rate 42477 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 753627 # Simulator tick rate (ticks/s) -host_mem_usage 411088 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 63739 # Simulator instruction rate (inst/s) +host_op_rate 63721 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1130531 # Simulator tick rate (ticks/s) +host_mem_usage 407420 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index be4c58d22..f80632a35 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu sim_ticks 41712 # Number of ticks simulated final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 38081 # Simulator instruction rate (inst/s) -host_op_rate 38070 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 616024 # Simulator tick rate (ticks/s) -host_mem_usage 414508 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 64355 # Simulator instruction rate (inst/s) +host_op_rate 64336 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1041083 # Simulator tick rate (ticks/s) +host_mem_usage 410320 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 6e16bb481..03e04136e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000041 # Nu sim_ticks 40527 # Number of ticks simulated final_tick 40527 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 25710 # Simulator instruction rate (inst/s) -host_op_rate 25704 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 404148 # Simulator tick rate (ticks/s) -host_mem_usage 390780 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 1955 # Simulator instruction rate (inst/s) +host_op_rate 1955 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30751 # Simulator tick rate (ticks/s) +host_mem_usage 407948 # Number of bytes of host memory used +host_seconds 1.32 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 08266d48d..2707b659f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu sim_ticks 32936 # Number of ticks simulated final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 52774 # Simulator instruction rate (inst/s) -host_op_rate 52753 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 673978 # Simulator tick rate (ticks/s) -host_mem_usage 411572 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 83066 # Simulator instruction rate (inst/s) +host_op_rate 82987 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1059779 # Simulator tick rate (ticks/s) +host_mem_usage 407644 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index c437c6665..15c5cf0e9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu sim_ticks 41659 # Number of ticks simulated final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 41992 # Simulator instruction rate (inst/s) -host_op_rate 41979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 678429 # Simulator tick rate (ticks/s) -host_mem_usage 412928 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 92225 # Simulator instruction rate (inst/s) +host_op_rate 92177 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1489374 # Simulator tick rate (ticks/s) +host_mem_usage 407716 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 3011688bd..9736e3d18 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000018 # Nu sim_ticks 18239500 # Number of ticks simulated final_tick 18239500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 277034 # Simulator instruction rate (inst/s) -host_op_rate 276552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1954350939 # Simulator tick rate (ticks/s) -host_mem_usage 249792 # Number of bytes of host memory used +host_inst_rate 339288 # Simulator instruction rate (inst/s) +host_op_rate 338780 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2394585777 # Simulator tick rate (ticks/s) +host_mem_usage 246188 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index cb66660d4..605a65a27 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu sim_ticks 29977500 # Number of ticks simulated final_tick 29977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89930 # Simulator instruction rate (inst/s) -host_op_rate 105235 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 584953104 # Simulator tick rate (ticks/s) -host_mem_usage 268772 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 146522 # Simulator instruction rate (inst/s) +host_op_rate 171470 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 953185288 # Simulator tick rate (ticks/s) +host_mem_usage 264656 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 58e5912c9..8765a9cf5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17232500 # Number of ticks simulated final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43939 # Simulator instruction rate (inst/s) -host_op_rate 51450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 164826819 # Simulator tick rate (ticks/s) -host_mem_usage 269540 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 66942 # Simulator instruction rate (inst/s) +host_op_rate 78386 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 251130115 # Simulator tick rate (ticks/s) +host_mem_usage 265932 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index d43357405..f8ba6e8d6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18821000 # Number of ticks simulated final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49791 # Simulator instruction rate (inst/s) -host_op_rate 58299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 203978556 # Simulator tick rate (ticks/s) -host_mem_usage 266084 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 45352 # Simulator instruction rate (inst/s) +host_op_rate 53108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 185838458 # Simulator tick rate (ticks/s) +host_mem_usage 261708 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 9ffa594c7..bcfa49270 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 13445 # Simulator instruction rate (inst/s) -host_op_rate 15745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7889483 # Simulator tick rate (ticks/s) -host_mem_usage 237392 # Number of bytes of host memory used -host_seconds 0.34 # Real time elapsed on the host +host_inst_rate 274500 # Simulator instruction rate (inst/s) +host_op_rate 321069 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 160714630 # Simulator tick rate (ticks/s) +host_mem_usage 254660 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index e53928c68..6f1efaf21 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 30076 # Simulator instruction rate (inst/s) -host_op_rate 35217 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17644392 # Simulator tick rate (ticks/s) -host_mem_usage 236884 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 363981 # Simulator instruction rate (inst/s) +host_op_rate 425522 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 212904964 # Simulator tick rate (ticks/s) +host_mem_usage 254404 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index facfa8248..e99784abb 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 28298500 # Number of ticks simulated final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 441317 # Simulator instruction rate (inst/s) -host_op_rate 514292 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2726097982 # Simulator tick rate (ticks/s) -host_mem_usage 267744 # Number of bytes of host memory used +host_inst_rate 343617 # Simulator instruction rate (inst/s) +host_op_rate 400476 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2123290642 # Simulator tick rate (ticks/s) +host_mem_usage 263372 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 815eb0bfe..0194e3c6f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu sim_ticks 22532000 # Number of ticks simulated final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65525 # Simulator instruction rate (inst/s) -host_op_rate 65509 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 295199371 # Simulator tick rate (ticks/s) -host_mem_usage 251356 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 96442 # Simulator instruction rate (inst/s) +host_op_rate 96403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 434426491 # Simulator tick rate (ticks/s) +host_mem_usage 247240 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 9b5c0be15..df8a010ee 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2820500 # Number of ticks simulated final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42403 # Simulator instruction rate (inst/s) -host_op_rate 42398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21196256 # Simulator tick rate (ticks/s) -host_mem_usage 214708 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 876414 # Simulator instruction rate (inst/s) +host_op_rate 873362 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 435104956 # Simulator tick rate (ticks/s) +host_mem_usage 235716 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 4c477fff4..194e91ae7 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000100 # Nu sim_ticks 100232 # Number of ticks simulated final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 20831 # Simulator instruction rate (inst/s) -host_op_rate 20830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 370097 # Simulator tick rate (ticks/s) -host_mem_usage 389556 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 97717 # Simulator instruction rate (inst/s) +host_op_rate 97699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1735645 # Simulator tick rate (ticks/s) +host_mem_usage 410048 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index f975f616d..0e87b1f2c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000034 # Nu sim_ticks 33932500 # Number of ticks simulated final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 442497 # Simulator instruction rate (inst/s) -host_op_rate 441783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2653552582 # Simulator tick rate (ticks/s) -host_mem_usage 249064 # Number of bytes of host memory used +host_inst_rate 431758 # Simulator instruction rate (inst/s) +host_op_rate 430982 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2588300068 # Simulator tick rate (ticks/s) +host_mem_usage 244424 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 2c6934aef..9c7cb3cdb 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19908000 # Number of ticks simulated final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130311 # Simulator instruction rate (inst/s) -host_op_rate 130281 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 447700777 # Simulator tick rate (ticks/s) -host_mem_usage 249300 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 120043 # Simulator instruction rate (inst/s) +host_op_rate 120013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 412413617 # Simulator tick rate (ticks/s) +host_mem_usage 245176 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index e25b901ab..5dd437e9a 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76704 # Simulator instruction rate (inst/s) -host_op_rate 76683 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38324639 # Simulator tick rate (ticks/s) -host_mem_usage 216536 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 887311 # Simulator instruction rate (inst/s) +host_op_rate 885785 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 442112700 # Simulator tick rate (ticks/s) +host_mem_usage 234416 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 8bcf3caa4..0889a55c9 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62253 # Simulator instruction rate (inst/s) -host_op_rate 62235 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31469743 # Simulator tick rate (ticks/s) -host_mem_usage 218904 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 633206 # Simulator instruction rate (inst/s) +host_op_rate 631372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 318532177 # Simulator tick rate (ticks/s) +host_mem_usage 236156 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 24a3b23de..3a583092f 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000082 # Nu sim_ticks 81703 # Number of ticks simulated final_tick 81703 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 27831 # Simulator instruction rate (inst/s) -host_op_rate 27828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 426765 # Simulator tick rate (ticks/s) -host_mem_usage 393224 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 79389 # Simulator instruction rate (inst/s) +host_op_rate 79372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1217125 # Simulator tick rate (ticks/s) +host_mem_usage 409468 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index ddd387c47..ad6f58618 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000031 # Nu sim_ticks 30526500 # Number of ticks simulated final_tick 30526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 608531 # Simulator instruction rate (inst/s) -host_op_rate 607803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3479427932 # Simulator tick rate (ticks/s) -host_mem_usage 249516 # Number of bytes of host memory used +host_inst_rate 398653 # Simulator instruction rate (inst/s) +host_op_rate 397863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2276293986 # Simulator tick rate (ticks/s) +host_mem_usage 245124 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 3c1544f1d..4713d8f7c 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 21273500 # Number of ticks simulated final_tick 21273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70008 # Simulator instruction rate (inst/s) -host_op_rate 126817 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 276755373 # Simulator tick rate (ticks/s) -host_mem_usage 271684 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 54566 # Simulator instruction rate (inst/s) +host_op_rate 98846 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215714601 # Simulator tick rate (ticks/s) +host_mem_usage 266040 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index c4292eb87..dcd77e088 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26569 # Simulator instruction rate (inst/s) -host_op_rate 48126 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27718570 # Simulator tick rate (ticks/s) -host_mem_usage 237032 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 380560 # Simulator instruction rate (inst/s) +host_op_rate 688269 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 395838528 # Simulator tick rate (ticks/s) +host_mem_usage 254256 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 06e819e18..bf06f8c45 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87948 # Number of ticks simulated final_tick 87948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 28860 # Simulator instruction rate (inst/s) -host_op_rate 52275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 471584 # Simulator tick rate (ticks/s) -host_mem_usage 411784 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 77426 # Simulator instruction rate (inst/s) +host_op_rate 140230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1264887 # Simulator tick rate (ticks/s) +host_mem_usage 428592 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index b345a9c01..0e6d74be3 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000031 # Nu sim_ticks 30886500 # Number of ticks simulated final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235920 # Simulator instruction rate (inst/s) -host_op_rate 427054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1352150005 # Simulator tick rate (ticks/s) -host_mem_usage 266824 # Number of bytes of host memory used +host_inst_rate 324268 # Simulator instruction rate (inst/s) +host_op_rate 586988 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1858658321 # Simulator tick rate (ticks/s) +host_mem_usage 262968 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt index fcca5b721..458736244 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25580500 # Number of ticks simulated final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85448 # Simulator instruction rate (inst/s) -host_op_rate 85436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171120344 # Simulator tick rate (ticks/s) -host_mem_usage 253996 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 119260 # Simulator instruction rate (inst/s) +host_op_rate 119247 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238851205 # Simulator tick rate (ticks/s) +host_mem_usage 249876 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 12770 # Number of instructions simulated sim_ops 12770 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index e76497684..e69de29bb 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,947 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28845500 # Number of ticks simulated -final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68981 # Simulator instruction rate (inst/s) -host_op_rate 68975 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137812851 # Simulator tick rate (ticks/s) -host_mem_usage 251992 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host -sim_insts 14436 # Number of instructions simulated -sim_ops 14436 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory -system.physmem.bytes_read::total 32640 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory -system.physmem.num_reads::total 510 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 511 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 105 # Per bank write bursts -system.physmem.perBankRdBursts::1 28 # Per bank write bursts -system.physmem.perBankRdBursts::2 53 # Per bank write bursts -system.physmem.perBankRdBursts::3 27 # Per bank write bursts -system.physmem.perBankRdBursts::4 23 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 32 # Per bank write bursts -system.physmem.perBankRdBursts::7 38 # Per bank write bursts -system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 4 # Per bank write bursts -system.physmem.perBankRdBursts::10 2 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 57 # Per bank write bursts -system.physmem.perBankRdBursts::13 31 # Per bank write bursts -system.physmem.perBankRdBursts::14 63 # Per bank write bursts -system.physmem.perBankRdBursts::15 41 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 28814000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 511 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation -system.physmem.totQLat 3584250 # Total ticks spent queuing -system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.86 # Data bus utilization in percentage -system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 428 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 56387.48 # Average gap between requests -system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ) -system.physmem_0.averagePower 856.515480 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states -system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ) -system.physmem_1.averagePower 820.243027 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states -system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 12618 # Number of BP lookups -system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 57692 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed -system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 7933 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 7918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups -system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 796 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 25362 # Type of FU issued -system.cpu.iq.rate 0.439610 # Inst issue rate -system.cpu.iq.fu_busy_cnt 294 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1579 # number of nop insts executed -system.cpu.iew.exec_refs 6244 # number of memory reference insts executed -system.cpu.iew.exec_branches 5021 # Number of branches executed -system.cpu.iew.exec_stores 2299 # Number of stores executed -system.cpu.iew.exec_rate 0.411045 # Inst execution rate -system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 22607 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10530 # num instructions producing a value -system.cpu.iew.wb_consumers 13790 # num instructions consuming a value -system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle -system.cpu.commit.committedInsts 15162 # Number of instructions committed -system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 3673 # Number of memory references committed -system.cpu.commit.loads 2225 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 3358 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 12174 # Number of committed integer instructions. -system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 62581 # The number of ROB reads -system.cpu.rob.rob_writes 65380 # The number of ROB writes -system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 14436 # Number of Instructions Simulated -system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads -system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 36850 # number of integer regfile reads -system.cpu.int_regfile_writes 20548 # number of integer regfile writes -system.cpu.misc_regfile_reads 8142 # number of misc regfile reads -system.cpu.misc_regfile_writes 569 # number of misc regfile writes -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4642 # number of overall hits -system.cpu.dcache.overall_hits::total 4642 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 140 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 140 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 549 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses -system.cpu.dcache.overall_misses::total 549 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5191 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5191 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5191 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5191 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037343 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037343 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses -system.cpu.icache.tags.data_accesses 15425 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits -system.cpu.icache.overall_hits::total 6949 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 581 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses -system.cpu.icache.overall_misses::total 581 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 7530 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 7530 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 7530 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.077158 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.077158 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 216 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.048473 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.048473 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses -system.cpu.l2cache.overall_misses::total 511 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6452500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6452500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27176000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27176000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5013500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5013500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27176000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11466000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 38642000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27176000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11466000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 38642000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 426 # Transaction distribution -system.membus.trans_dist::ReadExReq 83 # Transaction distribution -system.membus.trans_dist::ReadExResp 83 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 511 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 511 # Request fanout histogram -system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt index af8e6136b..e69de29bb 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt @@ -1,124 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000008 # Number of seconds simulated -sim_ticks 7612000 # Number of ticks simulated -final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20450 # Simulator instruction rate (inst/s) -host_op_rate 20449 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10266040 # Simulator tick rate (ticks/s) -host_mem_usage 218684 # Number of bytes of host memory used -host_seconds 0.74 # Real time elapsed on the host -sim_insts 15162 # Number of instructions simulated -sim_ops 15162 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11342 # Number of bytes read from this memory -system.physmem.bytes_read::total 72170 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60828 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60828 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 9042 # Number of bytes written to this memory -system.physmem.bytes_written::total 9042 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15207 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2225 # Number of read requests responded to by this memory -system.physmem.num_reads::total 17432 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 1442 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1442 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 6 # Number of other requests responded to by this memory -system.physmem.num_other::total 6 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7991066737 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1490015765 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9481082501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7991066737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7991066737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1187861272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1187861272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 15225 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 15162 # Number of instructions committed -system.cpu.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 385 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls -system.cpu.num_int_insts 12219 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29037 # number of times the integer registers were read -system.cpu.num_int_register_writes 13819 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 3683 # number of memory refs -system.cpu.num_load_insts 2231 # Number of load instructions -system.cpu.num_store_insts 1452 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 15224.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 3363 # Number of branches fetched -system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction -system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction -system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 15207 # Class of executed instruction -system.membus.trans_dist::ReadReq 17432 # Transaction distribution -system.membus.trans_dist::ReadResp 17432 # Transaction distribution -system.membus.trans_dist::WriteReq 1442 # Transaction distribution -system.membus.trans_dist::WriteResp 1442 # Transaction distribution -system.membus.trans_dist::SwapReq 6 # Transaction distribution -system.membus.trans_dist::SwapResp 6 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 30414 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 7346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37760 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 60828 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 20442 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 81270 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 18880 # Request fanout histogram -system.membus.snoop_fanout::mean 0.805456 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.395860 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3673 19.45% 19.45% # Request fanout histogram -system.membus.snoop_fanout::1 15207 80.55% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 18880 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 457c52bd3..e69de29bb 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,474 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000044 # Number of seconds simulated -sim_ticks 44282500 # Number of ticks simulated -final_tick 44282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 298703 # Simulator instruction rate (inst/s) -host_op_rate 298583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 871748609 # Simulator tick rate (ticks/s) -host_mem_usage 249440 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 15162 # Number of instructions simulated -sim_ops 15162 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory -system.physmem.bytes_read::total 26624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory -system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 401784000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 199446734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 601230734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 401784000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 401784000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 401784000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 199446734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 601230734 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 88565 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 15162 # Number of instructions committed -system.cpu.committedOps 15162 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 12219 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 385 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 2434 # number of instructions that are conditional controls -system.cpu.num_int_insts 12219 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 29037 # number of times the integer registers were read -system.cpu.num_int_register_writes 13818 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 3683 # number of memory refs -system.cpu.num_load_insts 2231 # Number of load instructions -system.cpu.num_store_insts 1452 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 88564.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 3363 # Number of branches fetched -system.cpu.op_class::No_OpClass 726 4.77% 4.77% # Class of executed instruction -system.cpu.op_class::IntAlu 10798 71.01% 75.78% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% # Class of executed instruction -system.cpu.op_class::MemRead 2231 14.67% 90.45% # Class of executed instruction -system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 15207 # Class of executed instruction -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.148649 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.148649 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023718 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023718 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits -system.cpu.dcache.overall_hits::total 3529 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3286000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3286000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5270000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5270000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8556000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8556000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8556000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8556000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3233000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5185000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8418000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 151.748662 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 151.748662 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.074096 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.074096 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 30696 # Number of tag accesses -system.cpu.icache.tags.data_accesses 30696 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 14928 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14928 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14928 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14928 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14928 # number of overall hits -system.cpu.icache.overall_hits::total 14928 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses -system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17264500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17264500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17264500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17264500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17264500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17264500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15208 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15208 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15208 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.018411 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61658.928571 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61658.928571 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61658.928571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61658.928571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61658.928571 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16984500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16984500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16984500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16984500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60658.928571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60658.928571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60658.928571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60658.928571 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 182.297739 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 151.068800 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.228940 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000953 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005563 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 276 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010101 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5057500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5057500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16541500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16541500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3153500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3153500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16541500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8211000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24752500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16541500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8211000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24752500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 280 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 53 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995215 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.201923 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.201923 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4207500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4207500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13761500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13761500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2623500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2623500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13761500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6831000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20592500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13761500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6831000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20592500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.201923 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.004785 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadResp 331 # Transaction distribution -system.membus.trans_dist::ReadExReq 85 # Transaction distribution -system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 331 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 416 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 416 # Request fanout histogram -system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2080000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.7 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt index 1b652ed70..3711ab70b 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000405 # Nu sim_ticks 405365000 # Number of ticks simulated final_tick 405365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83628 # Simulator instruction rate (inst/s) -host_op_rate 83610 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5251060650 # Simulator tick rate (ticks/s) -host_mem_usage 610048 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 217578 # Simulator instruction rate (inst/s) +host_op_rate 217432 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13650898473 # Simulator tick rate (ticks/s) +host_mem_usage 630716 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt index 3c13d46b0..57afd555e 100644 --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000061 # Nu sim_ticks 61470000 # Number of ticks simulated final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 583425 # Simulator instruction rate (inst/s) -host_op_rate 580281 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5518802940 # Simulator tick rate (ticks/s) -host_mem_usage 637904 # Number of bytes of host memory used +host_inst_rate 556042 # Simulator instruction rate (inst/s) +host_op_rate 555477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5286056763 # Simulator tick rate (ticks/s) +host_mem_usage 634812 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6453 # Number of instructions simulated sim_ops 6453 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt index 5a6464d85..6a638c326 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000326 # Nu sim_ticks 325849000 # Number of ticks simulated final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67062 # Simulator instruction rate (inst/s) -host_op_rate 77548 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4377845869 # Simulator tick rate (ticks/s) -host_mem_usage 629736 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 156546 # Simulator instruction rate (inst/s) +host_op_rate 180975 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10214317316 # Simulator tick rate (ticks/s) +host_mem_usage 647364 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 60d51d141..1fca855be 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 523400 # Simulator instruction rate (inst/s) -host_op_rate 604831 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5220928914 # Simulator tick rate (ticks/s) -host_mem_usage 655332 # Number of bytes of host memory used +host_inst_rate 388067 # Simulator instruction rate (inst/s) +host_op_rate 448196 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3866626926 # Simulator tick rate (ticks/s) +host_mem_usage 651460 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt index 4088c6bf9..9cc36ad4e 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000369 # Nu sim_ticks 368887000 # Number of ticks simulated final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25687 # Simulator instruction rate (inst/s) -host_op_rate 25686 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1679592961 # Simulator tick rate (ticks/s) -host_mem_usage 607900 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 294016 # Simulator instruction rate (inst/s) +host_op_rate 293668 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19182713753 # Simulator tick rate (ticks/s) +host_mem_usage 628676 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt index 2c65c222a..f4dfddbc8 100644 --- a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000059 # Nu sim_ticks 58892000 # Number of ticks simulated final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 350541 # Simulator instruction rate (inst/s) -host_op_rate 350101 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3650563038 # Simulator tick rate (ticks/s) -host_mem_usage 636120 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 509573 # Simulator instruction rate (inst/s) +host_op_rate 509069 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5309891860 # Simulator tick rate (ticks/s) +host_mem_usage 632772 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5641 # Number of instructions simulated sim_ops 5641 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt index 05b70a5db..aae0960f1 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000333 # Nu sim_ticks 333033000 # Number of ticks simulated final_tick 333033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75807 # Simulator instruction rate (inst/s) -host_op_rate 75776 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4546866876 # Simulator tick rate (ticks/s) -host_mem_usage 611808 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 348800 # Simulator instruction rate (inst/s) +host_op_rate 348537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20908249754 # Simulator tick rate (ticks/s) +host_mem_usage 629116 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index 718f7b51e..f9225f3bc 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000053 # Nu sim_ticks 53334000 # Number of ticks simulated final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 388058 # Simulator instruction rate (inst/s) -host_op_rate 387570 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3721714769 # Simulator tick rate (ticks/s) -host_mem_usage 636836 # Number of bytes of host memory used +host_inst_rate 429905 # Simulator instruction rate (inst/s) +host_op_rate 429380 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4122052129 # Simulator tick rate (ticks/s) +host_mem_usage 633208 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt index f579e14d0..f88f09a70 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000445 # Nu sim_ticks 445082000 # Number of ticks simulated final_tick 445082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66069 # Simulator instruction rate (inst/s) -host_op_rate 119271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5145784728 # Simulator tick rate (ticks/s) -host_mem_usage 629884 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 211115 # Simulator instruction rate (inst/s) +host_op_rate 380995 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16432986499 # Simulator tick rate (ticks/s) +host_mem_usage 647212 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt index e0706d7d4..78bfc0a03 100644 --- a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000056 # Nu sim_ticks 55844000 # Number of ticks simulated final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 250477 # Simulator instruction rate (inst/s) -host_op_rate 451948 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2445398371 # Simulator tick rate (ticks/s) -host_mem_usage 655164 # Number of bytes of host memory used +host_inst_rate 299396 # Simulator instruction rate (inst/s) +host_op_rate 540174 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2922543083 # Simulator tick rate (ticks/s) +host_mem_usage 651308 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5712 # Number of instructions simulated sim_ops 10314 # Number of ops (including micro ops) simulated diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt index 092f1ac37..1711c0a9f 100644 --- a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000663 # Nu sim_ticks 663454500 # Number of ticks simulated final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97803 # Simulator instruction rate (inst/s) -host_op_rate 201121 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 968968514 # Simulator tick rate (ticks/s) -host_mem_usage 1290208 # Number of bytes of host memory used -host_seconds 0.68 # Real time elapsed on the host +host_inst_rate 153021 # Simulator instruction rate (inst/s) +host_op_rate 314663 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1515963159 # Simulator tick rate (ticks/s) +host_mem_usage 1308268 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host sim_insts 66963 # Number of instructions simulated sim_ops 137705 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index f57e8a542..e69de29bb 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,243 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.054141 # Number of seconds simulated -sim_ticks 54141000500 # Number of ticks simulated -final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 763855 # Simulator instruction rate (inst/s) -host_op_rate 767659 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 456454296 # Simulator tick rate (ticks/s) -host_mem_usage 371948 # Number of bytes of host memory used -host_seconds 118.61 # Real time elapsed on the host -sim_insts 90602408 # Number of instructions simulated -sim_ops 91053639 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory -system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 431323084 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 431323084 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory -system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 107830771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130292303 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory -system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7966662604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1662632703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9629295306 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7966662604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7966662604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 349238799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 349238799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 108282002 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90602408 # Number of instructions committed -system.cpu.committedOps 91053639 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls -system.cpu.num_int_insts 72326352 # number of integer instructions -system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read -system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written -system.cpu.num_fp_register_reads 54 # number of times the floating registers were read -system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 271814243 # number of times the CC registers were read -system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written -system.cpu.num_mem_refs 27220755 # number of memory refs -system.cpu.num_load_insts 22475911 # Number of load instructions -system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 108282001.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732305 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054081 # Class of executed instruction -system.membus.trans_dist::ReadReq 130287906 # Transaction distribution -system.membus.trans_dist::ReadResp 130291793 # Transaction distribution -system.membus.trans_dist::WriteReq 4734981 # Transaction distribution -system.membus.trans_dist::WriteResp 4734981 # Transaction distribution -system.membus.trans_dist::SoftPFReq 510 # Transaction distribution -system.membus.trans_dist::SoftPFResp 510 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 270062342 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 135031171 # Request fanout histogram -system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 135031171 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 93c64ae72..e69de29bb 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,648 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.147149 # Number of seconds simulated -sim_ticks 147148719500 # Number of ticks simulated -final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1067474 # Simulator instruction rate (inst/s) -host_op_rate 1072778 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1734188097 # Simulator tick rate (ticks/s) -host_mem_usage 402040 # Number of bytes of host memory used -host_seconds 84.85 # Real time elapsed on the host -sim_insts 90576862 # Number of instructions simulated -sim_ops 91026991 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory -system.physmem.bytes_read::total 981760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 250957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6420933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6671890 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 250957 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 250957 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 250957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6420933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6671890 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294297439 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90576862 # Number of instructions committed -system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls -system.cpu.num_int_insts 72326352 # number of integer instructions -system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read -system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written -system.cpu.num_fp_register_reads 54 # number of times the floating registers were read -system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read -system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written -system.cpu.num_mem_refs 27220755 # number of memory refs -system.cpu.num_load_insts 22475911 # Number of load instructions -system.cpu.num_store_insts 4744844 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294297438.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732305 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction -system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction -system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction -system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054081 # Class of executed instruction -system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.478025 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54453325500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.478025 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.870478 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.870478 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1357 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits -system.cpu.dcache.overall_hits::total 26245827 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses -system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713009000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11713009000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1319019500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1319019500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13032028500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13032028500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13032028500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13032028500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.750892 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.750892 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28299.673883 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28299.673883 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13764.346808 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13764.346808 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13764.303194 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13764.303194 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks -system.cpu.dcache.writebacks::total 942334 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812776000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1272410500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1272410500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 134000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 134000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12085186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12085186500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12085320500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12085320500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.713135 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.713135 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27299.673883 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27299.673883 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12764.311704 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12764.311704 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12764.412789 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12764.412789 # average overall mshr miss latency -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.111710 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.111710 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.249078 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.249078 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses -system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits -system.cpu.icache.overall_hits::total 107830173 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses -system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 36093000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 36093000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 36093000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 36093000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 36093000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 36093000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60255.425710 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60255.425710 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60255.425710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60255.425710 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60255.425710 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2 # number of writebacks -system.cpu.icache.writebacks::total 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 599 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35494000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35494000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35494000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35494000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35494000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35494000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 59255.425710 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59255.425710 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 59255.425710 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 59255.425710 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9564.658425 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1827433 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 119.260784 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8876.269803 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.164592 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 194.224030 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.270882 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.005927 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.291890 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1473 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 15181828 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 15181828 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 942334 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 22 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 899974 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22 # 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number of overall misses -system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 865856500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 865856500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34343500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 34343500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12794500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 12794500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 34343500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 878651000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 912994500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 34343500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 878651000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 912994500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 942334 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 46609 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 599 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 900189 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 599 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 946798 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 947397 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59517.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59520.797227 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59520.797227 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59509.302326 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59509.302326 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59517.242503 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59520.797227 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59517.103570 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59517.242503 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 720376500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 720376500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 28573500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 28573500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10644500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10644500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28573500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 731021000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 759594500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28573500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 731021000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 759594500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49517.218862 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49520.797227 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49509.302326 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49520.797227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49517.103570 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49517.242503 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 947397 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 792 # Transaction distribution -system.membus.trans_dist::ReadExReq 14548 # Transaction distribution -system.membus.trans_dist::ReadExResp 14548 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 792 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 30680 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15340 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15340 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15604500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 76700000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index b85047da6..e69de29bb 100644 --- a/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,124 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.122216 # Number of seconds simulated -sim_ticks 122215823500 # Number of ticks simulated -final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1145191 # Simulator instruction rate (inst/s) -host_op_rate 1145238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 574019671 # Simulator tick rate (ticks/s) -host_mem_usage 353116 # Number of bytes of host memory used -host_seconds 212.91 # Real time elapsed on the host -sim_insts 243825150 # Number of instructions simulated -sim_ops 243835265 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory -system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 977685992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977685992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 91606089 # Number of bytes written to this memory -system.physmem.bytes_written::total 91606089 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 244421498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 82220433 # Number of read requests responded to by this memory -system.physmem.num_reads::total 326641931 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 22901951 # Number of write requests responded to by this memory -system.physmem.num_writes::total 22901951 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 3886 # Number of other requests responded to by this memory -system.physmem.num_other::total 3886 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999667834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2689291768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10688959601 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999667834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 749543606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 749543606 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 244431648 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 243825150 # Number of instructions committed -system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses -system.cpu.num_func_calls 4252956 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls -system.cpu.num_int_insts 194726494 # number of integer instructions -system.cpu.num_fp_insts 11630 # number of float instructions -system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read -system.cpu.num_int_register_writes 215451554 # number of times the integer registers were written -system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read -system.cpu.num_fp_register_writes 90 # number of times the floating registers were written -system.cpu.num_mem_refs 105711441 # number of memory refs -system.cpu.num_load_insts 82803521 # Number of load instructions -system.cpu.num_store_insts 22907920 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 244431647.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29302884 # Number of branches fetched -system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction -system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction -system.cpu.op_class::MemRead 82803527 33.88% 90.63% # Class of executed instruction -system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 244431613 # Class of executed instruction -system.membus.trans_dist::ReadReq 326641931 # Transaction distribution -system.membus.trans_dist::ReadResp 326641931 # Transaction distribution -system.membus.trans_dist::WriteReq 22901951 # Transaction distribution -system.membus.trans_dist::WriteResp 22901951 # Transaction distribution -system.membus.trans_dist::SwapReq 3886 # Transaction distribution -system.membus.trans_dist::SwapResp 3886 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 488842996 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 210252540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 699095536 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 977685992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 420311185 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1397997177 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 349547768 # Request fanout histogram -system.membus.snoop_fanout::mean 0.699251 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.458584 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 105126270 30.07% 30.07% # Request fanout histogram -system.membus.snoop_fanout::1 244421498 69.93% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 349547768 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index 98c94dc36..e69de29bb 100644 --- a/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -1,127 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.168950 # Number of seconds simulated -sim_ticks 168950040000 # Number of ticks simulated -final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 537919 # Simulator instruction rate (inst/s) -host_op_rate 947189 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 575240737 # Simulator tick rate (ticks/s) -host_mem_usage 379572 # Number of bytes of host memory used -host_seconds 293.70 # Real time elapsed on the host -sim_insts 157988548 # Number of instructions simulated -sim_ops 278192465 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory -system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1741569312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1741569312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 243173117 # Number of bytes written to this memory -system.physmem.bytes_written::total 243173117 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 217696164 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 90779447 # Number of read requests responded to by this memory -system.physmem.num_reads::total 308475611 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 31439752 # Number of write requests responded to by this memory -system.physmem.num_writes::total 31439752 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10308191179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 4245314254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14553505433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10308191179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10308191179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1439319677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1439319677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 337900081 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 157988548 # Number of instructions committed -system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses -system.cpu.num_func_calls 8475189 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls -system.cpu.num_int_insts 278169482 # number of integer instructions -system.cpu.num_fp_insts 40 # number of float instructions -system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read -system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 40 # number of times the floating registers were read -system.cpu.num_fp_register_writes 26 # number of times the floating registers were written -system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read -system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written -system.cpu.num_mem_refs 122219137 # number of memory refs -system.cpu.num_load_insts 90779385 # Number of load instructions -system.cpu.num_store_insts 31439752 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 337900080.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 29309705 # Number of branches fetched -system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction -system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction -system.cpu.op_class::MemRead 90779385 32.63% 88.70% # Class of executed instruction -system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 278192465 # Class of executed instruction -system.membus.trans_dist::ReadReq 308475611 # Transaction distribution -system.membus.trans_dist::ReadResp 308475611 # Transaction distribution -system.membus.trans_dist::WriteReq 31439752 # Transaction distribution -system.membus.trans_dist::WriteResp 31439752 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 339915363 # Request fanout histogram -system.membus.snoop_fanout::mean 0.640442 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 122219199 35.96% 35.96% # Request fanout histogram -system.membus.snoop_fanout::1 217696164 64.04% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 339915363 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt index 850ec8600..e69de29bb 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt @@ -1,152 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000250 # Number of seconds simulated -sim_ticks 250015500 # Number of ticks simulated -final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1181428 # Simulator instruction rate (inst/s) -host_op_rate 1181354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 590676886 # Simulator tick rate (ticks/s) -host_mem_usage 220296 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host -sim_insts 500001 # Number of instructions simulated -sim_ops 500001 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 2000076 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 872600 # Number of bytes read from this memory -system.physmem.bytes_read::total 2872676 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2000076 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2000076 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 417562 # Number of bytes written to this memory -system.physmem.bytes_written::total 417562 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 500019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124435 # Number of read requests responded to by this memory -system.physmem.num_reads::total 624454 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 56340 # Number of write requests responded to by this memory -system.physmem.num_writes::total 56340 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999808012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3490183609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11489991621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999808012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999808012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1670144451 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1670144451 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999808012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5160328060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13160136072 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 124435 # DTB read hits -system.cpu.dtb.read_misses 8 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 124443 # DTB read accesses -system.cpu.dtb.write_hits 56340 # DTB write hits -system.cpu.dtb.write_misses 10 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 56350 # DTB write accesses -system.cpu.dtb.data_hits 180775 # DTB hits -system.cpu.dtb.data_misses 18 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 180793 # DTB accesses -system.cpu.itb.fetch_hits 500019 # ITB hits -system.cpu.itb.fetch_misses 13 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 500032 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 500032 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 500001 # Number of instructions committed -system.cpu.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu.num_func_calls 14357 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu.num_int_insts 474689 # number of integer instructions -system.cpu.num_fp_insts 32 # number of float instructions -system.cpu.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 180793 # number of memory refs -system.cpu.num_load_insts 124443 # Number of load instructions -system.cpu.num_store_insts 56350 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 500032 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 59023 # Number of branches fetched -system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 500019 # Class of executed instruction -system.membus.trans_dist::ReadReq 624454 # Transaction distribution -system.membus.trans_dist::ReadResp 624454 # Transaction distribution -system.membus.trans_dist::WriteReq 56340 # Transaction distribution -system.membus.trans_dist::WriteResp 56340 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1000038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 361550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1361588 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2000076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1290162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 3290238 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 680794 # Request fanout histogram -system.membus.snoop_fanout::mean 0.734464 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.441618 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 180775 26.55% 26.55% # Request fanout histogram -system.membus.snoop_fanout::1 500019 73.45% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 680794 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt index 45ece38cc..e69de29bb 100644 --- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt +++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt @@ -1,497 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000733 # Number of seconds simulated -sim_ticks 733071500 # Number of ticks simulated -final_tick 733071500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 558953 # Simulator instruction rate (inst/s) -host_op_rate 558933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 819448941 # Simulator tick rate (ticks/s) -host_mem_usage 229836 # Number of bytes of host memory used -host_seconds 0.89 # Real time elapsed on the host -sim_insts 500001 # Number of instructions simulated -sim_ops 500001 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::total 54848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 25792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 857 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 35183471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39635970 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 74819441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 35183471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 35183471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 35183471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39635970 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 74819441 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 124435 # DTB read hits -system.cpu.dtb.read_misses 8 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 124443 # DTB read accesses -system.cpu.dtb.write_hits 56340 # DTB write hits -system.cpu.dtb.write_misses 10 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 56350 # DTB write accesses -system.cpu.dtb.data_hits 180775 # DTB hits -system.cpu.dtb.data_misses 18 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 180793 # DTB accesses -system.cpu.itb.fetch_hits 500020 # ITB hits -system.cpu.itb.fetch_misses 13 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 500033 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 1466143 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 500001 # Number of instructions committed -system.cpu.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu.num_func_calls 14357 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu.num_int_insts 474689 # number of integer instructions -system.cpu.num_fp_insts 32 # number of float instructions -system.cpu.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu.num_mem_refs 180793 # number of memory refs -system.cpu.num_load_insts 124443 # Number of load instructions -system.cpu.num_store_insts 56350 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1466143 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 59023 # Number of branches fetched -system.cpu.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 500019 # Class of executed instruction -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 286.668758 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 180321 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 454 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 397.182819 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 286.668758 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.069987 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.069987 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 454 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 426 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.110840 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 362004 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 362004 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 124120 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 180321 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 180321 # number of overall hits -system.cpu.dcache.overall_hits::total 180321 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 315 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 454 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 454 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 454 # number of overall misses -system.cpu.dcache.overall_misses::total 454 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19530000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19530000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8618000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8618000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28148000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28148000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28148000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28148000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002531 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002531 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002467 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002511 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002511 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002511 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002511 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 315 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 139 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 454 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 454 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 454 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19215000 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62001.240695 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62001.240695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62001.240695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62001.240695 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 403 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61001.240695 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61001.240695 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 480.680597 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 718 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 264.590924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 216.089673 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008075 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006595 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.240695 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.240695 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.240695 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.583431 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 857 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 403 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 315 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 806 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 25792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 857 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 857 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 428500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 604500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 681000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 718 # Transaction distribution -system.membus.trans_dist::ReadExReq 139 # Transaction distribution -system.membus.trans_dist::ReadExResp 139 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 718 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1714 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 54848 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 857 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 857 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 857 # Request fanout histogram -system.membus.reqLayer0.occupancy 857500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 4285000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt index f03bf3dc9..e69de29bb 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt @@ -1,1082 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000250 # Number of seconds simulated -sim_ticks 250015500 # Number of ticks simulated -final_tick 250015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1254205 # Simulator instruction rate (inst/s) -host_op_rate 1254187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 156780790 # Simulator tick rate (ticks/s) -host_mem_usage 242604 # Number of bytes of host memory used -host_seconds 1.59 # Real time elapsed on the host -sim_insts 2000004 # Number of instructions simulated -sim_ops 2000004 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::total 219392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 103161604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 116216795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 103161604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 116216795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 103161604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 116216795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 103161604 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 116216795 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877513594 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 103161604 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 412646416 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 103161604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 116216795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 103161604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 116216795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 103161604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 116216795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 103161604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 116216795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877513594 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 124435 # DTB read hits -system.cpu0.dtb.read_misses 8 # DTB read misses -system.cpu0.dtb.read_acv 0 # DTB read access violations -system.cpu0.dtb.read_accesses 124443 # DTB read accesses -system.cpu0.dtb.write_hits 56340 # DTB write hits -system.cpu0.dtb.write_misses 10 # DTB write misses -system.cpu0.dtb.write_acv 0 # DTB write access violations -system.cpu0.dtb.write_accesses 56350 # DTB write accesses -system.cpu0.dtb.data_hits 180775 # DTB hits -system.cpu0.dtb.data_misses 18 # DTB misses -system.cpu0.dtb.data_acv 0 # DTB access violations -system.cpu0.dtb.data_accesses 180793 # DTB accesses -system.cpu0.itb.fetch_hits 500019 # ITB hits -system.cpu0.itb.fetch_misses 13 # ITB misses -system.cpu0.itb.fetch_acv 0 # ITB acv -system.cpu0.itb.fetch_accesses 500032 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.workload.num_syscalls 18 # Number of system calls -system.cpu0.numCycles 500032 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 500001 # Number of instructions committed -system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu0.num_func_calls 14357 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu0.num_int_insts 474689 # number of integer instructions -system.cpu0.num_fp_insts 32 # number of float instructions -system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu0.num_mem_refs 180793 # number of memory refs -system.cpu0.num_load_insts 124443 # Number of load instructions -system.cpu0.num_store_insts 56350 # Number of store instructions -system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 500032 # Number of busy cycles -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.Branches 59023 # Number of branches fetched -system.cpu0.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu0.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu0.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 500019 # Class of executed instruction -system.cpu0.dcache.tags.replacements 61 # number of replacements -system.cpu0.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 276.872320 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.540766 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits -system.cpu0.dcache.overall_hits::total 180312 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses -system.cpu0.dcache.overall_misses::total 463 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu0.dcache.writebacks::total 29 # number of writebacks -system.cpu0.icache.tags.replacements 152 # number of replacements -system.cpu0.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 218.086151 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.425950 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 500482 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 500482 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 499556 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 499556 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 499556 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 499556 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 499556 # number of overall hits -system.cpu0.icache.overall_hits::total 499556 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses -system.cpu0.icache.overall_misses::total 463 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 500019 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 500019 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 500019 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 500019 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 500019 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 152 # number of writebacks -system.cpu0.icache.writebacks::total 152 # number of writebacks -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 124435 # DTB read hits -system.cpu1.dtb.read_misses 8 # DTB read misses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 124443 # DTB read accesses -system.cpu1.dtb.write_hits 56340 # DTB write hits -system.cpu1.dtb.write_misses 10 # DTB write misses -system.cpu1.dtb.write_acv 0 # DTB write access violations -system.cpu1.dtb.write_accesses 56350 # DTB write accesses -system.cpu1.dtb.data_hits 180775 # DTB hits -system.cpu1.dtb.data_misses 18 # DTB misses -system.cpu1.dtb.data_acv 0 # DTB access violations -system.cpu1.dtb.data_accesses 180793 # DTB accesses -system.cpu1.itb.fetch_hits 500019 # ITB hits -system.cpu1.itb.fetch_misses 13 # ITB misses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 500032 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.workload.num_syscalls 18 # Number of system calls -system.cpu1.numCycles 500032 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 500001 # Number of instructions committed -system.cpu1.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu1.num_func_calls 14357 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu1.num_int_insts 474689 # number of integer instructions -system.cpu1.num_fp_insts 32 # number of float instructions -system.cpu1.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu1.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu1.num_mem_refs 180793 # number of memory refs -system.cpu1.num_load_insts 124443 # Number of load instructions -system.cpu1.num_store_insts 56350 # Number of store instructions -system.cpu1.num_idle_cycles 0 # Number of idle cycles -system.cpu1.num_busy_cycles 500032 # Number of busy cycles -system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.Branches 59023 # Number of branches fetched -system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu1.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu1.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 500019 # Class of executed instruction -system.cpu1.dcache.tags.replacements 61 # number of replacements -system.cpu1.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 276.872320 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.540766 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 723563 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 723563 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 56201 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu1.dcache.demand_hits::cpu1.data 180312 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 180312 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 180312 # number of overall hits -system.cpu1.dcache.overall_hits::total 180312 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses -system.cpu1.dcache.overall_misses::total 463 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 180775 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 180775 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu1.dcache.writebacks::total 29 # number of writebacks -system.cpu1.icache.tags.replacements 152 # number of replacements -system.cpu1.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 218.086151 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.425950 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 500482 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 500482 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 499556 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 499556 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 499556 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 499556 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 499556 # number of overall hits -system.cpu1.icache.overall_hits::total 499556 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses -system.cpu1.icache.overall_misses::total 463 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 500019 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 500019 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 500019 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 500019 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 500019 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 152 # number of writebacks -system.cpu1.icache.writebacks::total 152 # number of writebacks -system.cpu2.dtb.fetch_hits 0 # ITB hits -system.cpu2.dtb.fetch_misses 0 # ITB misses -system.cpu2.dtb.fetch_acv 0 # ITB acv -system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 124435 # DTB read hits -system.cpu2.dtb.read_misses 8 # DTB read misses -system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_accesses 124443 # DTB read accesses -system.cpu2.dtb.write_hits 56340 # DTB write hits -system.cpu2.dtb.write_misses 10 # DTB write misses -system.cpu2.dtb.write_acv 0 # DTB write access violations -system.cpu2.dtb.write_accesses 56350 # DTB write accesses -system.cpu2.dtb.data_hits 180775 # DTB hits -system.cpu2.dtb.data_misses 18 # DTB misses -system.cpu2.dtb.data_acv 0 # DTB access violations -system.cpu2.dtb.data_accesses 180793 # DTB accesses -system.cpu2.itb.fetch_hits 500019 # ITB hits -system.cpu2.itb.fetch_misses 13 # ITB misses -system.cpu2.itb.fetch_acv 0 # ITB acv -system.cpu2.itb.fetch_accesses 500032 # ITB accesses -system.cpu2.itb.read_hits 0 # DTB read hits -system.cpu2.itb.read_misses 0 # DTB read misses -system.cpu2.itb.read_acv 0 # DTB read access violations -system.cpu2.itb.read_accesses 0 # DTB read accesses -system.cpu2.itb.write_hits 0 # DTB write hits -system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.write_acv 0 # DTB write access violations -system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.data_hits 0 # DTB hits -system.cpu2.itb.data_misses 0 # DTB misses -system.cpu2.itb.data_acv 0 # DTB access violations -system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.workload.num_syscalls 18 # Number of system calls -system.cpu2.numCycles 500032 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 500001 # Number of instructions committed -system.cpu2.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu2.num_func_calls 14357 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu2.num_int_insts 474689 # number of integer instructions -system.cpu2.num_fp_insts 32 # number of float instructions -system.cpu2.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu2.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu2.num_mem_refs 180793 # number of memory refs -system.cpu2.num_load_insts 124443 # Number of load instructions -system.cpu2.num_store_insts 56350 # Number of store instructions -system.cpu2.num_idle_cycles 0 # Number of idle cycles -system.cpu2.num_busy_cycles 500032 # Number of busy cycles -system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.Branches 59023 # Number of branches fetched -system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu2.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu2.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 500019 # Class of executed instruction -system.cpu2.dcache.tags.replacements 61 # number of replacements -system.cpu2.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 276.872320 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.540766 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 723563 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 723563 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 56201 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu2.dcache.demand_hits::cpu2.data 180312 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 180312 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 180312 # number of overall hits -system.cpu2.dcache.overall_hits::total 180312 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses -system.cpu2.dcache.overall_misses::total 463 # number of overall misses -system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 180775 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 180775 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu2.dcache.writebacks::total 29 # number of writebacks -system.cpu2.icache.tags.replacements 152 # number of replacements -system.cpu2.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 218.086151 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.425950 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 500482 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 500482 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 499556 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 499556 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 499556 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 499556 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 499556 # number of overall hits -system.cpu2.icache.overall_hits::total 499556 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses -system.cpu2.icache.overall_misses::total 463 # number of overall misses -system.cpu2.icache.ReadReq_accesses::cpu2.inst 500019 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 500019 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 500019 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 500019 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 500019 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 152 # number of writebacks -system.cpu2.icache.writebacks::total 152 # number of writebacks -system.cpu3.dtb.fetch_hits 0 # ITB hits -system.cpu3.dtb.fetch_misses 0 # ITB misses -system.cpu3.dtb.fetch_acv 0 # ITB acv -system.cpu3.dtb.fetch_accesses 0 # ITB accesses -system.cpu3.dtb.read_hits 124435 # DTB read hits -system.cpu3.dtb.read_misses 8 # DTB read misses -system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_accesses 124443 # DTB read accesses -system.cpu3.dtb.write_hits 56340 # DTB write hits -system.cpu3.dtb.write_misses 10 # DTB write misses -system.cpu3.dtb.write_acv 0 # DTB write access violations -system.cpu3.dtb.write_accesses 56350 # DTB write accesses -system.cpu3.dtb.data_hits 180775 # DTB hits -system.cpu3.dtb.data_misses 18 # DTB misses -system.cpu3.dtb.data_acv 0 # DTB access violations -system.cpu3.dtb.data_accesses 180793 # DTB accesses -system.cpu3.itb.fetch_hits 500019 # ITB hits -system.cpu3.itb.fetch_misses 13 # ITB misses -system.cpu3.itb.fetch_acv 0 # ITB acv -system.cpu3.itb.fetch_accesses 500032 # ITB accesses -system.cpu3.itb.read_hits 0 # DTB read hits -system.cpu3.itb.read_misses 0 # DTB read misses -system.cpu3.itb.read_acv 0 # DTB read access violations -system.cpu3.itb.read_accesses 0 # DTB read accesses -system.cpu3.itb.write_hits 0 # DTB write hits -system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.write_acv 0 # DTB write access violations -system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.data_hits 0 # DTB hits -system.cpu3.itb.data_misses 0 # DTB misses -system.cpu3.itb.data_acv 0 # DTB access violations -system.cpu3.itb.data_accesses 0 # DTB accesses -system.cpu3.workload.num_syscalls 18 # Number of system calls -system.cpu3.numCycles 500032 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 500001 # Number of instructions committed -system.cpu3.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu3.num_func_calls 14357 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu3.num_int_insts 474689 # number of integer instructions -system.cpu3.num_fp_insts 32 # number of float instructions -system.cpu3.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu3.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu3.num_mem_refs 180793 # number of memory refs -system.cpu3.num_load_insts 124443 # Number of load instructions -system.cpu3.num_store_insts 56350 # Number of store instructions -system.cpu3.num_idle_cycles 0 # Number of idle cycles -system.cpu3.num_busy_cycles 500032 # Number of busy cycles -system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.Branches 59023 # Number of branches fetched -system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu3.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu3.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 500019 # Class of executed instruction -system.cpu3.dcache.tags.replacements 61 # number of replacements -system.cpu3.dcache.tags.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 276.872320 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.540766 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.540766 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 723563 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 723563 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 124111 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 56201 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu3.dcache.demand_hits::cpu3.data 180312 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 180312 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 180312 # number of overall hits -system.cpu3.dcache.overall_hits::total 180312 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses -system.cpu3.dcache.overall_misses::total 463 # number of overall misses -system.cpu3.dcache.ReadReq_accesses::cpu3.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 180775 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 180775 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu3.dcache.writebacks::total 29 # number of writebacks -system.cpu3.icache.tags.replacements 152 # number of replacements -system.cpu3.icache.tags.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 499556 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 218.086151 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.425950 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.425950 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 500482 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 500482 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 499556 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 499556 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 499556 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 499556 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 499556 # number of overall hits -system.cpu3.icache.overall_hits::total 499556 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 463 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 463 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 463 # number of overall misses -system.cpu3.icache.overall_misses::total 463 # number of overall misses -system.cpu3.icache.ReadReq_accesses::cpu3.inst 500019 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 500019 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 500019 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 500019 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 500019 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 500019 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000926 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000926 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000926 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 152 # number of writebacks -system.cpu3.icache.writebacks::total 152 # number of writebacks -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 1962.780232 # Cycle average of tags in use -system.l2c.tags.total_refs 1068 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 0.364256 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 17.466765 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 267.152061 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 219.176305 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000267 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.004076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.003344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.029950 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1088 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1836 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 39936 # Number of tag accesses -system.l2c.tags.data_accesses 39936 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 608 # number of WritebackClean hits -system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 36 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 60 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 276 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 60 # number of overall hits -system.l2c.overall_hits::cpu0.data 9 # number of overall hits -system.l2c.overall_hits::cpu1.inst 60 # number of overall hits -system.l2c.overall_hits::cpu1.data 9 # number of overall hits -system.l2c.overall_hits::cpu2.inst 60 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 60 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.ReadExReq_misses::cpu0.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 403 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 403 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 403 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 403 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 1612 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 315 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 315 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 315 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 315 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 1260 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 454 # number of demand (read+write) misses -system.l2c.demand_misses::total 3428 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 403 # number of overall misses -system.l2c.overall_misses::cpu0.data 454 # number of overall misses -system.l2c.overall_misses::cpu1.inst 403 # number of overall misses -system.l2c.overall_misses::cpu1.data 454 # number of overall misses -system.l2c.overall_misses::cpu2.inst 403 # number of overall misses -system.l2c.overall_misses::cpu2.data 454 # number of overall misses -system.l2c.overall_misses::cpu3.inst 403 # number of overall misses -system.l2c.overall_misses::cpu3.data 454 # number of overall misses -system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 116 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 116 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 608 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 608 # number of WritebackClean accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 463 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 463 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 463 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu3.inst 463 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1852 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 324 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 324 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 324 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 324 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1296 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 463 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 463 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.870410 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.870410 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.870410 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.870410 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.870410 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.972222 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.972222 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.972222 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.972222 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.972222 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.870410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.980562 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.925486 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.870410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.980562 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.925486 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.membus.trans_dist::ReadResp 2872 # Transaction distribution -system.membus.trans_dist::ReadExReq 556 # Transaction distribution -system.membus.trans_dist::ReadExResp 556 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3428 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3428 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3428 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 4556 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 852 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 128 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 283392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4556 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4556 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4556 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt index e6bd082aa..e69de29bb 100644 --- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt +++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt @@ -1,1634 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000734 # Number of seconds simulated -sim_ticks 733914500 # Number of ticks simulated -final_tick 733914500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 598517 # Simulator instruction rate (inst/s) -host_op_rate 598513 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 219630055 # Simulator tick rate (ticks/s) -host_mem_usage 242608 # Number of bytes of host memory used -host_seconds 3.34 # Real time elapsed on the host -sim_insts 1999973 # Number of instructions simulated -sim_ops 1999973 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 25792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 29056 # Number of bytes read from this memory -system.physmem.bytes_read::total 219392 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 25792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 103168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 35143058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39590443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35143058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 39590443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 35143058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 39590443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 35143058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 39590443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 298934004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 35143058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35143058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 35143058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 35143058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 140572233 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 35143058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39590443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35143058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 39590443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 35143058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 39590443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 35143058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 39590443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 298934004 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 124435 # DTB read hits -system.cpu0.dtb.read_misses 8 # DTB read misses -system.cpu0.dtb.read_acv 0 # DTB read access violations -system.cpu0.dtb.read_accesses 124443 # DTB read accesses -system.cpu0.dtb.write_hits 56340 # DTB write hits -system.cpu0.dtb.write_misses 10 # DTB write misses -system.cpu0.dtb.write_acv 0 # DTB write access violations -system.cpu0.dtb.write_accesses 56350 # DTB write accesses -system.cpu0.dtb.data_hits 180775 # DTB hits -system.cpu0.dtb.data_misses 18 # DTB misses -system.cpu0.dtb.data_acv 0 # DTB access violations -system.cpu0.dtb.data_accesses 180793 # DTB accesses -system.cpu0.itb.fetch_hits 500020 # ITB hits -system.cpu0.itb.fetch_misses 13 # ITB misses -system.cpu0.itb.fetch_acv 0 # ITB acv -system.cpu0.itb.fetch_accesses 500033 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.workload.num_syscalls 18 # Number of system calls -system.cpu0.numCycles 1467829 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 500001 # Number of instructions committed -system.cpu0.committedOps 500001 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 474689 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu0.num_func_calls 14357 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 38180 # number of instructions that are conditional controls -system.cpu0.num_int_insts 474689 # number of integer instructions -system.cpu0.num_fp_insts 32 # number of float instructions -system.cpu0.num_int_register_reads 654286 # number of times the integer registers were read -system.cpu0.num_int_register_writes 371542 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu0.num_mem_refs 180793 # number of memory refs -system.cpu0.num_load_insts 124443 # Number of load instructions -system.cpu0.num_store_insts 56350 # Number of store instructions -system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 1467829 # Number of busy cycles -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.Branches 59023 # Number of branches fetched -system.cpu0.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu0.op_class::IntAlu 300388 60.08% 63.84% # Class of executed instruction -system.cpu0.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu0.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 56350 11.27% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 500019 # Class of executed instruction -system.cpu0.dcache.tags.replacements 61 # number of replacements -system.cpu0.dcache.tags.tagsinuse 273.068294 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 273.068294 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.533337 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.533337 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 723563 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 723563 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 56201 # number of WriteReq hits -system.cpu0.dcache.demand_hits::cpu0.data 180312 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 180312 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 180312 # number of overall hits -system.cpu0.dcache.overall_hits::total 180312 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 324 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 139 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu0.dcache.demand_misses::cpu0.data 463 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 463 # number of overall misses -system.cpu0.dcache.overall_misses::total 463 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19649000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8621000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 28270000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28270000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 28270000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28270000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 180775 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 180775 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 180775 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 180775 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.002467 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.002561 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 60645.061728 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62021.582734 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 61058.315335 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 61058.315335 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 61058.315335 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 61058.315335 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu0.dcache.writebacks::total 29 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 324 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 139 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 463 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 463 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 19325000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 19325000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8482000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8482000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27807000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 27807000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 27807000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 27807000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 59645.061728 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 61021.582734 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734 # average WriteReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 60058.315335 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 60058.315335 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency -system.cpu0.icache.tags.replacements 152 # number of replacements -system.cpu0.icache.tags.tagsinuse 216.116668 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 499557 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 1078.956803 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 216.116668 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.422103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.422103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 500483 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 500483 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 499557 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 499557 # number of overall hits -system.cpu0.icache.overall_hits::total 499557 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 463 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 463 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses -system.cpu0.icache.overall_misses::total 463 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25776500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 25776500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 25776500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 25776500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 25776500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 25776500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 500020 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 500020 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 500020 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000926 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 55672.786177 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 55672.786177 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 55672.786177 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 55672.786177 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 55672.786177 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 55672.786177 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 152 # number of writebacks -system.cpu0.icache.writebacks::total 152 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 463 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 463 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 25313500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 25313500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 25313500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 25313500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 25313500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 25313500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 54672.786177 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 54672.786177 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 54672.786177 # average overall mshr miss latency -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 124435 # DTB read hits -system.cpu1.dtb.read_misses 8 # DTB read misses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 124443 # DTB read accesses -system.cpu1.dtb.write_hits 56339 # DTB write hits -system.cpu1.dtb.write_misses 10 # DTB write misses -system.cpu1.dtb.write_acv 0 # DTB write access violations -system.cpu1.dtb.write_accesses 56349 # DTB write accesses -system.cpu1.dtb.data_hits 180774 # DTB hits -system.cpu1.dtb.data_misses 18 # DTB misses -system.cpu1.dtb.data_acv 0 # DTB access violations -system.cpu1.dtb.data_accesses 180792 # DTB accesses -system.cpu1.itb.fetch_hits 500014 # ITB hits -system.cpu1.itb.fetch_misses 13 # ITB misses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 500027 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.workload.num_syscalls 18 # Number of system calls -system.cpu1.numCycles 1467829 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 499995 # Number of instructions committed -system.cpu1.committedOps 499995 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 474683 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu1.num_func_calls 14357 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 38179 # number of instructions that are conditional controls -system.cpu1.num_int_insts 474683 # number of integer instructions -system.cpu1.num_fp_insts 32 # number of float instructions -system.cpu1.num_int_register_reads 654276 # number of times the integer registers were read -system.cpu1.num_int_register_writes 371538 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu1.num_mem_refs 180792 # number of memory refs -system.cpu1.num_load_insts 124443 # Number of load instructions -system.cpu1.num_store_insts 56349 # Number of store instructions -system.cpu1.num_idle_cycles 0 # Number of idle cycles -system.cpu1.num_busy_cycles 1467829 # Number of busy cycles -system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.Branches 59022 # Number of branches fetched -system.cpu1.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu1.op_class::IntAlu 300383 60.08% 63.84% # Class of executed instruction -system.cpu1.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu1.op_class::MemRead 124443 24.89% 88.73% # Class of executed instruction -system.cpu1.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 500013 # Class of executed instruction -system.cpu1.dcache.tags.replacements 61 # number of replacements -system.cpu1.dcache.tags.tagsinuse 273.065457 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 180311 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 273.065457 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.533331 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.533331 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 723559 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 723559 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 124111 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 56200 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 56200 # number of WriteReq hits -system.cpu1.dcache.demand_hits::cpu1.data 180311 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 180311 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 180311 # number of overall hits -system.cpu1.dcache.overall_hits::total 180311 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 324 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 139 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu1.dcache.demand_misses::cpu1.data 463 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 463 # number of overall misses -system.cpu1.dcache.overall_misses::total 463 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 19649000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8621500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8621500 # number of WriteReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 28270500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 28270500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 28270500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 28270500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 56339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 180774 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 180774 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002467 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002561 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002561 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 60645.061728 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 62025.179856 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 62025.179856 # average WriteReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 61059.395248 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 61059.395248 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 61059.395248 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 61059.395248 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu1.dcache.writebacks::total 29 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 324 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 139 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 463 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 463 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 19325000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 19325000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 8482500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 8482500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 27807500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 27807500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 27807500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 27807500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002467 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002561 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 59645.061728 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61025.179856 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 61025.179856 # average WriteReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 60059.395248 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 60059.395248 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 60059.395248 # average overall mshr miss latency -system.cpu1.icache.tags.replacements 152 # number of replacements -system.cpu1.icache.tags.tagsinuse 216.114546 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 499551 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 1078.943844 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 216.114546 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.422099 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.422099 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 500477 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 500477 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 499551 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 499551 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 499551 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 499551 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 499551 # number of overall hits -system.cpu1.icache.overall_hits::total 499551 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463 # number of overall misses -system.cpu1.icache.overall_misses::total 463 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 25783000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 25783000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 25783000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 25783000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 25783000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 25783000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 500014 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 500014 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 500014 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 500014 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 500014 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 500014 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.000926 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.000926 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 55686.825054 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 55686.825054 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 55686.825054 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 55686.825054 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 55686.825054 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 55686.825054 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 152 # number of writebacks -system.cpu1.icache.writebacks::total 152 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 463 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 463 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 25320000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 25320000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 25320000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 25320000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 25320000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 25320000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.000926 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 54686.825054 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 54686.825054 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 54686.825054 # average overall mshr miss latency -system.cpu2.dtb.fetch_hits 0 # ITB hits -system.cpu2.dtb.fetch_misses 0 # ITB misses -system.cpu2.dtb.fetch_acv 0 # ITB acv -system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 124435 # DTB read hits -system.cpu2.dtb.read_misses 8 # DTB read misses -system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_accesses 124443 # DTB read accesses -system.cpu2.dtb.write_hits 56339 # DTB write hits -system.cpu2.dtb.write_misses 10 # DTB write misses -system.cpu2.dtb.write_acv 0 # DTB write access violations -system.cpu2.dtb.write_accesses 56349 # DTB write accesses -system.cpu2.dtb.data_hits 180774 # DTB hits -system.cpu2.dtb.data_misses 18 # DTB misses -system.cpu2.dtb.data_acv 0 # DTB access violations -system.cpu2.dtb.data_accesses 180792 # DTB accesses -system.cpu2.itb.fetch_hits 500009 # ITB hits -system.cpu2.itb.fetch_misses 13 # ITB misses -system.cpu2.itb.fetch_acv 0 # ITB acv -system.cpu2.itb.fetch_accesses 500022 # ITB accesses -system.cpu2.itb.read_hits 0 # DTB read hits -system.cpu2.itb.read_misses 0 # DTB read misses -system.cpu2.itb.read_acv 0 # DTB read access violations -system.cpu2.itb.read_accesses 0 # DTB read accesses -system.cpu2.itb.write_hits 0 # DTB write hits -system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.write_acv 0 # DTB write access violations -system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.data_hits 0 # DTB hits -system.cpu2.itb.data_misses 0 # DTB misses -system.cpu2.itb.data_acv 0 # DTB access violations -system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.workload.num_syscalls 18 # Number of system calls -system.cpu2.numCycles 1467829 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 499990 # Number of instructions committed -system.cpu2.committedOps 499990 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 474678 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu2.num_func_calls 14357 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 38179 # number of instructions that are conditional controls -system.cpu2.num_int_insts 474678 # number of integer instructions -system.cpu2.num_fp_insts 32 # number of float instructions -system.cpu2.num_int_register_reads 654270 # number of times the integer registers were read -system.cpu2.num_int_register_writes 371533 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu2.num_mem_refs 180791 # number of memory refs -system.cpu2.num_load_insts 124442 # Number of load instructions -system.cpu2.num_store_insts 56349 # Number of store instructions -system.cpu2.num_idle_cycles 0 # Number of idle cycles -system.cpu2.num_busy_cycles 1467829 # Number of busy cycles -system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.Branches 59022 # Number of branches fetched -system.cpu2.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu2.op_class::IntAlu 300379 60.07% 63.84% # Class of executed instruction -system.cpu2.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu2.op_class::MemRead 124442 24.89% 88.73% # Class of executed instruction -system.cpu2.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 500008 # Class of executed instruction -system.cpu2.dcache.tags.replacements 61 # number of replacements -system.cpu2.dcache.tags.tagsinuse 273.062707 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 180311 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 389.440605 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 273.062707 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.533326 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.533326 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 723559 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 723559 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 124111 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 124111 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 56200 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 56200 # number of WriteReq hits -system.cpu2.dcache.demand_hits::cpu2.data 180311 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 180311 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 180311 # number of overall hits -system.cpu2.dcache.overall_hits::total 180311 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 324 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 139 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu2.dcache.demand_misses::cpu2.data 463 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 463 # number of overall misses -system.cpu2.dcache.overall_misses::total 463 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 19649000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 19649000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 8621000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 28270000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 28270000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 28270000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 28270000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 56339 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 180774 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 180774 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 180774 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 180774 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.002467 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.002561 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.002561 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 60645.061728 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 60645.061728 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 62021.582734 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 61058.315335 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 61058.315335 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 61058.315335 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 61058.315335 # average overall miss latency -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.writebacks::writebacks 29 # number of writebacks -system.cpu2.dcache.writebacks::total 29 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 324 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 324 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 139 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 139 # number of WriteReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 463 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 463 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 19325000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 19325000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 8482000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 8482000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 27807000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 27807000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 27807000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 27807000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002467 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002467 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.002561 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 59645.061728 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 59645.061728 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 61021.582734 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 61021.582734 # average WriteReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 60058.315335 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 60058.315335 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 60058.315335 # average overall mshr miss latency -system.cpu2.icache.tags.replacements 152 # number of replacements -system.cpu2.icache.tags.tagsinuse 216.112416 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 499546 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 1078.933045 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 216.112416 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.422095 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.422095 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 311 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 500472 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 500472 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 499546 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 499546 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 499546 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 499546 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 499546 # number of overall hits -system.cpu2.icache.overall_hits::total 499546 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 463 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 463 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 463 # number of overall misses -system.cpu2.icache.overall_misses::total 463 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 25788500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 25788500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 25788500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 25788500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 25788500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 25788500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 500009 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 500009 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 500009 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 500009 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 500009 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 500009 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000926 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000926 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 55698.704104 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 55698.704104 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 55698.704104 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 55698.704104 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 55698.704104 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 55698.704104 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 152 # number of writebacks -system.cpu2.icache.writebacks::total 152 # number of writebacks -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 463 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 463 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 463 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 463 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 463 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 25325500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 25325500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 25325500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 25325500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 25325500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 25325500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.000926 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 54698.704104 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 54698.704104 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 54698.704104 # average overall mshr miss latency -system.cpu3.dtb.fetch_hits 0 # ITB hits -system.cpu3.dtb.fetch_misses 0 # ITB misses -system.cpu3.dtb.fetch_acv 0 # ITB acv -system.cpu3.dtb.fetch_accesses 0 # ITB accesses -system.cpu3.dtb.read_hits 124433 # DTB read hits -system.cpu3.dtb.read_misses 8 # DTB read misses -system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_accesses 124441 # DTB read accesses -system.cpu3.dtb.write_hits 56339 # DTB write hits -system.cpu3.dtb.write_misses 10 # DTB write misses -system.cpu3.dtb.write_acv 0 # DTB write access violations -system.cpu3.dtb.write_accesses 56349 # DTB write accesses -system.cpu3.dtb.data_hits 180772 # DTB hits -system.cpu3.dtb.data_misses 18 # DTB misses -system.cpu3.dtb.data_acv 0 # DTB access violations -system.cpu3.dtb.data_accesses 180790 # DTB accesses -system.cpu3.itb.fetch_hits 500006 # ITB hits -system.cpu3.itb.fetch_misses 13 # ITB misses -system.cpu3.itb.fetch_acv 0 # ITB acv -system.cpu3.itb.fetch_accesses 500019 # ITB accesses -system.cpu3.itb.read_hits 0 # DTB read hits -system.cpu3.itb.read_misses 0 # DTB read misses -system.cpu3.itb.read_acv 0 # DTB read access violations -system.cpu3.itb.read_accesses 0 # DTB read accesses -system.cpu3.itb.write_hits 0 # DTB write hits -system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.write_acv 0 # DTB write access violations -system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.data_hits 0 # DTB hits -system.cpu3.itb.data_misses 0 # DTB misses -system.cpu3.itb.data_acv 0 # DTB access violations -system.cpu3.itb.data_accesses 0 # DTB accesses -system.cpu3.workload.num_syscalls 18 # Number of system calls -system.cpu3.numCycles 1467829 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 499987 # Number of instructions committed -system.cpu3.committedOps 499987 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 474675 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 32 # Number of float alu accesses -system.cpu3.num_func_calls 14357 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 38179 # number of instructions that are conditional controls -system.cpu3.num_int_insts 474675 # number of integer instructions -system.cpu3.num_fp_insts 32 # number of float instructions -system.cpu3.num_int_register_reads 654265 # number of times the integer registers were read -system.cpu3.num_int_register_writes 371530 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written -system.cpu3.num_mem_refs 180790 # number of memory refs -system.cpu3.num_load_insts 124441 # Number of load instructions -system.cpu3.num_store_insts 56349 # Number of store instructions -system.cpu3.num_idle_cycles 0 # Number of idle cycles -system.cpu3.num_busy_cycles 1467829 # Number of busy cycles -system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.Branches 59022 # Number of branches fetched -system.cpu3.op_class::No_OpClass 18814 3.76% 3.76% # Class of executed instruction -system.cpu3.op_class::IntAlu 300377 60.07% 63.84% # Class of executed instruction -system.cpu3.op_class::IntMult 10 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatAdd 10 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatCmp 2 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatMult 2 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction -system.cpu3.op_class::MemRead 124441 24.89% 88.73% # Class of executed instruction -system.cpu3.op_class::MemWrite 56349 11.27% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 500005 # Class of executed instruction -system.cpu3.dcache.tags.replacements 61 # number of replacements -system.cpu3.dcache.tags.tagsinuse 273.059955 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 180309 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 389.436285 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 273.059955 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.533320 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.533320 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 367 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 723551 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 723551 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 124109 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 124109 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 56200 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 56200 # number of WriteReq hits -system.cpu3.dcache.demand_hits::cpu3.data 180309 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 180309 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 180309 # number of overall hits -system.cpu3.dcache.overall_hits::total 180309 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 324 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 324 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses -system.cpu3.dcache.demand_misses::cpu3.data 463 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 463 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 463 # number of overall misses -system.cpu3.dcache.overall_misses::total 463 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 19649500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 19649500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 8621000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 8621000 # number of WriteReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 28270500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 28270500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 28270500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 28270500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 124433 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 124433 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 56339 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 56339 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 180772 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 180772 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 180772 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 180772 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.002467 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.002467 # miss rate for WriteReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.002561 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.002561 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 60646.604938 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 60646.604938 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 62021.582734 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 62021.582734 # average WriteReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 61059.395248 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 61059.395248 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 61059.395248 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 61059.395248 # average overall miss latency -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 264.661885 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 216.132475 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 264.659128 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 216.130297 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 264.656363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 216.128138 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 264.653570 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 216.125986 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000262 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.003298 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.003298 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.004038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.003298 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.004038 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.003298 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.029607 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 2932 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2904 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.044739 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 39936 # Number of tag accesses -system.l2c.tags.data_accesses 39936 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 116 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 116 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 608 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 608 # number of WritebackClean hits -system.l2c.ReadCleanReq_hits::cpu0.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 60 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 240 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 9 # 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average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49503.174603 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49504.761905 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49503.571429 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49513.647643 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49505.506608 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 49527.295285 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 49506.607930 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49542.183623 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49505.506608 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49555.831266 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49507.709251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49519.690782 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49513.647643 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49505.506608 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 49527.295285 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49506.607930 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49542.183623 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49505.506608 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49555.831266 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49507.709251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49519.690782 # average overall mshr miss latency -system.membus.trans_dist::ReadResp 2872 # Transaction distribution -system.membus.trans_dist::ReadExReq 556 # Transaction distribution -system.membus.trans_dist::ReadExResp 556 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2872 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6856 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6856 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 219392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 219392 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3442 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3442 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3442 # Request fanout histogram -system.membus.reqLayer0.occupancy 3471468 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17140000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.3 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4556 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 852 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 3148 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 116 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 608 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 128 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 556 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 556 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1852 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1296 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1078 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 987 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8260 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 39360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 31488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 283392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3704 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 3704 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3704 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3002000 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 694500 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index d462b7494..e69de29bb 100644 --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,152 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.199332 # Number of seconds simulated -sim_ticks 199332411500 # Number of ticks simulated -final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1276946 # Simulator instruction rate (inst/s) -host_op_rate 1276946 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 638473293 # Simulator tick rate (ticks/s) -host_mem_usage 226984 # Number of bytes of host memory used -host_seconds 312.20 # Real time elapsed on the host -sim_insts 398664595 # Number of instructions simulated -sim_ops 398664595 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory -system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory -system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory -system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory -system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754489 # DTB read hits -system.cpu.dtb.read_misses 21 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754510 # DTB read accesses -system.cpu.dtb.write_hits 73520729 # DTB write hits -system.cpu.dtb.write_misses 35 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73520764 # DTB write accesses -system.cpu.dtb.data_hits 168275218 # DTB hits -system.cpu.dtb.data_misses 56 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275274 # DTB accesses -system.cpu.itb.fetch_hits 398664651 # ITB hits -system.cpu.itb.fetch_misses 173 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398664824 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 398664824 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 398664595 # Number of instructions committed -system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses -system.cpu.num_func_calls 16015498 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls -system.cpu.num_int_insts 316365907 # number of integer instructions -system.cpu.num_fp_insts 155295119 # number of float instructions -system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read -system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read -system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written -system.cpu.num_mem_refs 168275274 # number of memory refs -system.cpu.num_load_insts 94754510 # Number of load instructions -system.cpu.num_store_insts 73520764 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 398664824 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 44587532 # Number of branches fetched -system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction -system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction -system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction -system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction -system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::MemRead 94754510 23.77% 81.56% # Class of executed instruction -system.cpu.op_class::MemWrite 73520764 18.44% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 398664651 # Class of executed instruction -system.membus.trans_dist::ReadReq 493419140 # Transaction distribution -system.membus.trans_dist::ReadResp 493419140 # Transaction distribution -system.membus.trans_dist::WriteReq 73520729 # Transaction distribution -system.membus.trans_dist::WriteResp 73520729 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 566939869 # Request fanout histogram -system.membus.snoop_fanout::mean 0.703187 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456853 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 168275218 29.68% 29.68% # Request fanout histogram -system.membus.snoop_fanout::1 398664651 70.32% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 566939869 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index d612f6415..e69de29bb 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,2892 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000126 # Number of seconds simulated -sim_ticks 125889000 # Number of ticks simulated -final_tick 125889000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196054 # Simulator instruction rate (inst/s) -host_op_rate 196054 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 21072637 # Simulator tick rate (ticks/s) -host_mem_usage 267156 # Number of bytes of host memory used -host_seconds 5.97 # Real time elapsed on the host -sim_insts 1171234 # Number of instructions simulated -sim_ops 1171234 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 1536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 5824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 45696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 1536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 5824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 31616 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 24 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 91 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 714 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 190644139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 86425343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 12201225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7117381 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 46262978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 10676072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2033537 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7625766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 362986440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190644139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 12201225 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 46262978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2033537 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 251141879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190644139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 86425343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 12201225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7117381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 46262978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 10676072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2033537 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7625766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 362986440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 714 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 714 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 45696 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 45696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 120 # Per bank write bursts -system.physmem.perBankRdBursts::1 45 # Per bank write bursts -system.physmem.perBankRdBursts::2 34 # Per bank write bursts -system.physmem.perBankRdBursts::3 62 # Per bank write bursts -system.physmem.perBankRdBursts::4 68 # Per bank write bursts -system.physmem.perBankRdBursts::5 28 # Per bank write bursts -system.physmem.perBankRdBursts::6 19 # Per bank write bursts -system.physmem.perBankRdBursts::7 28 # Per bank write bursts -system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 31 # Per bank write bursts -system.physmem.perBankRdBursts::10 23 # Per bank write bursts -system.physmem.perBankRdBursts::11 13 # Per bank write bursts -system.physmem.perBankRdBursts::12 69 # Per bank write bursts -system.physmem.perBankRdBursts::13 47 # Per bank write bursts -system.physmem.perBankRdBursts::14 19 # Per bank write bursts -system.physmem.perBankRdBursts::15 101 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 125655000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 714 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.392265 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.885057 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 238.848920 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 70 38.67% 38.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41 22.65% 61.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 29 16.02% 77.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 15 8.29% 85.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9 4.97% 90.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7 3.87% 94.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 1.66% 96.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.10% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 2.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 181 # Bytes accessed per row activation -system.physmem.totQLat 8022250 # Total ticks spent queuing -system.physmem.totMemAccLat 21409750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11235.64 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29985.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 362.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 362.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.84 # Data bus utilization in percentage -system.physmem.busUtilRead 2.84 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 529 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.09 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 175987.39 # Average gap between requests -system.physmem.pageHitRate 74.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 914760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 499125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3088800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61236810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 21187500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 95063955 # Total energy per rank (pJ) -system.physmem_0.averagePower 761.486343 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 34878500 # Time in different power states -system.physmem_0.memoryStateTime::REF 4160000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 85815250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 453600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 247500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2324400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8136960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 43234785 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36978750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 91375995 # Total energy per rank (pJ) -system.physmem_1.averagePower 731.944849 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 61171750 # Time in different power states -system.physmem_1.memoryStateTime::REF 4160000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 59522000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 99978 # Number of BP lookups -system.cpu0.branchPred.condPredicted 95393 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1592 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 97255 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 0 # Number of BTB hits -system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 1133 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 97255 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 89772 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 7483 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 1066 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 251779 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 22796 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 589750 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 99978 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 90905 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 197463 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3483 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 64 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 2183 # Number of stall cycles due to pending traps -system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8051 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 854 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 224259 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.629772 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.263592 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34588 15.42% 15.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 92788 41.38% 56.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 690 0.31% 57.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1001 0.45% 57.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 509 0.23% 57.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 88318 39.38% 97.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 733 0.33% 97.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 501 0.22% 97.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5131 2.29% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 224259 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.397086 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.342332 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17767 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 19916 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 184006 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 829 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1741 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 571897 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1741 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18447 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2370 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16226 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 184143 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1332 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 566816 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 855 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 387804 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1129387 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 853087 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 2 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 368443 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 19361 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1077 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1101 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5304 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 180818 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 91318 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 88191 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 87908 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 472586 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1109 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 468485 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 16710 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13548 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 550 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 224259 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.089035 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.110026 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 37572 16.75% 16.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4453 1.99% 18.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 89499 39.91% 58.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 89119 39.74% 98.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1731 0.77% 99.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 984 0.44% 99.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 574 0.26% 99.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 227 0.10% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 100 0.04% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 224259 # Number of insts issued each cycle -system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 140 42.68% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 69 21.04% 63.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 119 36.28% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 197740 42.21% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.21% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 180204 38.47% 80.67% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 90541 19.33% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 468485 # Type of FU issued -system.cpu0.iq.rate 1.860699 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 328 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000700 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1161676 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 490453 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 465867 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 468813 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 87651 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 3007 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1906 # Number of stores squashed -system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1741 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2371 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 562514 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 182 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 180818 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 91318 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 990 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1703 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1939 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 466997 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 179835 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1488 # Number of squashed instructions skipped in execute -system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 88819 # number of nop insts executed -system.cpu0.iew.exec_refs 270170 # number of memory reference insts executed -system.cpu0.iew.exec_branches 92803 # Number of branches executed -system.cpu0.iew.exec_stores 90335 # Number of stores executed -system.cpu0.iew.exec_rate 1.854789 # Inst execution rate -system.cpu0.iew.wb_sent 466340 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 465867 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 276291 # num instructions producing a value -system.cpu0.iew.wb_consumers 279830 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.850301 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.987353 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 17414 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1592 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 220844 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.467878 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.142709 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 37532 16.99% 16.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 91545 41.45% 58.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2011 0.91% 59.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 623 0.28% 59.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 506 0.23% 59.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 87423 39.59% 99.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 455 0.21% 99.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 281 0.13% 99.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 468 0.21% 100.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 220844 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 545016 # Number of instructions committed -system.cpu0.commit.committedOps 545016 # Number of ops (including micro ops) committed -system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 267223 # Number of memory references committed -system.cpu0.commit.loads 177811 # Number of loads committed -system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 91299 # Number of branches committed -system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 366774 # Number of committed integer instructions. -system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 88031 16.15% 16.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 189678 34.80% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.95% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 177895 32.64% 83.59% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 89412 16.41% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 545016 # Class of committed instruction -system.cpu0.commit.bw_lim_events 468 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 781645 # The number of ROB reads -system.cpu0.rob.rob_writes 1128336 # The number of ROB writes -system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27520 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 456901 # Number of Instructions Simulated -system.cpu0.committedOps 456901 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.551058 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.551058 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.814691 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.814691 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 834795 # number of integer regfile reads -system.cpu0.int_regfile_writes 376287 # number of integer regfile writes -system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 272308 # number of misc regfile reads -system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 143.015419 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 180238 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 1047.895349 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 143.015419 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.279327 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.279327 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 726286 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 726286 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 91504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 91504 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 88818 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 88818 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 19 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 180322 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 180322 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 180322 # number of overall hits -system.cpu0.dcache.overall_hits::total 180322 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 576 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 576 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 552 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 552 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 23 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 23 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1128 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1128 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1128 # number of overall misses -system.cpu0.dcache.overall_misses::total 1128 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 18232000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 18232000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36205990 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36205990 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 589500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 589500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 54437990 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 54437990 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 54437990 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 54437990 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 92080 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 92080 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 89370 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 89370 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 181450 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 181450 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 181450 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 181450 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006255 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006255 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006177 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006177 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.547619 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.547619 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006217 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006217 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006217 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006217 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31652.777778 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31652.777778 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65590.561594 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 65590.561594 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 25630.434783 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 25630.434783 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 48260.629433 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 48260.629433 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 48260.629433 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 48260.629433 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.181818 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 380 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 380 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 386 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 386 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 766 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 766 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 766 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 766 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 196 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 196 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 166 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 166 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 23 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 23 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7598500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7598500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8576000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8576000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 566500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 566500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 16174500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16174500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 16174500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16174500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002129 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002129 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001857 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001857 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.547619 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.547619 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.001995 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.001995 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.001995 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.001995 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 38767.857143 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 38767.857143 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 51662.650602 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 51662.650602 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 24630.434783 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 24630.434783 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 44680.939227 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 44680.939227 # average overall mshr miss latency -system.cpu0.icache.tags.replacements 403 # number of replacements -system.cpu0.icache.tags.tagsinuse 251.059263 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7130 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 705 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.113475 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 251.059263 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490350 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.490350 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.589844 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 8756 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 8756 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7130 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7130 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7130 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7130 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7130 # number of overall hits -system.cpu0.icache.overall_hits::total 7130 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 921 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 921 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 921 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 921 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 921 # number of overall misses -system.cpu0.icache.overall_misses::total 921 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 43922000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 43922000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 43922000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 43922000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 43922000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 43922000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8051 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8051 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8051 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8051 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8051 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8051 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114396 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.114396 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114396 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.114396 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114396 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.114396 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47689.467970 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 47689.467970 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47689.467970 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 47689.467970 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47689.467970 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 47689.467970 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 113 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.250000 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 403 # number of writebacks -system.cpu0.icache.writebacks::total 403 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 706 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 706 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 706 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 706 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 706 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 706 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 33748500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 33748500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 33748500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 33748500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 33748500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 33748500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087691 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.087691 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087691 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.087691 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47802.407932 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47802.407932 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 47802.407932 # average overall mshr miss latency -system.cpu1.branchPred.lookups 75929 # Number of BP lookups -system.cpu1.branchPred.condPredicted 68631 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 2222 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 68395 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 0 # Number of BTB hits -system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 1839 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 68395 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 58396 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 9999 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 1194 # Number of mispredicted indirect branches. -system.cpu1.numCycles 196540 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 32617 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 424540 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 75929 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 60235 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 157282 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4599 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1756 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 22091 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 889 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 193967 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 2.188723 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.372433 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 56525 29.14% 29.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 66630 34.35% 63.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5516 2.84% 66.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3688 1.90% 68.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 688 0.35% 68.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 50225 25.89% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1136 0.59% 95.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1351 0.70% 95.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 8208 4.23% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 193967 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.386328 # Number of branch fetches per cycle -system.cpu1.fetch.rate 2.160069 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20990 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50963 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 116406 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3299 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2299 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 394135 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2299 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22042 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 22361 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 117990 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 14649 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 387817 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 13215 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full -system.cpu1.rename.RenamedOperands 272713 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 753683 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 582463 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 32 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 245854 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 26859 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1602 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1739 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 20098 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 111716 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 54519 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 52739 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 48254 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 321016 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5993 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 319557 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 23622 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 18296 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 1159 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 193967 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.647481 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.362491 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 60994 31.45% 31.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 19742 10.18% 41.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 53241 27.45% 69.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 52847 27.25% 96.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3638 1.88% 98.19% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1763 0.91% 99.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1052 0.54% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 407 0.21% 99.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 283 0.15% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 193967 # Number of insts issued each cycle -system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 169 37.31% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 37.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 58 12.80% 50.11% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 226 49.89% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 151236 47.33% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 114807 35.93% 83.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 53514 16.75% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 319557 # Type of FU issued -system.cpu1.iq.rate 1.625913 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 453 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001418 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 833588 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 350606 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 315974 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 320010 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 48132 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4290 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 32 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 2608 # Number of stores squashed -system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2299 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 7227 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 380950 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 338 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 111716 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 54519 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1500 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2382 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 2811 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 317250 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 110168 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2307 # Number of squashed instructions skipped in execute -system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 53941 # number of nop insts executed -system.cpu1.iew.exec_refs 163396 # number of memory reference insts executed -system.cpu1.iew.exec_branches 64160 # Number of branches executed -system.cpu1.iew.exec_stores 53228 # Number of stores executed -system.cpu1.iew.exec_rate 1.614175 # Inst execution rate -system.cpu1.iew.wb_sent 316458 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 315974 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 181395 # num instructions producing a value -system.cpu1.iew.wb_consumers 189019 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.607683 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.959665 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 24733 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4834 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 2222 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 189334 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.881189 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.115429 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 65341 34.51% 34.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 60499 31.95% 66.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5361 2.83% 69.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5469 2.89% 72.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1297 0.69% 72.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 48347 25.54% 98.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 750 0.40% 98.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1038 0.55% 99.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1232 0.65% 100.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 189334 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 356173 # Number of instructions committed -system.cpu1.commit.committedOps 356173 # Number of ops (including micro ops) committed -system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 159337 # Number of memory references committed -system.cpu1.commit.loads 107426 # Number of loads committed -system.cpu1.commit.membars 4118 # Number of memory barriers committed -system.cpu1.commit.branches 61998 # Number of branches committed -system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 243452 # Number of committed integer instructions. -system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 52786 14.82% 14.82% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 139932 39.29% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.11% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 111544 31.32% 85.43% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 51911 14.57% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 356173 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1232 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 568422 # The number of ROB reads -system.cpu1.rob.rob_writes 766486 # The number of ROB writes -system.cpu1.timesIdled 207 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2573 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 46533 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 299269 # Number of Instructions Simulated -system.cpu1.committedOps 299269 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.656734 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.656734 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.522687 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.522687 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 554283 # number of integer regfile reads -system.cpu1.int_regfile_writes 257020 # number of integer regfile writes -system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 165298 # number of misc regfile reads -system.cpu1.misc_regfile_writes 648 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.915239 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 58936 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 2032.275862 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.915239 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050616 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 455882 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 455882 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 61472 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 61472 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 51691 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 51691 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 10 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 113163 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 113163 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 113163 # number of overall hits -system.cpu1.dcache.overall_hits::total 113163 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 523 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 523 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 150 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 150 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 60 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 60 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 673 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 673 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 673 # number of overall misses -system.cpu1.dcache.overall_misses::total 673 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8464500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8464500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2960500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2960500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 828000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 828000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 11425000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 11425000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 11425000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 11425000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 61995 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 61995 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 51841 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 51841 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 113836 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 113836 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 113836 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 113836 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008436 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.008436 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.002893 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.002893 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.857143 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.857143 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005912 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005912 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005912 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005912 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16184.512428 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16184.512428 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19736.666667 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19736.666667 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13800 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 13800 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16976.225854 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16976.225854 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16976.225854 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16976.225854 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 362 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 362 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 43 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 43 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 405 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 405 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 405 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 161 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 60 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 268 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 268 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1517000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1517000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 768000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 768000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3047000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3047000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3047000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3047000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002064 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002064 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.857143 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.857143 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002354 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002354 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002354 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002354 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9503.105590 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9503.105590 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14177.570093 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14177.570093 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 12800 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 12800 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11369.402985 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11369.402985 # average overall mshr miss latency -system.cpu1.icache.tags.replacements 548 # number of replacements -system.cpu1.icache.tags.tagsinuse 97.609803 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 21265 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 682 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 31.180352 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 97.609803 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.190644 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.190644 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.261719 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 22773 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 22773 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 21265 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 21265 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 21265 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 21265 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 21265 # number of overall hits -system.cpu1.icache.overall_hits::total 21265 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 826 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 826 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 826 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 826 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 826 # number of overall misses -system.cpu1.icache.overall_misses::total 826 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13533000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 13533000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 13533000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 13533000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 13533000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 13533000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 22091 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 22091 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 22091 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 22091 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 22091 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 22091 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037391 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.037391 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037391 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.037391 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037391 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.037391 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16383.777240 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 16383.777240 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16383.777240 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 16383.777240 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16383.777240 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 16383.777240 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 548 # number of writebacks -system.cpu1.icache.writebacks::total 548 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 144 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 144 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 144 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 144 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 144 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 682 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 682 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 682 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 682 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 682 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 682 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 10822000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 10822000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 10822000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 10822000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 10822000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 10822000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030872 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.030872 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030872 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.030872 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 15868.035191 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 15868.035191 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 15868.035191 # average overall mshr miss latency -system.cpu2.branchPred.lookups 65577 # Number of BP lookups -system.cpu2.branchPred.condPredicted 57724 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2464 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 57712 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 0 # Number of BTB hits -system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1983 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 57712 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 46848 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 10864 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 1379 # Number of mispredicted indirect branches. -system.cpu2.numCycles 195641 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 39175 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 357136 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 65577 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 48831 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 146036 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 5085 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 2246 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 27545 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 945 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 190045 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.879218 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.350973 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 72125 37.95% 37.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 57864 30.45% 68.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8007 4.21% 72.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3378 1.78% 74.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 697 0.37% 74.76% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 36524 19.22% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1219 0.64% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 1446 0.76% 95.38% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 8785 4.62% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 190045 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.335190 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.825466 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 23115 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 69586 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 90388 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4404 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2542 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 325134 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2542 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 24144 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 33213 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 15151 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 91754 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 23231 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 318523 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 20453 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full -system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 223607 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605589 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 472031 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 193721 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 29886 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1685 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1831 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 29018 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 87037 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 41099 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 41296 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34595 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 259686 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8253 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 260132 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 104 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 25858 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19408 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 1214 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 190045 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.368792 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.393545 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 77002 40.52% 40.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 26562 13.98% 54.49% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39729 20.91% 75.40% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 39504 20.79% 96.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3584 1.89% 98.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1794 0.94% 99.02% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1114 0.59% 99.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 438 0.23% 99.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 318 0.17% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 190045 # Number of insts issued each cycle -system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 198 41.51% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 41.51% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 44 9.22% 50.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 235 49.27% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 127776 49.12% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.12% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 92295 35.48% 84.60% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 40061 15.40% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 260132 # Type of FU issued -system.cpu2.iq.rate 1.329639 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 477 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001834 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 710890 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 293781 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 256087 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 260609 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 34538 # Number of loads that had data forwarded from stores -system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 4572 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 34 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 2770 # Number of stores squashed -system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2542 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9787 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 310555 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 374 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 87037 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 41099 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1544 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 30 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 2649 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3110 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 257554 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 85462 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 2578 # Number of squashed instructions skipped in execute -system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 42616 # number of nop insts executed -system.cpu2.iew.exec_refs 125205 # number of memory reference insts executed -system.cpu2.iew.exec_branches 53054 # Number of branches executed -system.cpu2.iew.exec_stores 39743 # Number of stores executed -system.cpu2.iew.exec_rate 1.316462 # Inst execution rate -system.cpu2.iew.wb_sent 256619 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 256087 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 143359 # num instructions producing a value -system.cpu2.iew.wb_consumers 151246 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.308964 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.947853 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 27054 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7039 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 2464 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 184962 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.532661 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.012592 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 83513 45.15% 45.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 49247 26.63% 71.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5539 2.99% 74.77% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7621 4.12% 78.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1289 0.70% 79.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34776 18.80% 98.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 735 0.40% 98.79% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1086 0.59% 99.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1156 0.62% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 184962 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 283484 # Number of instructions committed -system.cpu2.commit.committedOps 283484 # Number of ops (including micro ops) committed -system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 120794 # Number of memory references committed -system.cpu2.commit.loads 82465 # Number of loads committed -system.cpu2.commit.membars 6325 # Number of memory barriers committed -system.cpu2.commit.branches 50613 # Number of branches committed -system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 193531 # Number of committed integer instructions. -system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 41403 14.61% 14.61% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 114962 40.55% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.16% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 88790 31.32% 86.48% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 38329 13.52% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 283484 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1156 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 493758 # The number of ROB reads -system.cpu2.rob.rob_writes 626207 # The number of ROB writes -system.cpu2.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5596 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 47431 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 235756 # Number of Instructions Simulated -system.cpu2.committedOps 235756 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.829845 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.829845 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.205044 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.205044 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 440950 # number of integer regfile reads -system.cpu2.int_regfile_writes 206257 # number of integer regfile writes -system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 127194 # number of misc regfile reads -system.cpu2.misc_regfile_writes 648 # number of misc regfile writes -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.976674 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 45756 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1525.200000 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.976674 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052689 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.052689 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 357076 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 357076 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 50413 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 50413 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 38109 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 38109 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 88522 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 88522 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 88522 # number of overall hits -system.cpu2.dcache.overall_hits::total 88522 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 463 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 152 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 152 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 615 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 615 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 615 # number of overall misses -system.cpu2.dcache.overall_misses::total 615 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8046000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 8046000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3843000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3843000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 809500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 809500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 11889000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 11889000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 11889000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 11889000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 50876 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 50876 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 38261 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 38261 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 89137 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 89137 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 89137 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 89137 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009101 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009101 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003973 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003973 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.779412 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.779412 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006899 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.006899 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006899 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.006899 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17377.969762 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17377.969762 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 25282.894737 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 25282.894737 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 15273.584906 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 15273.584906 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19331.707317 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 19331.707317 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19331.707317 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 19331.707317 # average overall miss latency -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 298 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 298 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits -system.cpu2.dcache.SwapReq_mshr_hits::cpu2.data 5 # number of SwapReq MSHR hits -system.cpu2.dcache.SwapReq_mshr_hits::total 5 # number of SwapReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 345 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 345 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 165 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 48 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 48 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 270 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 270 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1997000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1997000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1762500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1762500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 756500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 756500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3759500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3759500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3759500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3759500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003243 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003243 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002744 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002744 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.705882 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.705882 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003029 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003029 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003029 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003029 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12103.030303 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12103.030303 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16785.714286 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16785.714286 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 15760.416667 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 15760.416667 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13924.074074 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13924.074074 # average overall mshr miss latency -system.cpu2.icache.tags.replacements 555 # number of replacements -system.cpu2.icache.tags.tagsinuse 101.261159 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 26702 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 694 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 38.475504 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 101.261159 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.197776 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.197776 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 139 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.271484 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 28239 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 28239 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 26702 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 26702 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 26702 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 26702 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 26702 # number of overall hits -system.cpu2.icache.overall_hits::total 26702 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 843 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 843 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 843 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 843 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 843 # number of overall misses -system.cpu2.icache.overall_misses::total 843 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 19527000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 19527000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 19527000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 19527000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 19527000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 19527000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 27545 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 27545 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 27545 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 27545 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 27545 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 27545 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.030604 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.030604 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.030604 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.030604 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.030604 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.030604 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23163.701068 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23163.701068 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23163.701068 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23163.701068 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23163.701068 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23163.701068 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 220 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 7 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 31.428571 # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 555 # number of writebacks -system.cpu2.icache.writebacks::total 555 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 149 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 149 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 149 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 149 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 149 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 149 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 694 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 694 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 694 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 694 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 694 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 694 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 15501500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 15501500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 15501500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 15501500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 15501500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 15501500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025195 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.025195 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025195 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.025195 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 22336.455331 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 22336.455331 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 22336.455331 # average overall mshr miss latency -system.cpu3.branchPred.lookups 57182 # Number of BP lookups -system.cpu3.branchPred.condPredicted 48797 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 2586 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 48362 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 0 # Number of BTB hits -system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 2121 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 48362 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 37349 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 11013 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 1473 # Number of mispredicted indirect branches. -system.cpu3.numCycles 195288 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 45700 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 298023 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 57182 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 39470 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 143366 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 5327 # Number of cycles fetch has spent squashing -system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1948 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 34377 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 1007 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 193690 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.538660 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.252819 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 90820 46.89% 46.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51773 26.73% 73.62% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 11180 5.77% 79.39% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3385 1.75% 81.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 629 0.32% 81.46% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 24090 12.44% 93.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1143 0.59% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 1449 0.75% 95.24% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 9221 4.76% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 193690 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.292809 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.526069 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 23670 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 95373 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 66026 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 5948 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2663 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 265184 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2663 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 24704 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 48500 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 15195 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 67410 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 35208 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 258083 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 30956 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full -system.cpu3.rename.RenamedOperands 178302 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 471983 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 372133 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 28 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 146703 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 31599 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1744 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1884 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 41025 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 65361 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 28681 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 31955 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 22074 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 204469 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 11525 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 207359 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 114 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 27267 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 21384 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 1390 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 193690 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.070572 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.351583 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 96267 49.70% 49.70% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 35951 18.56% 68.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 27208 14.05% 82.31% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 26919 13.90% 96.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3677 1.90% 98.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1713 0.88% 98.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 1079 0.56% 99.55% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 520 0.27% 99.82% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 356 0.18% 100.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 193690 # Number of insts issued each cycle -system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 253 45.42% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 45.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 65 11.67% 57.09% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 239 42.91% 100.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 106203 51.22% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.22% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 73580 35.48% 86.70% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 27576 13.30% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 207359 # Type of FU issued -system.cpu3.iq.rate 1.061811 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 557 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.002686 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 609079 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 243241 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 202956 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 56 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 207916 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 22032 # Number of loads that had data forwarded from stores -system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 4860 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 37 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 2877 # Number of stores squashed -system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2663 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 13076 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 249222 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 65361 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 28681 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1596 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 2781 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 3236 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 204483 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 63509 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 2876 # Number of squashed instructions skipped in execute -system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 33228 # number of nop insts executed -system.cpu3.iew.exec_refs 90738 # number of memory reference insts executed -system.cpu3.iew.exec_branches 43690 # Number of branches executed -system.cpu3.iew.exec_stores 27229 # Number of stores executed -system.cpu3.iew.exec_rate 1.047084 # Inst execution rate -system.cpu3.iew.wb_sent 203493 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 202956 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 108735 # num instructions producing a value -system.cpu3.iew.wb_consumers 116603 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.039265 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.932523 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 28499 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 10135 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2586 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 188297 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.172069 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.830514 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 105729 56.15% 56.15% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 39844 21.16% 77.31% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5499 2.92% 80.23% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 10725 5.70% 85.93% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1244 0.66% 86.59% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 22268 11.83% 98.41% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 755 0.40% 98.81% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1030 0.55% 99.36% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1203 0.64% 100.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 188297 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 220697 # Number of instructions committed -system.cpu3.commit.committedOps 220697 # Number of ops (including micro ops) committed -system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 86305 # Number of memory references committed -system.cpu3.commit.loads 60501 # Number of loads committed -system.cpu3.commit.membars 9419 # Number of memory barriers committed -system.cpu3.commit.branches 41182 # Number of branches committed -system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 149608 # Number of committed integer instructions. -system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 31970 14.49% 14.49% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 93003 42.14% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.63% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 69920 31.68% 88.31% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 25804 11.69% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 220697 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1203 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 435704 # The number of ROB reads -system.cpu3.rob.rob_writes 503857 # The number of ROB writes -system.cpu3.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1598 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 47785 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 179308 # Number of Instructions Simulated -system.cpu3.committedOps 179308 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.089120 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.089120 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.918172 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.918172 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 337868 # number of integer regfile reads -system.cpu3.int_regfile_writes 159407 # number of integer regfile writes -system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 92688 # number of misc regfile reads -system.cpu3.misc_regfile_writes 648 # number of misc regfile writes -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.364861 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 33092 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1103.066667 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.364861 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.049541 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.049541 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 269290 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 269290 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 40990 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 40990 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 25593 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 25593 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 66583 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 66583 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 66583 # number of overall hits -system.cpu3.dcache.overall_hits::total 66583 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 463 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 141 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 141 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 604 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 604 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 604 # number of overall misses -system.cpu3.dcache.overall_misses::total 604 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7157000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 7157000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3001000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3001000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 868000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 868000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 10158000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 10158000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 10158000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 10158000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41453 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41453 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 25734 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 25734 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 67187 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 67187 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 67187 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 67187 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011169 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.011169 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.005479 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.005479 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008990 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008990 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008990 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008990 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15457.883369 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 15457.883369 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21283.687943 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 21283.687943 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 15781.818182 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 15781.818182 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16817.880795 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 16817.880795 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16817.880795 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 16817.880795 # average overall miss latency -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 291 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 35 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 35 # number of WriteReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_hits::cpu3.data 4 # number of SwapReq MSHR hits -system.cpu3.dcache.SwapReq_mshr_hits::total 4 # number of SwapReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 326 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 326 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 172 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 51 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 278 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 278 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1798500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1798500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1645500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1645500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 813000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 813000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3444000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3444000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3444000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3444000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004149 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004149 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004119 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004119 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.728571 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.728571 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004138 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004138 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004138 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004138 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10456.395349 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10456.395349 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15523.584906 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15523.584906 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 15941.176471 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 15941.176471 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12388.489209 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12388.489209 # average overall mshr miss latency -system.cpu3.icache.tags.replacements 608 # number of replacements -system.cpu3.icache.tags.tagsinuse 93.738869 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 33506 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 743 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 45.095559 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 93.738869 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.183084 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.183084 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.263672 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 35120 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 35120 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 33506 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 33506 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 33506 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 33506 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 33506 # number of overall hits -system.cpu3.icache.overall_hits::total 33506 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 871 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 871 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 871 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 871 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 871 # number of overall misses -system.cpu3.icache.overall_misses::total 871 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 11659000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 11659000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 11659000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 11659000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 11659000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 11659000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 34377 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 34377 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 34377 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 34377 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 34377 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 34377 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.025337 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.025337 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.025337 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.025337 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.025337 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.025337 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13385.763490 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13385.763490 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13385.763490 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13385.763490 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13385.763490 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13385.763490 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 608 # number of writebacks -system.cpu3.icache.writebacks::total 608 # number of writebacks -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 128 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 128 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 128 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 128 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 128 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 128 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 743 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 743 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 743 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 743 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 743 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 743 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 10055000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 10055000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 10055000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 10055000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 10055000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 10055000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021613 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021613 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021613 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.021613 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021613 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.021613 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13532.974428 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13532.974428 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13532.974428 # average overall mshr miss latency -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 458.562207 # Cycle average of tags in use -system.l2c.tags.total_refs 3097 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 581 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 5.330465 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.811695 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 303.236105 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.939439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 17.006196 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1.379366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 67.599671 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.915132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1.812120 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1.862482 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004627 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000899 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000259 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000021 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.001031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000090 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000028 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006997 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 581 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008865 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 32091 # Number of tag accesses -system.l2c.tags.data_accesses 32091 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 751 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 751 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 329 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 654 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 595 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 735 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 2313 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 5 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 11 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 329 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 654 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 2345 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 329 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 654 # number of overall hits -system.l2c.overall_hits::cpu1.data 11 # number of overall hits -system.l2c.overall_hits::cpu2.inst 595 # number of overall hits -system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 735 # number of overall hits -system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 2345 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 24 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 89 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 377 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 28 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 99 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 8 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 512 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 76 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 3 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 89 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 377 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 170 # 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number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 751 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 751 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 22 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 24 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 12 # 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number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 14 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 121 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 706 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 175 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 682 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 694 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 743 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3077 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 706 # 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average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19028.089888 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74813.829787 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65166.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70615.384615 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 67250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 72820.610687 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 67163.563830 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 77375 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 68395.959596 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 75967.105263 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72750 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 69312.500000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 77333.333333 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 75342.696629 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67163.563830 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75329.411765 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70119.047619 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 77375 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 69266.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 70071.328671 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67163.563830 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75329.411765 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 80604.166667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 69873.626374 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70119.047619 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 77375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 69266.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 70071.328671 # average overall mshr miss latency -system.membus.trans_dist::ReadResp 583 # Transaction distribution -system.membus.trans_dist::UpgradeReq 286 # Transaction distribution -system.membus.trans_dist::ReadExReq 182 # Transaction distribution -system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 583 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1765 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1765 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45696 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45696 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 248 # Total snoops (count) -system.membus.snoop_fanout::samples 1051 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1051 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1051 # Request fanout histogram -system.membus.reqLayer0.occupancy 998006 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3803500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 6324 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1712 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3265 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 3513 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 6 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 2114 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 289 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 289 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 399 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 399 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 2825 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 695 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1814 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1912 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1943 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2094 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9492 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 70912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 78720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 79936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 332224 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1039 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4208 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.288736 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.116485 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1347 32.01% 32.01% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1142 27.14% 59.15% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 876 20.82% 79.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 843 20.03% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4208 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5296461 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 4.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1058997 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 523496 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1025493 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 437958 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1044987 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 431472 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1116994 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 444965 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index f2280533e..e69de29bb 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,991 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 87707000 # Number of ticks simulated -final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1039500 # Simulator instruction rate (inst/s) -host_op_rate 1039462 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 134594380 # Simulator tick rate (ticks/s) -host_mem_usage 262812 # Number of bytes of host memory used -host_seconds 0.65 # Real time elapsed on the host -sim_insts 677333 # Number of instructions simulated -sim_ops 677333 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 35776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 559 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2189107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 729702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2189107 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 729702 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2189107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 729702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 175415 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 175326 # Number of instructions committed -system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls -system.cpu0.num_int_insts 120376 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read -system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 82397 # number of memory refs -system.cpu0.num_load_insts 54591 # Number of load instructions -system.cpu0.num_store_insts 27806 # Number of store instructions -system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 175414.998000 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 29689 # Number of branches fetched -system.cpu0.op_class::No_OpClass 26416 15.06% 15.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 66491 37.91% 52.97% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 52.97% # Class of executed instruction -system.cpu0.op_class::MemRead 54675 31.17% 84.15% # Class of executed instruction -system.cpu0.op_class::MemWrite 27806 15.85% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 175388 # Class of executed instruction -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 150.745705 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 81882 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 490.311377 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 150.745705 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 329804 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 329804 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits -system.cpu0.dcache.overall_hits::total 82008 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses -system.cpu0.dcache.overall_misses::total 328 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 222.772732 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 222.772732 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 175855 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 175855 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits -system.cpu0.icache.overall_hits::total 174921 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 215 # number of writebacks -system.cpu0.icache.writebacks::total 215 # number of writebacks -system.cpu1.numCycles 173297 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 167400 # Number of instructions committed -system.cpu1.committedOps 167400 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107326 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 633 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 34043 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107326 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 254436 # number of times the integer registers were read -system.cpu1.num_int_register_writes 94218 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 49494 # number of memory refs -system.cpu1.num_load_insts 39345 # Number of load instructions -system.cpu1.num_store_insts 10149 # Number of store instructions -system.cpu1.num_idle_cycles 7872.827276 # Number of idle cycles -system.cpu1.num_busy_cycles 165424.172724 # Number of busy cycles -system.cpu1.not_idle_fraction 0.954570 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.045430 # Percentage of idle cycles -system.cpu1.Branches 35694 # Number of branches fetched -system.cpu1.op_class::No_OpClass 26475 15.81% 15.81% # Class of executed instruction -system.cpu1.op_class::IntAlu 71873 42.93% 58.74% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu1.op_class::MemRead 58935 35.20% 93.94% # Class of executed instruction -system.cpu1.op_class::MemWrite 10149 6.06% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 167432 # Class of executed instruction -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 30.295170 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 21529 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 828.038462 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 30.295170 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.059170 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.059170 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 198211 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 198211 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 39152 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39152 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 9968 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 9968 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 49120 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 49120 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 49120 # number of overall hits -system.cpu1.dcache.overall_hits::total 49120 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 185 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 185 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 102 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 102 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 61 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 61 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 287 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 287 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 287 # number of overall misses -system.cpu1.dcache.overall_misses::total 287 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 39337 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 39337 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 10070 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 10070 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 77 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 77 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 49407 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 49407 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 49407 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 49407 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004703 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004703 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.010129 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.010129 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.792208 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.792208 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005809 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005809 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005809 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005809 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.tags.replacements 278 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.752158 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167074 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 466.687151 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.752158 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.149907 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 167790 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 167790 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 167074 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 167074 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 167074 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 167074 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 167074 # number of overall hits -system.cpu1.icache.overall_hits::total 167074 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses -system.cpu1.icache.overall_misses::total 358 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 167432 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 167432 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 167432 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 167432 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 167432 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 278 # number of writebacks -system.cpu1.icache.writebacks::total 278 # number of writebacks -system.cpu2.numCycles 173296 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 167335 # Number of instructions committed -system.cpu2.committedOps 167335 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 114196 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 633 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 30577 # number of instructions that are conditional controls -system.cpu2.num_int_insts 114196 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 295784 # number of times the integer registers were read -system.cpu2.num_int_register_writes 111461 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59830 # number of memory refs -system.cpu2.num_load_insts 42793 # Number of load instructions -system.cpu2.num_store_insts 17037 # Number of store instructions -system.cpu2.num_idle_cycles 7936.997017 # Number of idle cycles -system.cpu2.num_busy_cycles 165359.002983 # Number of busy cycles -system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.Branches 32221 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23013 13.75% 13.75% # Class of executed instruction -system.cpu2.op_class::IntAlu 75303 44.99% 58.74% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 58.74% # Class of executed instruction -system.cpu2.op_class::MemRead 52014 31.08% 89.82% # Class of executed instruction -system.cpu2.op_class::MemWrite 17037 10.18% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 167367 # Class of executed instruction -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 29.575165 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 35457 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1313.222222 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 29.575165 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.057764 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.057764 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 27 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.052734 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 239521 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 239521 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 42635 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42635 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 16864 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 16864 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 59499 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 59499 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 59499 # number of overall hits -system.cpu2.dcache.overall_hits::total 59499 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 150 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 150 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 255 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 255 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 255 # number of overall misses -system.cpu2.dcache.overall_misses::total 255 # number of overall misses -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42785 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42785 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 16969 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 16969 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 59754 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 59754 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 59754 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 59754 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003506 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003506 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006188 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006188 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.818182 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.818182 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004267 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004267 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004267 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004267 # miss rate for overall accesses -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.tags.replacements 278 # number of replacements -system.cpu2.icache.tags.tagsinuse 74.781471 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167009 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 466.505587 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 74.781471 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.146058 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 167725 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 167725 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 167009 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 167009 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 167009 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 167009 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 167009 # number of overall hits -system.cpu2.icache.overall_hits::total 167009 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses -system.cpu2.icache.overall_misses::total 358 # number of overall misses -system.cpu2.icache.ReadReq_accesses::cpu2.inst 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 167367 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 167367 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 167367 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 167367 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 167367 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 278 # number of writebacks -system.cpu2.icache.writebacks::total 278 # number of writebacks -system.cpu3.numCycles 173297 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 167272 # Number of instructions committed -system.cpu3.committedOps 167272 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 113295 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 633 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 30996 # number of instructions that are conditional controls -system.cpu3.num_int_insts 113295 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 290503 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109270 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 58510 # number of memory refs -system.cpu3.num_load_insts 42344 # Number of load instructions -system.cpu3.num_store_insts 16166 # Number of store instructions -system.cpu3.num_idle_cycles 7999.282495 # Number of idle cycles -system.cpu3.num_busy_cycles 165297.717505 # Number of busy cycles -system.cpu3.not_idle_fraction 0.953841 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.046159 # Percentage of idle cycles -system.cpu3.Branches 32639 # Number of branches fetched -system.cpu3.op_class::No_OpClass 23433 14.01% 14.01% # Class of executed instruction -system.cpu3.op_class::IntAlu 74851 44.74% 58.75% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.75% # Class of executed instruction -system.cpu3.op_class::MemRead 52854 31.59% 90.34% # Class of executed instruction -system.cpu3.op_class::MemWrite 16166 9.66% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 167304 # Class of executed instruction -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 28.848199 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 33595 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1292.115385 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 28.848199 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.056344 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.056344 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 26 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.050781 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 234241 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 234241 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 42185 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 42185 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 15991 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 15991 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 58176 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 58176 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 58176 # number of overall hits -system.cpu3.dcache.overall_hits::total 58176 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 260 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 260 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 260 # number of overall misses -system.cpu3.dcache.overall_misses::total 260 # number of overall misses -system.cpu3.dcache.ReadReq_accesses::cpu3.data 42336 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 42336 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 16100 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 16100 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 58436 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 58436 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 58436 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 58436 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003567 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003567 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006770 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.006770 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004449 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004449 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004449 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004449 # miss rate for overall accesses -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.tags.replacements 279 # number of replacements -system.cpu3.icache.tags.tagsinuse 72.874953 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 166945 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 465.027855 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 72.874953 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.142334 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 80 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.156250 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 167663 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 167663 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 166945 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 166945 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 166945 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 166945 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 166945 # number of overall hits -system.cpu3.icache.overall_hits::total 166945 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses -system.cpu3.icache.overall_misses::total 359 # number of overall misses -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167304 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167304 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167304 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167304 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167304 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 279 # number of writebacks -system.cpu3.icache.writebacks::total 279 # number of writebacks -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use -system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 19424 # Number of tag accesses -system.l2c.tags.data_accesses 19424 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 185 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 355 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 282 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 62 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 3 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 1 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 348 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 282 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 62 # number of overall misses -system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 3 # number of overall misses -system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 1 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 82 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 467 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 358 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu2.inst 358 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu3.inst 359 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1542 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 71 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3.data 10 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.008380 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.002786 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.225681 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.742574 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.008380 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.002786 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.008380 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.002786 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.membus.trans_dist::ReadResp 423 # Transaction distribution -system.membus.trans_dist::UpgradeReq 273 # Transaction distribution -system.membus.trans_dist::UpgradeResp 80 # Transaction distribution -system.membus.trans_dist::ReadExReq 183 # Transaction distribution -system.membus.trans_dist::ReadExResp 136 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 879 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 879 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 0 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 22d94928b..e69de29bb 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,1638 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000264 # Number of seconds simulated -sim_ticks 263565500 # Number of ticks simulated -final_tick 263565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 821706 # Simulator instruction rate (inst/s) -host_op_rate 821692 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 326627282 # Simulator tick rate (ticks/s) -host_mem_usage 262816 # Number of bytes of host memory used -host_seconds 0.81 # Real time elapsed on the host -sim_insts 663039 # Number of instructions simulated -sim_ops 663039 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory -system.physmem.bytes_read::total 36608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory -system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69204809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40065942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 2428239 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3642358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 13112490 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5342126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1214119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3885182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138895265 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69204809 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 2428239 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 13112490 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1214119 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85959657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69204809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40065942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 2428239 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3642358 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 13112490 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5342126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1214119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3885182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138895265 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 527131 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158196 # Number of instructions committed -system.cpu0.committedOps 158196 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108956 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25969 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108956 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315026 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110562 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73832 # number of memory refs -system.cpu0.num_load_insts 48881 # Number of load instructions -system.cpu0.num_store_insts 24951 # Number of store instructions -system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 527130.998000 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26834 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23561 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60781 38.41% 53.29% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 48965 30.94% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 24951 15.77% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158258 # Class of executed instruction -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.050771 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73302 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 438.934132 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.050771 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283302 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.283302 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 295559 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 295559 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48703 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48703 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24717 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24717 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73420 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73420 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73420 # number of overall hits -system.cpu0.dcache.overall_hits::total 73420 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 168 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 168 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 351 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 351 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 351 # number of overall misses -system.cpu0.dcache.overall_misses::total 351 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4817500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4817500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6985500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6985500 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 395000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 395000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11803000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11803000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11803000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11803000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48871 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48871 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24900 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24900 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73771 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73771 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73771 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73771 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003438 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003438 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007349 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007349 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004758 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004758 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004758 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004758 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28675.595238 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28675.595238 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38172.131148 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38172.131148 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33626.780627 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33626.780627 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4649500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4649500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6802500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6802500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 369000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 369000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11452000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11452000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11452000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11452000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003438 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003438 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004758 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004758 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004758 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004758 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27675.595238 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27675.595238 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37172.131148 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37172.131148 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 211.380247 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157792 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 337.884368 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.380247 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412852 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.412852 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 158726 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 158726 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 157792 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157792 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157792 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157792 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157792 # number of overall hits -system.cpu0.icache.overall_hits::total 157792 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20140500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20140500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20140500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20140500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20140500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20140500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158259 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158259 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158259 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158259 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158259 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158259 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002951 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002951 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002951 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002951 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002951 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002951 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43127.408994 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 43127.408994 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 43127.408994 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 43127.408994 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 215 # number of writebacks -system.cpu0.icache.writebacks::total 215 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19673500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19673500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19673500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19673500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19673500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19673500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002951 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002951 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002951 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42127.408994 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency -system.cpu1.numCycles 527130 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 170790 # Number of instructions committed -system.cpu1.committedOps 170790 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 110708 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 34050 # number of instructions that are conditional controls -system.cpu1.num_int_insts 110708 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 268858 # number of times the integer registers were read -system.cpu1.num_int_register_writes 101318 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 52827 # number of memory refs -system.cpu1.num_load_insts 41019 # Number of load instructions -system.cpu1.num_store_insts 11808 # Number of store instructions -system.cpu1.num_idle_cycles 73818.861681 # Number of idle cycles -system.cpu1.num_busy_cycles 453311.138319 # Number of busy cycles -system.cpu1.not_idle_fraction 0.859961 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.140039 # Percentage of idle cycles -system.cpu1.Branches 35703 # Number of branches fetched -system.cpu1.op_class::No_OpClass 26483 15.50% 15.50% # Class of executed instruction -system.cpu1.op_class::IntAlu 74610 43.68% 59.18% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.18% # Class of executed instruction -system.cpu1.op_class::MemRead 57921 33.91% 93.09% # Class of executed instruction -system.cpu1.op_class::MemWrite 11808 6.91% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 170822 # Class of executed instruction -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.474097 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 25884 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 892.551724 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.474097 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051707 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.051707 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 211529 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 211529 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 40844 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40844 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 11631 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 11631 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 52475 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 52475 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 52475 # number of overall hits -system.cpu1.dcache.overall_hits::total 52475 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 167 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 167 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 272 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 272 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 272 # number of overall misses -system.cpu1.dcache.overall_misses::total 272 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1891500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1891500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1642500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1642500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 3534000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 3534000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 3534000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 3534000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41011 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41011 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 11736 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 11736 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 52747 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 52747 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 52747 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 52747 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004072 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004072 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008947 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008947 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005157 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005157 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005157 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005157 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11326.347305 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 11326.347305 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15642.857143 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 15642.857143 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 12992.647059 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 12992.647059 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1537500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1537500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3262000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3262000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3262000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3262000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004072 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004072 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008947 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008947 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005157 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005157 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005157 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005157 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10326.347305 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10326.347305 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14642.857143 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14642.857143 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency -system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 66.953040 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 170457 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 465.729508 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.953040 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130768 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.130768 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 171189 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 171189 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 170457 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 170457 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 170457 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 170457 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 170457 # number of overall hits -system.cpu1.icache.overall_hits::total 170457 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses -system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5688500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5688500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5688500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5688500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5688500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5688500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 170823 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 170823 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 170823 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 170823 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 170823 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 170823 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002143 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002143 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002143 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002143 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002143 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002143 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15542.349727 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15542.349727 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15542.349727 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15542.349727 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 280 # number of writebacks -system.cpu1.icache.writebacks::total 280 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5322500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5322500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5322500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5322500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5322500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5322500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002143 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002143 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14542.349727 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency -system.cpu2.numCycles 527130 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 168244 # Number of instructions committed -system.cpu2.committedOps 168244 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 109603 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 33329 # number of instructions that are conditional controls -system.cpu2.num_int_insts 109603 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 267321 # number of times the integer registers were read -system.cpu2.num_int_register_writes 101101 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 52443 # number of memory refs -system.cpu2.num_load_insts 40463 # Number of load instructions -system.cpu2.num_store_insts 11980 # Number of store instructions -system.cpu2.num_idle_cycles 74087.861169 # Number of idle cycles -system.cpu2.num_busy_cycles 453042.138831 # Number of busy cycles -system.cpu2.not_idle_fraction 0.859450 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.140550 # Percentage of idle cycles -system.cpu2.Branches 34984 # Number of branches fetched -system.cpu2.op_class::No_OpClass 25761 15.31% 15.31% # Class of executed instruction -system.cpu2.op_class::IntAlu 74059 44.01% 59.32% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.32% # Class of executed instruction -system.cpu2.op_class::MemRead 56476 33.56% 92.88% # Class of executed instruction -system.cpu2.op_class::MemWrite 11980 7.12% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 168276 # Class of executed instruction -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.444081 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 26343 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 878.100000 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.444081 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053602 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.053602 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 209996 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 209996 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 40285 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40285 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 11801 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 11801 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 52086 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 52086 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 52086 # number of overall hits -system.cpu2.dcache.overall_hits::total 52086 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 170 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 170 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 104 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 104 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 274 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 274 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 274 # number of overall misses -system.cpu2.dcache.overall_misses::total 274 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2220000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2220000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1703000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1703000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 260000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 3923000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 3923000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 3923000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 3923000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40455 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40455 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 11905 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 11905 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 52360 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 52360 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 52360 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 52360 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004202 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008736 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.008736 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794521 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.794521 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005233 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.005233 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005233 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.005233 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13058.823529 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 13058.823529 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 16375 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 16375 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.758621 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.758621 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 14317.518248 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 14317.518248 # average overall miss latency -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2050000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2050000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1599000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1599000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3649000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3649000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3649000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3649000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004202 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004202 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.008736 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.008736 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005233 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.005233 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005233 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.005233 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12058.823529 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12058.823529 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15375 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15375 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.758621 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.758621 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency -system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 69.363893 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 167911 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 458.773224 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.363893 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135476 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.135476 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 168643 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 168643 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 167911 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 167911 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 167911 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 167911 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 167911 # number of overall hits -system.cpu2.icache.overall_hits::total 167911 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses -system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8088500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8088500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8088500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8088500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8088500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8088500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 168277 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 168277 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 168277 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 168277 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 168277 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 168277 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002175 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002175 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002175 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22099.726776 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22099.726776 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22099.726776 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22099.726776 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.writebacks::writebacks 280 # number of writebacks -system.cpu2.icache.writebacks::total 280 # number of writebacks -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7722500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7722500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7722500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7722500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7722500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7722500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21099.726776 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency -system.cpu3.numCycles 527131 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 165809 # Number of instructions committed -system.cpu3.committedOps 165809 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 112442 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 30690 # number of instructions that are conditional controls -system.cpu3.num_int_insts 112442 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 289238 # number of times the integer registers were read -system.cpu3.num_int_register_writes 110642 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 57921 # number of memory refs -system.cpu3.num_load_insts 41890 # Number of load instructions -system.cpu3.num_store_insts 16031 # Number of store instructions -system.cpu3.num_idle_cycles 74358.001718 # Number of idle cycles -system.cpu3.num_busy_cycles 452772.998282 # Number of busy cycles -system.cpu3.not_idle_fraction 0.858938 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.141062 # Percentage of idle cycles -system.cpu3.Branches 32344 # Number of branches fetched -system.cpu3.op_class::No_OpClass 23127 13.95% 13.95% # Class of executed instruction -system.cpu3.op_class::IntAlu 75479 45.51% 59.46% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.46% # Class of executed instruction -system.cpu3.op_class::MemRead 51204 30.88% 90.33% # Class of executed instruction -system.cpu3.op_class::MemWrite 16031 9.67% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 165841 # Class of executed instruction -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.704074 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 34341 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1184.172414 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.704074 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050203 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050203 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 231895 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 231895 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 41733 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41733 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 15853 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 15853 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 57586 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 57586 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 57586 # number of overall hits -system.cpu3.dcache.overall_hits::total 57586 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 150 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 150 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses -system.cpu3.dcache.overall_misses::total 259 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1542500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 1542500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1810500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1810500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 250500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 250500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 3353000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 3353000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 3353000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 3353000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41883 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41883 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 15962 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 15962 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 57845 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 57845 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 57845 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 57845 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003581 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003581 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006829 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.006829 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835821 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004477 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004477 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004477 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004477 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 10283.333333 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 10283.333333 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16610.091743 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 16610.091743 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4473.214286 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4473.214286 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 12945.945946 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 12945.945946 # average overall miss latency -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 150 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 259 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 259 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1392500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1392500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1701500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1701500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 194500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 194500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3094000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3094000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3094000 # 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mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9283.333333 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9283.333333 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15610.091743 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15610.091743 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3473.214286 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3473.214286 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946 # 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Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 166209 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 166209 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 165475 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 165475 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 165475 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 165475 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 165475 # number of overall hits -system.cpu3.icache.overall_hits::total 165475 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 367 # 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average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14914.168937 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14914.168937 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.writebacks::writebacks 281 # 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Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.227742 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.835119 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 46.668024 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 6.066881 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.961095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.822991 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003520 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005298 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 19669 # Number of tag accesses -system.l2c.tags.data_accesses 19669 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 9 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 26 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 182 # 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number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1218 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 14 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3.data 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 78 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 23 # 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mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.974359 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.013624 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.226054 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.636364 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.730769 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013624 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.027322 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.147541 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.846154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013624 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19035.714286 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19357.142857 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19214.285714 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 19050 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19131.578947 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49515.151515 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 49821.428571 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50333.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 49714.285714 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 49651.408451 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50050 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49500 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49539.548023 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50050 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 49800 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50068.181818 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50050 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49800 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency -system.membus.trans_dist::ReadResp 430 # Transaction distribution -system.membus.trans_dist::UpgradeReq 271 # Transaction distribution -system.membus.trans_dist::ReadExReq 208 # Transaction distribution -system.membus.trans_dist::ReadExResp 142 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1481 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1481 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 261 # Total snoops (count) -system.membus.snoop_fanout::samples 915 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 915 # Request fanout histogram -system.membus.reqLayer0.occupancy 685132 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 3976 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1120 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1854 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 2221 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 424 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 424 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 655 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5866 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1028 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2918 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.265250 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.153418 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1002 34.34% 34.34% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 794 27.21% 61.55% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 468 16.04% 77.59% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 654 22.41% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2918 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3048992 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 700999 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 500989 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 435970 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 554485 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 441968 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 552992 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 411482 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index 7c2d41959..b7f3d9217 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.010022 # Nu sim_ticks 10021833 # Number of ticks simulated final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 141404 # Simulator tick rate (ticks/s) -host_mem_usage 425972 # Number of bytes of host memory used -host_seconds 70.87 # Real time elapsed on the host +host_tick_rate 162199 # Simulator tick rate (ticks/s) +host_mem_usage 417868 # Number of bytes of host memory used +host_seconds 61.79 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 10214a209..b8eac504c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007437 # Nu sim_ticks 7436579 # Number of ticks simulated final_tick 7436579 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 32317 # Simulator tick rate (ticks/s) -host_mem_usage 403848 # Number of bytes of host memory used -host_seconds 230.12 # Real time elapsed on the host +host_tick_rate 74529 # Simulator tick rate (ticks/s) +host_mem_usage 420508 # Number of bytes of host memory used +host_seconds 99.78 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39411840 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 8f87abafb..d149e53a7 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.006099 # Nu sim_ticks 6099346 # Number of ticks simulated final_tick 6099346 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 34740 # Simulator tick rate (ticks/s) -host_mem_usage 404344 # Number of bytes of host memory used -host_seconds 175.57 # Real time elapsed on the host +host_tick_rate 81040 # Simulator tick rate (ticks/s) +host_mem_usage 421980 # Number of bytes of host memory used +host_seconds 75.26 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39765376 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 02b6c9c1b..2391b011d 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.004723 # Nu sim_ticks 4722948 # Number of ticks simulated final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 43612 # Simulator tick rate (ticks/s) -host_mem_usage 429416 # Number of bytes of host memory used -host_seconds 108.30 # Real time elapsed on the host +host_tick_rate 53510 # Simulator tick rate (ticks/s) +host_mem_usage 421672 # Number of bytes of host memory used +host_seconds 88.26 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index ac17b1f35..87ea51c89 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007679 # Nu sim_ticks 7678882 # Number of ticks simulated final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 131227 # Simulator tick rate (ticks/s) -host_mem_usage 425824 # Number of bytes of host memory used -host_seconds 58.52 # Real time elapsed on the host +host_tick_rate 120821 # Simulator tick rate (ticks/s) +host_mem_usage 418672 # Number of bytes of host memory used +host_seconds 63.56 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 30ddbd92e..f24c7c909 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000502 # Nu sim_ticks 501584000 # Number of ticks simulated final_tick 501584000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 112049096 # Simulator tick rate (ticks/s) -host_mem_usage 235328 # Number of bytes of host memory used -host_seconds 4.48 # Real time elapsed on the host +host_tick_rate 82658959 # Simulator tick rate (ticks/s) +host_mem_usage 231728 # Number of bytes of host memory used +host_seconds 6.07 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0 77173 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index 35b91ee55..b05d177c6 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000500 # Nu sim_ticks 500337000 # Number of ticks simulated final_tick 500337000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 94931123 # Simulator tick rate (ticks/s) -host_mem_usage 234040 # Number of bytes of host memory used -host_seconds 5.27 # Real time elapsed on the host +host_tick_rate 90464630 # Simulator tick rate (ticks/s) +host_mem_usage 231728 # Number of bytes of host memory used +host_seconds 5.53 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0 75919 # Number of bytes read from this memory diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index 381569cba..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,152 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.044221 # Number of seconds simulated -sim_ticks 44221003000 # Number of ticks simulated -final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1271644 # Simulator instruction rate (inst/s) -host_op_rate 1271643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 636550745 # Simulator tick rate (ticks/s) -host_mem_usage 229384 # Number of bytes of host memory used -host_seconds 69.47 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory -system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory -system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438073 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442007 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 88442007 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 88442007 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction -system.membus.trans_dist::ReadReq 108714711 # Transaction distribution -system.membus.trans_dist::ReadResp 108714711 # Transaction distribution -system.membus.trans_dist::WriteReq 14613377 # Transaction distribution -system.membus.trans_dist::WriteResp 14613377 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 123328088 # Request fanout histogram -system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 34890015 28.29% 28.29% # Request fanout histogram -system.membus.snoop_fanout::1 88438073 71.71% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 123328088 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index e76d0cce6..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,546 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.134742 # Number of seconds simulated -sim_ticks 134741611500 # Number of ticks simulated -final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1303886 # Simulator instruction rate (inst/s) -host_op_rate 1303885 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1988750581 # Simulator tick rate (ticks/s) -host_mem_usage 260188 # Number of bytes of host memory used -host_seconds 67.75 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 367360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10138112 # Number of bytes read from this memory -system.physmem.bytes_read::total 10505472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 367360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 367360 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7320448 # Number of bytes written to this memory -system.physmem.bytes_written::total 7320448 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158408 # Number of read requests responded to by this memory -system.physmem.num_reads::total 164148 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114382 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114382 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2726403 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75241137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 77967540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2726403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2726403 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54329527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54329527 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54329527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2726403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75241137 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 132297067 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438074 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442008 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 269483223 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 269483223 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366786 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction -system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.397630 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 983457500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.397630 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995703 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995703 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3595 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits -system.cpu.dcache.overall_hits::total 34685671 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses -system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2138978000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2138978000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8279807000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8279807000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10418785000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10418785000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10418785000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10418785000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35200.243557 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35200.243557 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57667.657998 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57667.657998 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50986.498258 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50986.498258 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50986.498258 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168278 # number of writebacks -system.cpu.dcache.writebacks::total 168278 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2078212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2078212000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8136229000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8136229000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10214441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10214441000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10214441000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10214441000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34200.243557 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34200.243557 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56667.657998 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56667.657998 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258 # average overall mshr miss latency -system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1870.507754 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1870.507754 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.913334 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.913334 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses -system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits -system.cpu.icache.overall_hits::total 88361638 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses -system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1275518500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1275518500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1275518500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1275518500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1275518500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1275518500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16687.405149 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16687.405149 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16687.405149 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16687.405149 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16687.405149 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 74391 # number of writebacks -system.cpu.icache.writebacks::total 74391 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1199082500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1199082500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1199082500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1199082500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1199082500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1199082500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15687.405149 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15687.405149 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 131998 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30708.485304 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 247404 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164074 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.507881 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27397.900187 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1667.759999 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1642.825119 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.836118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.050896 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.937149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 731 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9441 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21639 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 122 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4751004 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4751004 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 168278 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168278 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 74391 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12696 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12696 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 70696 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 70696 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33240 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 33240 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 70696 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 45936 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 116632 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 70696 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 45936 # number of overall hits -system.cpu.l2cache.overall_hits::total 116632 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130882 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130882 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 5740 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 5740 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27526 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27526 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5740 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158408 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 164148 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5740 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158408 # number of overall misses -system.cpu.l2cache.overall_misses::total 164148 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7787542500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7787542500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 341866000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 341866000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1637990000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1637990000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 341866000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9425532500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9767398500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 341866000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9425532500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9767398500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168278 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168278 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 74391 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 74391 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 76436 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 76436 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 60766 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 60766 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911574 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911574 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.075096 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.075096 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.452984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.452984 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.075096 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775203 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.584614 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.075096 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775203 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.584614 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.485170 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.485170 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59558.536585 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59558.536585 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59507.011553 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59507.011553 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59503.609547 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59558.536585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.619236 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59503.609547 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 114382 # number of writebacks -system.cpu.l2cache.writebacks::total 114382 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 105 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 105 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5740 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5740 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27526 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27526 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5740 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158408 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 164148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5740 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158408 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 164148 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6478722500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6478722500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 284466000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 284466000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1362730000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1362730000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 284466000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7841452500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8125918500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 284466000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7841452500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8125918500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911574 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911574 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075096 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452984 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.584614 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075096 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775203 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.584614 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.485170 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.485170 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49558.536585 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49558.536585 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49507.011553 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49507.011553 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3875 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3875 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 282660 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 49586 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 131998 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 408903 99.06% 99.06% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3875 0.94% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 412778 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 520378500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 33266 # Transaction distribution -system.membus.trans_dist::WritebackDirty 114382 # Transaction distribution -system.membus.trans_dist::CleanEvict 13845 # Transaction distribution -system.membus.trans_dist::ReadExReq 130882 # Transaction distribution -system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33266 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 456523 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 456523 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 292375 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292375 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292375 # Request fanout histogram -system.membus.reqLayer0.occupancy 750324500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 820740000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index bcdad61b2..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,243 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.048960 # Number of seconds simulated -sim_ticks 48960022500 # Number of ticks simulated -final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 991674 # Simulator instruction rate (inst/s) -host_op_rate 1268214 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 684673258 # Simulator tick rate (ticks/s) -host_mem_usage 242788 # Number of bytes of host memory used -host_seconds 71.51 # Real time elapsed on the host -sim_insts 70913204 # Number of instructions simulated -sim_ops 90688159 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 312580364 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory -system.physmem.bytes_read::total 419153709 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 312580364 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 312580364 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory -system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 78145091 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory -system.physmem.num_reads::total 101064821 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory -system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6384399925 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2176742157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8561142083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6384399925 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6384399925 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1606621218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1606621218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6384399925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3783363376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10167763301 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 97920046 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70913204 # Number of instructions committed -system.cpu.committedOps 90688159 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528528 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141479386 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 266608097 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 97920045.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741468 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690106 # Class of executed instruction -system.membus.trans_dist::ReadReq 100925158 # Transaction distribution -system.membus.trans_dist::ReadResp 100941077 # Transaction distribution -system.membus.trans_dist::WriteReq 19849901 # Transaction distribution -system.membus.trans_dist::WriteResp 19849901 # Transaction distribution -system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution -system.membus.trans_dist::SoftPFResp 123744 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution -system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290182 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861282 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 120930641 # Request fanout histogram -system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::1 78145091 64.62% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 120930641 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 2518d4d22..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,662 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.128077 # Number of seconds simulated -sim_ticks 128076834500 # Number of ticks simulated -final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 775777 # Simulator instruction rate (inst/s) -host_op_rate 990450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1411878896 # Simulator tick rate (ticks/s) -host_mem_usage 277764 # Number of bytes of host memory used -host_seconds 90.71 # Real time elapsed on the host -sim_insts 70373651 # Number of instructions simulated -sim_ops 89847385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 233152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7925248 # Number of bytes read from this memory -system.physmem.bytes_read::total 8158400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 233152 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 233152 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5513600 # Number of bytes written to this memory -system.physmem.bytes_written::total 5513600 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123832 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127475 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 86150 # Number of write requests responded to by this memory -system.physmem.num_writes::total 86150 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1820407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 61878856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 63699263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1820407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1820407 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 43049159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 43049159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 43049159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1820407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 61878856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106748422 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 256153669 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373651 # Number of instructions committed -system.cpu.committedOps 89847385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 81528528 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses -system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 9253630 # number of instructions that are conditional controls -system.cpu.num_int_insts 81528528 # number of integer instructions -system.cpu.num_fp_insts 56 # number of float instructions -system.cpu.num_int_register_reads 141328550 # number of times the integer registers were read -system.cpu.num_int_register_writes 53916335 # number of times the integer registers were written -system.cpu.num_fp_register_reads 36 # number of times the floating registers were read -system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 334802072 # number of times the CC registers were read -system.cpu.num_cc_register_writes 36877111 # number of times the CC registers were written -system.cpu.num_mem_refs 43422001 # number of memory refs -system.cpu.num_load_insts 22866262 # Number of load instructions -system.cpu.num_store_insts 20555739 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 256153668.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741468 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187979 52.03% 52.03% # Class of executed instruction -system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction -system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction -system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690106 # Class of executed instruction -system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4075.927155 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42601677 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.263810 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1109655500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4075.927155 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995099 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995099 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 787 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3263 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22743361 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22743361 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83609 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83609 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42486230 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42486230 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42569839 # number of overall hits -system.cpu.dcache.overall_hits::total 42569839 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 36706 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 36706 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40135 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40135 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 143738 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 143738 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 183873 # number of overall misses -system.cpu.dcache.overall_misses::total 183873 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 577584000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 577584000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6405138000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6405138000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6982722000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6982722000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6982722000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6982722000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001611 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001611 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324339 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324339 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003372 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003372 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004301 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004301 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15735.411104 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15735.411104 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59843.205770 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59843.205770 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48579.512725 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48579.512725 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37975.787636 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37975.787636 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 128175 # number of writebacks -system.cpu.dcache.writebacks::total 128175 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7598 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7598 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7598 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7598 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7598 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7598 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 495022500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 495022500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6298106000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6298106000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1201109000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1201109000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793128500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6793128500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7994237500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7994237500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17006.407173 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17006.407173 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58843.205770 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58843.205770 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50344.077458 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50344.077458 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933 # average overall mshr miss latency -system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1732.356634 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78126184 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4131.911572 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1732.356634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.845877 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.845877 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156309092 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156309092 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78126184 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126184 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126184 # 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number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 426200500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 426200500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145092 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145092 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145092 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145092 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145092 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22540.749947 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22540.749947 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22540.749947 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22540.749947 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22540.749947 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16890 # number of writebacks -system.cpu.icache.writebacks::total 16890 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 407292500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 407292500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 407292500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 407292500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 407292500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 407292500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21540.749947 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21540.749947 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 95333 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30336.891531 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 114380 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126455 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.904511 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27758.605525 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1088.258663 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1490.027343 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.847125 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.033211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.045472 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.925808 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1225 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13921 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15196 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 624 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949768 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3017503 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3017503 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 128175 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 128175 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 15790 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 15790 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4751 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4751 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 15265 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 15265 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31415 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 31415 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 15265 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36166 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 51431 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 15265 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36166 # number of overall hits -system.cpu.l2cache.overall_hits::total 51431 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3643 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3643 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21551 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21551 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123832 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 127475 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123832 # number of overall misses -system.cpu.l2cache.overall_misses::total 127475 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6087670500 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7589370000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 128175 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 128175 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 15790 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 15790 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107032 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 18908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 18908 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 52966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 52966 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 18908 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 159998 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 178906 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 18908 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 159998 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 178906 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955611 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955611 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.192670 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.192670 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.406884 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.406884 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.192670 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.773960 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.712525 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.192670 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.773960 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.712525 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59519.074901 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59519.074901 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59639.171013 # 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number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 86150 # number of writebacks -system.cpu.l2cache.writebacks::total 86150 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 104 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 104 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3643 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3643 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21551 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21551 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3643 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123832 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 127475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3643 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123832 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 127475 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5064860500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5064860500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 180835500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 180835500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1068924000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1068924000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180835500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6133784500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6314620000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180835500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6133784500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6314620000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.192670 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406884 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406884 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.712525 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.192670 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773960 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.712525 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49519.074901 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49519.074901 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49639.171013 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49639.171013 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49599.740151 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49599.740151 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49639.171013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49533.113412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49536.144342 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 351698 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 172817 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3696 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3119 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 95333 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.156979 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 267399 97.51% 97.51% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 6810 2.48% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 274239 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 320914000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 25194 # Transaction distribution -system.membus.trans_dist::WritebackDirty 86150 # Transaction distribution -system.membus.trans_dist::CleanEvict 6168 # Transaction distribution -system.membus.trans_dist::ReadExReq 102281 # Transaction distribution -system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 25194 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 347268 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 347268 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13672000 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13672000 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 219817 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 219817 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 219817 # Request fanout histogram -system.membus.reqLayer0.occupancy 568080092 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 637375000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 3ed030f96..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -1,124 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.068149 # Number of seconds simulated -sim_ticks 68148677000 # Number of ticks simulated -final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1843276 # Simulator instruction rate (inst/s) -host_op_rate 1867142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 934655607 # Simulator tick rate (ticks/s) -host_mem_usage 225200 # Number of bytes of host memory used -host_seconds 72.91 # Real time elapsed on the host -sim_insts 134398959 # Number of instructions simulated -sim_ops 136139187 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 538214320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory -system.physmem.bytes_read::total 685773680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 538214320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 538214320 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 89882950 # Number of bytes written to this memory -system.physmem.bytes_written::total 89882950 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 134553580 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 37231300 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171784880 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 20864304 # Number of write requests responded to by this memory -system.physmem.num_writes::total 20864304 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 15916 # Number of other requests responded to by this memory -system.physmem.num_other::total 15916 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7897648842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2165256414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10062905256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7897648842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7897648842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1318924357 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1318924357 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7897648842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3484180771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11381829614 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 136297355 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398959 # Number of instructions committed -system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses -system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187757 # number of integer instructions -system.cpu.num_fp_insts 2326976 # number of float instructions -system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147731 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160261 # number of memory refs -system.cpu.num_load_insts 37275864 # Number of load instructions -system.cpu.num_store_insts 20884397 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 136297354.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719094 # Number of branches fetched -system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293808 # Class of executed instruction -system.membus.trans_dist::ReadReq 171784880 # Transaction distribution -system.membus.trans_dist::ReadResp 171784880 # Transaction distribution -system.membus.trans_dist::WriteReq 20864304 # Transaction distribution -system.membus.trans_dist::WriteResp 20864304 # Transaction distribution -system.membus.trans_dist::SwapReq 15916 # Transaction distribution -system.membus.trans_dist::SwapResp 15916 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 269107160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 116223040 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 385330200 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 192665100 # Request fanout histogram -system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 58111520 30.16% 30.16% # Request fanout histogram -system.membus.snoop_fanout::1 134553580 69.84% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 192665100 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 97bc2f274..e69de29bb 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,535 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.203116 # Number of seconds simulated -sim_ticks 203115946500 # Number of ticks simulated -final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1277402 # Simulator instruction rate (inst/s) -host_op_rate 1293942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1930526358 # Simulator tick rate (ticks/s) -host_mem_usage 259920 # Number of bytes of host memory used -host_seconds 105.21 # Real time elapsed on the host -sim_insts 134398959 # Number of instructions simulated -sim_ops 136139187 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 525056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7828352 # Number of bytes read from this memory -system.physmem.bytes_read::total 8353408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 525056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 525056 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5457280 # Number of bytes written to this memory -system.physmem.bytes_written::total 5457280 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122318 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130522 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 85270 # Number of write requests responded to by this memory -system.physmem.num_writes::total 85270 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2585006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38541297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41126303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2585006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2585006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26867807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26867807 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26867807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2585006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38541297 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67994110 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 406231893 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 134398959 # Number of instructions committed -system.cpu.committedOps 136139187 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 115187757 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2326976 # Number of float alu accesses -system.cpu.num_func_calls 1709332 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8898968 # number of instructions that are conditional controls -system.cpu.num_int_insts 115187757 # number of integer instructions -system.cpu.num_fp_insts 2326976 # number of float instructions -system.cpu.num_int_register_reads 263032419 # number of times the integer registers were read -system.cpu.num_int_register_writes 113147730 # number of times the integer registers were written -system.cpu.num_fp_register_reads 4725606 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1150968 # number of times the floating registers were written -system.cpu.num_mem_refs 58160261 # number of memory refs -system.cpu.num_load_insts 37275864 # Number of load instructions -system.cpu.num_store_insts 20884397 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 406231892.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12719094 # Number of branches fetched -system.cpu.op_class::No_OpClass 11445042 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 66342067 48.68% 57.07% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 57.07% # Class of executed instruction -system.cpu.op_class::FloatAdd 325584 0.24% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.31% # Class of executed instruction -system.cpu.op_class::MemRead 37296718 27.36% 84.68% # Class of executed instruction -system.cpu.op_class::MemWrite 20884397 15.32% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 136293808 # Class of executed instruction -system.cpu.dcache.tags.replacements 146583 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.268923 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 57960841 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 150679 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 384.664359 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 822359500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.268923 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997868 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997868 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 474 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3586 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 116373719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 116373719 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37185800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37185800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 57944940 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 57944940 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 57944940 # number of overall hits -system.cpu.dcache.overall_hits::total 57944940 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 45500 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 45500 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 150664 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 150664 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 150664 # number of overall misses -system.cpu.dcache.overall_misses::total 150664 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1623315500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1623315500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6329554000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6329554000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 441000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 441000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7952869500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7952869500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7952869500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7952869500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35677.263736 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35677.263736 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60187.459587 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60187.459587 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 29400 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 29400 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52785.466336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52785.466336 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52785.466336 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 123865 # number of writebacks -system.cpu.dcache.writebacks::total 123865 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45500 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 45500 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 150664 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 150664 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 150664 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 150664 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1577815500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1577815500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6224390000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6224390000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 426000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 426000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7802205500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7802205500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7802205500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7802205500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34677.263736 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34677.263736 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59187.459587 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59187.459587 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 28400 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 28400 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336 # average overall mshr miss latency -system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.181265 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 134366557 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 718.445531 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 144582800500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.181265 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.978604 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.978604 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 269294186 # Number of tag accesses -system.cpu.icache.tags.data_accesses 269294186 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 134366557 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 134366557 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 134366557 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 134366557 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 134366557 # number of overall hits -system.cpu.icache.overall_hits::total 134366557 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 187024 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses -system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2835239000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2835239000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2835239000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2835239000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2835239000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2835239000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 134553581 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 134553581 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 134553581 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 134553581 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 134553581 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 134553581 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001390 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15159.760245 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15159.760245 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15159.760245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15159.760245 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15159.760245 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 184976 # number of writebacks -system.cpu.icache.writebacks::total 184976 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187024 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 187024 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2648215000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2648215000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2648215000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2648215000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2648215000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2648215000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14159.760245 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14159.760245 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 99022 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30843.699683 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 433832 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130065 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.335501 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26289.169168 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3249.863620 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1304.666895 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.802282 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.099178 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.039815 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941275 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31043 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 566 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11257 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18470 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 557 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.947357 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5588812 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5588812 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 123865 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 123865 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 184923 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 184923 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3915 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3915 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 178820 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 178820 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 24446 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 24446 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 178820 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 28361 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 207181 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 178820 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 28361 # number of overall hits -system.cpu.l2cache.overall_hits::total 207181 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 101264 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101264 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 8204 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21054 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 21054 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 122318 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 130522 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8204 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 122318 # number of overall misses -system.cpu.l2cache.overall_misses::total 130522 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6025890000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6025890000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 488461500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 488461500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1252834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1252834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 488461500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7278724000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7767185500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 488461500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7278724000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7767185500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 123865 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 123865 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 184923 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 184923 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 105179 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187024 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 187024 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 45500 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 45500 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 187024 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 150679 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 337703 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 187024 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 150679 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 337703 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.962778 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.962778 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043866 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043866 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.462725 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.462725 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043866 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.811779 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.386499 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043866 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.811779 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.386499 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59506.734871 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59506.734871 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59539.431984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59539.431984 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59505.747126 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59505.747126 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59508.630729 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59539.431984 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59506.564856 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59508.630729 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 85270 # number of writebacks -system.cpu.l2cache.writebacks::total 85270 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101264 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101264 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8204 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8204 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21054 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21054 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8204 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122318 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 130522 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8204 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122318 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 130522 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 406421500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 406421500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1042294000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1042294000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 406421500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6055544000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6461965500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 406421500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6055544000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6461965500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962778 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962778 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043866 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462725 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462725 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.386499 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043866 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811779 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.386499 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49506.734871 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49506.734871 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49539.431984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49539.431984 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49505.747126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49505.747126 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49539.431984 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49506.564856 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49508.630729 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 669262 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 331559 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 66 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3547 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 232524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36470 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 45500 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447941 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1006965 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 99022 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 433112 99.17% 99.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3613 0.83% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 436725 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 643472000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 226018500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 29258 # Transaction distribution -system.membus.trans_dist::WritebackDirty 85270 # Transaction distribution -system.membus.trans_dist::CleanEvict 10301 # Transaction distribution -system.membus.trans_dist::ReadExReq 101264 # Transaction distribution -system.membus.trans_dist::ReadExResp 101264 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 29258 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 356615 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 356615 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 226093 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 226093 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 226093 # Request fanout histogram -system.membus.reqLayer0.occupancy 568574500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 652610000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt index 18987ac29..6e51bc804 100644 --- a/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt +++ b/tests/quick/se/51.memcheck/ref/null/none/memcheck/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.010000 # Nu sim_ticks 10000000000 # Number of ticks simulated final_tick 10000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 995173175 # Simulator tick rate (ticks/s) -host_mem_usage 1449604 # Number of bytes of host memory used -host_seconds 10.05 # Real time elapsed on the host +host_tick_rate 621801419 # Simulator tick rate (ticks/s) +host_mem_usage 1442452 # Number of bytes of host memory used +host_seconds 16.08 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::l0subsys0.tester0 2151552 # Number of bytes read from this memory diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt index 2da8cfc3e..bdf77ebe4 100644 --- a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000014 # Nu sim_ticks 14181 # Number of ticks simulated final_tick 14181 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 116506 # Simulator tick rate (ticks/s) -host_mem_usage 464616 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 154609 # Simulator tick rate (ticks/s) +host_mem_usage 480252 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::dir_cntrl0 16576 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index 5cadbdde3..16afa43a3 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000043 # Nu sim_ticks 43191 # Number of ticks simulated final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 428274 # Simulator tick rate (ticks/s) -host_mem_usage 410016 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 667875 # Simulator tick rate (ticks/s) +host_mem_usage 406088 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index 1db6620aa..75f44776f 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000054 # Nu sim_ticks 54211 # Number of ticks simulated final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 316777 # Simulator tick rate (ticks/s) -host_mem_usage 410608 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 538772 # Simulator tick rate (ticks/s) +host_mem_usage 406688 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index 851456fb6..f8400a6e4 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000050 # Nu sim_ticks 50141 # Number of ticks simulated final_tick 50141 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 395128 # Simulator tick rate (ticks/s) -host_mem_usage 389312 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 969830 # Simulator tick rate (ticks/s) +host_mem_usage 406616 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 50624 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 5a3d40466..c2eacbfda 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000030 # Nu sim_ticks 29561 # Number of ticks simulated final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 334780 # Simulator tick rate (ticks/s) -host_mem_usage 410240 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 593739 # Simulator tick rate (ticks/s) +host_mem_usage 406316 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index d1da3d54a..3208bfd4e 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000038 # Nu sim_ticks 37741 # Number of ticks simulated final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 544029 # Simulator tick rate (ticks/s) -host_mem_usage 408776 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 877206 # Simulator tick rate (ticks/s) +host_mem_usage 404076 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 14d004205..238ebf7d9 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 4618007467 # Simulator tick rate (ticks/s) -host_mem_usage 202228 # Number of bytes of host memory used -host_seconds 21.65 # Real time elapsed on the host +host_tick_rate 9064709748 # Simulator tick rate (ticks/s) +host_mem_usage 219696 # Number of bytes of host memory used +host_seconds 11.03 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt index 710d324a6..cbbc1075a 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 15880275218 # Simulator tick rate (ticks/s) -host_mem_usage 204660 # Number of bytes of host memory used -host_seconds 6.30 # Real time elapsed on the host +host_tick_rate 16220790107 # Simulator tick rate (ticks/s) +host_mem_usage 221740 # Number of bytes of host memory used +host_seconds 6.17 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 46baca50d..e69de29bb 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -1,152 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.045952 # Number of seconds simulated -sim_ticks 45951567500 # Number of ticks simulated -final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1065115 # Simulator instruction rate (inst/s) -host_op_rate 1065115 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 532557762 # Simulator tick rate (ticks/s) -host_mem_usage 224960 # Number of bytes of host memory used -host_seconds 86.28 # Real time elapsed on the host -sim_insts 91903056 # Number of instructions simulated -sim_ops 91903056 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory -system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory -system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory -system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory -system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.itb.fetch_hits 91903089 # ITB hits -system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 91903136 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 91903136 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 91903056 # Number of instructions committed -system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses -system.cpu.num_func_calls 2059216 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls -system.cpu.num_int_insts 79581109 # number of integer instructions -system.cpu.num_fp_insts 6862064 # number of float instructions -system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read -system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read -system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written -system.cpu.num_mem_refs 26497334 # number of memory refs -system.cpu.num_load_insts 19996208 # Number of load instructions -system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 91903136 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 10240685 # Number of branches fetched -system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction -system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction -system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction -system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction -system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction -system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91903089 # Class of executed instruction -system.membus.trans_dist::ReadReq 111899287 # Transaction distribution -system.membus.trans_dist::ReadResp 111899287 # Transaction distribution -system.membus.trans_dist::WriteReq 6501103 # Transaction distribution -system.membus.trans_dist::WriteResp 6501103 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 118400390 # Request fanout histogram -system.membus.snoop_fanout::mean 0.776206 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.416786 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 26497301 22.38% 22.38% # Request fanout histogram -system.membus.snoop_fanout::1 91903089 77.62% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 118400390 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index c2aa1fab9..e69de29bb 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,534 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.118763 # Number of seconds simulated -sim_ticks 118762761500 # Number of ticks simulated -final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1409040 # Simulator instruction rate (inst/s) -host_op_rate 1409039 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1820846467 # Simulator tick rate (ticks/s) -host_mem_usage 255756 # Number of bytes of host memory used -host_seconds 65.22 # Real time elapsed on the host -sim_insts 91903056 # Number of instructions simulated -sim_ops 91903056 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory -system.physmem.bytes_read::total 304960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155379 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2567808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.itb.fetch_hits 91903090 # ITB hits -system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 91903137 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237525523 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 91903056 # Number of instructions committed -system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses -system.cpu.num_func_calls 2059216 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls -system.cpu.num_int_insts 79581109 # number of integer instructions -system.cpu.num_fp_insts 6862064 # number of float instructions -system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read -system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read -system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written -system.cpu.num_mem_refs 26497334 # number of memory refs -system.cpu.num_load_insts 19996208 # Number of load instructions -system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237525523 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 10240685 # Number of branches fetched -system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction -system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction -system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction -system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction -system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::MemRead 19996208 21.76% 92.93% # Class of executed instruction -system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91903089 # Class of executed instruction -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.946319 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352038 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352038 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 491 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits -system.cpu.dcache.overall_hits::total 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses -system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26856500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26856500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 107103000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 107103000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133959500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133959500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133959500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133959500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56540 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56540 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61271.739130 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61271.739130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60260.683761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60260.683761 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60260.683761 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26381500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26381500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105355000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 105355000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131736500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 131736500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 131736500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 131736500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55540 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55540 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60271.739130 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60271.739130 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency -system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1417.953327 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.692360 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.692360 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 585 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 953 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses -system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits -system.cpu.icache.overall_hits::total 91894580 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses -system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 239145000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 239145000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 239145000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 239145000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 239145000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 239145000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28101.645123 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28101.645123 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28101.645123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28101.645123 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28101.645123 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6681 # number of writebacks -system.cpu.icache.writebacks::total 6681 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 230635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 230635000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 230635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 230635000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 230635000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 230635000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27101.645123 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27101.645123 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.080733 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.795341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.894227 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.233582 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052029 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.010719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.063291 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6681 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5889 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 5889 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 5968 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2621 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2621 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 422 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 422 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2621 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2144 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4765 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses -system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 102460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155964000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 155964000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 25110500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 25110500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 155964000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 127570500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 283534500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 155964000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 127570500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 283534500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 6681 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 6681 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8510 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 8510 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 475 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 475 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8510 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2223 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 10733 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8510 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2223 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 10733 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985126 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.307991 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.307991 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.888421 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.888421 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.307991 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964462 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.443958 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.580720 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.580720 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59505.532240 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59505.532240 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59503.554502 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59503.554502 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59503.567681 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59505.532240 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.166045 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59503.567681 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2621 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2621 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 422 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 422 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2621 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2144 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4765 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129754000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129754000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 20890500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 20890500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129754000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 106130500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 235884500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129754000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 106130500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 235884500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.307991 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888421 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.580720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.580720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49505.532240 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49505.532240 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49503.554502 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49503.554502 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49505.532240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.166045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.567681 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 8510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 475 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 28304 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 972224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1121344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10733 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10733 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10733 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15573500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3043 # Transaction distribution -system.membus.trans_dist::ReadExReq 1722 # Transaction distribution -system.membus.trans_dist::ReadExResp 1722 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3043 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4765 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4765 # Request fanout histogram -system.membus.reqLayer0.occupancy 4782000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 23825000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 177b96346..e69de29bb 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,243 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.099596 # Number of seconds simulated -sim_ticks 99596491500 # Number of ticks simulated -final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 695621 # Simulator instruction rate (inst/s) -host_op_rate 733297 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 402056906 # Simulator tick rate (ticks/s) -host_mem_usage 242228 # Number of bytes of host memory used -host_seconds 247.72 # Real time elapsed on the host -sim_insts 172317410 # Number of instructions simulated -sim_ops 181650342 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory -system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 759440208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 759440208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory -system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 189860052 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217637773 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory -system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7625170290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1109814807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8734985097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7625170290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7625170290 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 454362792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 454362792 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 199192984 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 172317410 # Number of instructions committed -system.cpu.committedOps 181650342 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls -system.cpu.num_int_insts 143085668 # number of integer instructions -system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 241970171 # number of times the integer registers were read -system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written -system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_cc_register_reads 543309970 # number of times the CC registers were read -system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written -system.cpu.num_mem_refs 40540779 # number of memory refs -system.cpu.num_load_insts 27896144 # Number of load instructions -system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 199192983.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 40300312 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction -system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction -system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 181650743 # Class of executed instruction -system.membus.trans_dist::ReadReq 217614903 # Transaction distribution -system.membus.trans_dist::ReadResp 217637310 # Transaction distribution -system.membus.trans_dist::WriteReq 12364287 # Transaction distribution -system.membus.trans_dist::WriteResp 12364287 # Transaction distribution -system.membus.trans_dist::SoftPFReq 463 # Transaction distribution -system.membus.trans_dist::SoftPFResp 463 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution -system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460048934 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 230024467 # Request fanout histogram -system.membus.snoop_fanout::mean 0.825391 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::1 189860052 82.54% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 230024467 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index d21481ee3..e69de29bb 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,644 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.230198 # Number of seconds simulated -sim_ticks 230197694500 # Number of ticks simulated -final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 927075 # Simulator instruction rate (inst/s) -host_op_rate 977372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1241896591 # Simulator tick rate (ticks/s) -host_mem_usage 272260 # Number of bytes of host memory used -host_seconds 185.36 # Real time elapsed on the host -sim_insts 171842484 # Number of instructions simulated -sim_ops 181165371 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory -system.physmem.bytes_read::total 220992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460395389 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 171842484 # Number of instructions committed -system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses -system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls -system.cpu.num_int_insts 143085668 # number of integer instructions -system.cpu.num_fp_insts 1752310 # number of float instructions -system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read -system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written -system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read -system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written -system.cpu.num_mem_refs 40540779 # number of memory refs -system.cpu.num_load_insts 27896144 # Number of load instructions -system.cpu.num_store_insts 12644635 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 40300312 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction -system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction -system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction -system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 181650743 # Class of executed instruction -system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits -system.cpu.dcache.overall_hits::total 40117812 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses -system.cpu.dcache.overall_misses::total 1789 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency -system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses -system.cpu.icache.tags.data_accesses 379723157 # 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number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 189860053 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 189860053 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 189860053 # 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average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1506 # number of writebacks -system.cpu.icache.writebacks::total 1506 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # 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mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 16 # 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miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.917271 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.917271 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # 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number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # 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mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11226 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 407168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.179882 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4678 96.65% 96.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 162 3.35% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 2361 # Transaction distribution -system.membus.trans_dist::ReadExReq 1092 # Transaction distribution -system.membus.trans_dist::ReadExResp 1092 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 2361 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3453 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3453 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3601500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 17265000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index cdb442c20..e69de29bb 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -1,124 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.096723 # Number of seconds simulated -sim_ticks 96722945000 # Number of ticks simulated -final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 966666 # Simulator instruction rate (inst/s) -host_op_rate 966667 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 483336155 # Simulator tick rate (ticks/s) -host_mem_usage 225024 # Number of bytes of host memory used -host_seconds 200.12 # Real time elapsed on the host -sim_insts 193444518 # Number of instructions simulated -sim_ops 193444756 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory -system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory -system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory -system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory -system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory -system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory -system.physmem.num_other::total 22406 # Number of other requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 193445891 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444518 # Number of instructions committed -system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses -system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974806 # number of integer instructions -system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733958 # number of memory refs -system.cpu.num_load_insts 57735091 # Number of load instructions -system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 193445890.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 15132745 # Number of branches fetched -system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction -system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction -system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 193445773 # Class of executed instruction -system.membus.trans_dist::ReadReq 251180603 # Transaction distribution -system.membus.trans_dist::ReadResp 251180603 # Transaction distribution -system.membus.trans_dist::WriteReq 18976439 # Transaction distribution -system.membus.trans_dist::WriteResp 18976439 # Transaction distribution -system.membus.trans_dist::SwapReq 22406 # Transaction distribution -system.membus.trans_dist::SwapResp 22406 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 270179448 # Request fanout histogram -system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram -system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 270179448 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index c87fb96c4..e69de29bb 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,515 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.270600 # Number of seconds simulated -sim_ticks 270599529500 # Number of ticks simulated -final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1248385 # Simulator instruction rate (inst/s) -host_op_rate 1248386 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1746300725 # Simulator tick rate (ticks/s) -host_mem_usage 255364 # Number of bytes of host memory used -host_seconds 154.96 # Real time elapsed on the host -sim_insts 193444518 # Number of instructions simulated -sim_ops 193444756 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory -system.physmem.bytes_read::total 331072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541199059 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 193444518 # Number of instructions committed -system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses -system.cpu.num_func_calls 1957920 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls -system.cpu.num_int_insts 167974806 # number of integer instructions -system.cpu.num_fp_insts 1970372 # number of float instructions -system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read -system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written -system.cpu.num_mem_refs 76733958 # number of memory refs -system.cpu.num_load_insts 57735091 # Number of load instructions -system.cpu.num_store_insts 18998867 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 15132745 # Number of branches fetched -system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction -system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction -system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction -system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction -system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 193445773 # Class of executed instruction -system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits -system.cpu.dcache.overall_hits::total 76709932 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses -system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2 # number of writebacks -system.cpu.dcache.writebacks::total 2 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30379500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30379500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 65698000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 65698000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 61000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 61000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 96077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 96077500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 96077500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 96077500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61003.012048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61003.012048 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000.928505 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000.928505 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 61000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 61000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency -system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.528232 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.777113 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.777113 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses -system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 193433248 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 193433248 # number of overall hits -system.cpu.icache.overall_hits::total 193433248 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses -system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 336231000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 336231000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 336231000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 336231000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 336231000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 336231000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 193445536 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 193445536 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 193445536 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000064 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27362.548828 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27362.548828 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27362.548828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27362.548828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27362.548828 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10362 # number of writebacks -system.cpu.icache.writebacks::total 10362 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323943000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 323943000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323943000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 323943000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323943000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 323943000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26362.548828 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26362.548828 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.650476 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.000456 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.203530 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 403.042121 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069434 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.081734 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10362 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8691 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8691 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8691 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8691 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8691 # number of overall hits -system.cpu.l2cache.overall_hits::total 8691 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1078 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1078 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3597 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3597 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 498 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 498 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3597 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1576 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5173 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses -system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64142000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64142000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 214049500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 214049500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29632000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 29632000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 214049500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 93774000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 307823500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 214049500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 93774000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 307823500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10362 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10362 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1078 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1078 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12288 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 12288 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 498 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 498 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12288 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1576 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13864 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12288 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1576 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13864 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.292725 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.292725 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.292725 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.373125 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.927644 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.927644 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59507.784265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59507.784265 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59502.008032 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59502.008032 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 4095 # Transaction distribution -system.membus.trans_dist::ReadExReq 1078 # Transaction distribution -system.membus.trans_dist::ReadExResp 1078 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5173 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5173 # Request fanout histogram -system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 5a46e9bad..e69de29bb 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -1,127 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.131393 # Number of seconds simulated -sim_ticks 131393279000 # Number of ticks simulated -final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 550181 # Simulator instruction rate (inst/s) -host_op_rate 922154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 547357033 # Simulator tick rate (ticks/s) -host_mem_usage 269224 # Number of bytes of host memory used -host_seconds 240.05 # Real time elapsed on the host -sim_insts 132071193 # Number of instructions simulated -sim_ops 221363385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory -system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1387954936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1387954936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 99822191 # Number of bytes written to this memory -system.physmem.bytes_written::total 99822191 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 173494367 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 56682005 # Number of read requests responded to by this memory -system.physmem.num_reads::total 230176372 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 20515731 # Number of write requests responded to by this memory -system.physmem.num_writes::total 20515731 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 10563363260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2362554267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12925917527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 10563363260 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 10563363260 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 759720678 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 759720678 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 262786559 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_func_calls 1595632 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 219019986 # number of integer instructions -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read -system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read -system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written -system.cpu.num_mem_refs 77165304 # number of memory refs -system.cpu.num_load_insts 56649587 # Number of load instructions -system.cpu.num_store_insts 20515717 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 262786558.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12326938 # Number of branches fetched -system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction -system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction -system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction -system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction -system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction -system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 221363385 # Class of executed instruction -system.membus.trans_dist::ReadReq 230176372 # Transaction distribution -system.membus.trans_dist::ReadResp 230176372 # Transaction distribution -system.membus.trans_dist::WriteReq 20515731 # Transaction distribution -system.membus.trans_dist::WriteResp 20515731 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 250692103 # Request fanout histogram -system.membus.snoop_fanout::mean 0.692062 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 77197736 30.79% 30.79% # Request fanout histogram -system.membus.snoop_fanout::1 173494367 69.21% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 250692103 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 25c6ff3ba..e69de29bb 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,507 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.250987 # Number of seconds simulated -sim_ticks 250987138500 # Number of ticks simulated -final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 637690 # Simulator instruction rate (inst/s) -host_op_rate 1068827 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1211861746 # Simulator tick rate (ticks/s) -host_mem_usage 298388 # Number of bytes of host memory used -host_seconds 207.11 # Real time elapsed on the host -sim_insts 132071193 # Number of instructions simulated -sim_ops 221363385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory -system.physmem.bytes_read::total 303040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 181760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 181760 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2840 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1895 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4735 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 724181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 483212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1207393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 724181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 724181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501974277 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 132071193 # Number of instructions committed -system.cpu.committedOps 221363385 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 219019986 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses -system.cpu.num_func_calls 1595632 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8268466 # number of instructions that are conditional controls -system.cpu.num_int_insts 219019986 # number of integer instructions -system.cpu.num_fp_insts 2162459 # number of float instructions -system.cpu.num_int_register_reads 519996939 # number of times the integer registers were read -system.cpu.num_int_register_writes 201355989 # number of times the integer registers were written -system.cpu.num_fp_register_reads 3037165 # number of times the floating registers were read -system.cpu.num_fp_register_writes 1831403 # number of times the floating registers were written -system.cpu.num_cc_register_reads 96962463 # number of times the CC registers were read -system.cpu.num_cc_register_writes 56242058 # number of times the CC registers were written -system.cpu.num_mem_refs 77165304 # number of memory refs -system.cpu.num_load_insts 56649587 # Number of load instructions -system.cpu.num_store_insts 20515717 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501974276.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 12326938 # Number of branches fetched -system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% # Class of executed instruction -system.cpu.op_class::IntAlu 134111833 60.58% 61.12% # Class of executed instruction -system.cpu.op_class::IntMult 772953 0.35% 61.47% # Class of executed instruction -system.cpu.op_class::IntDiv 7031501 3.18% 64.64% # Class of executed instruction -system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% # Class of executed instruction -system.cpu.op_class::MemRead 56649587 25.59% 90.73% # Class of executed instruction -system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 221363385 # Class of executed instruction -system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.414730 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332865 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332865 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits -system.cpu.dcache.overall_hits::total 77195831 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses -system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19933500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19933500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 97691000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 97691000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117624500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117624500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117624500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117624500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60958.715596 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60958.715596 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61908.111534 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61908.111534 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61745.144357 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61745.144357 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61745.144357 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7 # number of writebacks -system.cpu.dcache.writebacks::total 7 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19606500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19606500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 96113000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 96113000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115719500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 115719500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115719500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 115719500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59958.715596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59958.715596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60908.111534 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60908.111534 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency -system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.245085 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.710569 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.710569 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 415 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses -system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 173489673 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 173489673 # number of overall hits -system.cpu.icache.overall_hits::total 173489673 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses -system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 200232500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 200232500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 200232500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 200232500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 200232500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 200232500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 173494367 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 173494367 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 173494367 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000027 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42657.115467 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 42657.115467 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 42657.115467 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 42657.115467 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 42657.115467 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2836 # number of writebacks -system.cpu.icache.writebacks::total 2836 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4694 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 195538500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 195538500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 195538500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 195538500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 195538500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 195538500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41657.115467 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41657.115467 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.495575 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 0.021821 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.911143 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.172589 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.062808 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 532 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2836 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1854 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1854 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1864 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1854 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits -system.cpu.l2cache.overall_hits::total 1864 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1575 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2840 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 320 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2840 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1895 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4735 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses -system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93713500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 93713500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 169013000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 169013000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19042000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 19042000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 169013000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 112755500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 281768500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 169013000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 112755500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 281768500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 7 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2836 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4694 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 327 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4694 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6599 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4694 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6599 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.717533 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.619718 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.583113 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59507.602957 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 77963500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 77963500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 140613000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 140613000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15842000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15842000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 140613000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 93805500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 234418500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 140613000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 93805500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 234418500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.634921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.634921 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.619718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.619718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49506.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49506.250000 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.619718 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.583113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49507.602957 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9476 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16075 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 604288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6599 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000152 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6599 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7581000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3160 # Transaction distribution -system.membus.trans_dist::ReadExReq 1575 # Transaction distribution -system.membus.trans_dist::ReadExResp 1575 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3160 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4735 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4735 # Request fanout histogram -system.membus.reqLayer0.occupancy 4771000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 23675000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |