diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-22 11:16:40 -0800 |
---|---|---|
committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-22 11:16:40 -0800 |
commit | 63a25a56ccc93c24703fec87f830c833974e7060 (patch) | |
tree | a0f12244a32eb7da2963ca974ab49a993aee2cfc /tests/quick | |
parent | 8ea71c3907a411de9c203b45bfd6eab24e3ad849 (diff) | |
parent | 77eed184f529c4ccbef59ad2018d18ff3fbb54af (diff) | |
download | gem5-63a25a56ccc93c24703fec87f830c833974e7060.tar.xz |
m5: merged in hammer fix
Diffstat (limited to 'tests/quick')
22 files changed, 1050 insertions, 991 deletions
diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index 254c4b8b1..fa50fea55 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:47:18 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:47:37 -M5 executing on burrito +M5 compiled Feb 18 2011 15:40:30 +M5 revision Unknown +M5 started Feb 18 2011 18:52:59 +M5 executing on m55-001.pool command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 22288500 because target called exit() +Exiting @ tick 22294500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 246665e32..bb298d30a 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,37 +1,37 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 37548 # Simulator instruction rate (inst/s) -host_mem_usage 223436 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 130476959 # Simulator tick rate (ticks/s) +host_inst_rate 97475 # Simulator instruction rate (inst/s) +host_mem_usage 190320 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +host_tick_rate 337940129 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22288500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 2187 # Number of Address Generations +sim_ticks 22294500 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 2186 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 23.015873 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 87 # Number of BTB hits system.cpu.Branch-Predictor.BTBLookups 378 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 543 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condIncorrect 542 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 995 # Number of conditional branches predicted system.cpu.Branch-Predictor.lookups 1423 # Number of BP lookups system.cpu.Branch-Predictor.predictedNotTaken 1183 # Number of Branches Predicted As Not Taken (False). system.cpu.Branch-Predictor.predictedTaken 240 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 125 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 4617 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 51.615970 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 543 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.executions 4596 # Number of Instructions Executed. +system.cpu.Execution-Unit.mispredictPct 51.569933 # Percentage of Incorrect Branches Predicts +system.cpu.Execution-Unit.mispredicted 542 # Number of Branches Incorrectly Predicted system.cpu.Execution-Unit.predicted 509 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 538 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedNotTakenIncorrect 537 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.Execution-Unit.predictedTakenIncorrect 5 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 10532 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 5949 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 10530 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 5947 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File system.cpu.RegFile-Manager.regForwards 2845 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 16.048275 # Percentage of cycles cpu is active +system.cpu.activity 16.075353 # Percentage of cycles cpu is active system.cpu.comBranches 1051 # Number of Branches instructions committed system.cpu.comFloats 2 # Number of Floating Point instructions committed system.cpu.comInts 3265 # Number of Integer instructions committed @@ -42,17 +42,17 @@ system.cpu.comStores 865 # Nu system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 6.960962 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 6.960962 # CPI: Total CPI of All Threads +system.cpu.cpi 6.962836 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 6.962836 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56781.250000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53784.210526 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56786.458333 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53789.473684 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1089 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5451000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 5451500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.081013 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 5109500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 5110000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) @@ -75,31 +75,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 162000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56661.157025 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53687.500000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56663.223140 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53690.476190 # average overall mshr miss latency system.cpu.dcache.demand_hits 1808 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13712000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 13712500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.118049 # miss rate for demand accesses system.cpu.dcache.demand_misses 242 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 74 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9019500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 9020000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.024901 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 101.993452 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.024898 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 101.981030 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56661.157025 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53687.500000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56663.223140 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53690.476190 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1808 # number of overall hits -system.cpu.dcache.overall_miss_latency 13712000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 13712500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.118049 # miss rate for overall accesses system.cpu.dcache.overall_misses 242 # number of overall misses system.cpu.dcache.overall_mshr_hits 74 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9019500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 9020000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -107,7 +107,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 101.993452 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 101.981030 # Cycle average of tags in use system.cpu.dcache.total_refs 1808 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -128,10 +128,10 @@ system.cpu.dtb.write_acv 0 # DT system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.icache.ReadReq_accesses 955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55326.979472 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55322.580645 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 53094.684385 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 614 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 18866500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 18865000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.357068 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits @@ -147,10 +147,10 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 955 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55326.979472 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency 55322.580645 # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency system.cpu.icache.demand_hits 614 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 18866500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 18865000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.357068 # miss rate for demand accesses system.cpu.icache.demand_misses 341 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits @@ -160,14 +160,14 @@ system.cpu.icache.demand_mshr_misses 301 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.066887 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 136.984147 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.066877 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 136.964505 # Average occupied blocks per context system.cpu.icache.overall_accesses 955 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55326.979472 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency 55322.580645 # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 614 # number of overall hits -system.cpu.icache.overall_miss_latency 18866500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 18865000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.357068 # miss rate for overall accesses system.cpu.icache.overall_misses 341 # number of overall misses system.cpu.icache.overall_mshr_hits 40 # number of overall MSHR hits @@ -179,13 +179,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 0 # number of replacements system.cpu.icache.sampled_refs 300 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 136.984147 # Cycle average of tags in use +system.cpu.icache.tagsinuse 136.964505 # Cycle average of tags in use system.cpu.icache.total_refs 614 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 37424 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.143658 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.143658 # IPC: Total IPC of All Threads +system.cpu.idleCycles 37422 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.143620 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.143620 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits @@ -243,8 +243,8 @@ system.cpu.l2cache.demand_mshr_misses 468 # nu system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005889 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 192.975400 # Average occupied blocks per context +system.cpu.l2cache.occ_%::0 0.005888 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 192.950109 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 469 # number of overall (read+write) accesses system.cpu.l2cache.overall_avg_miss_latency 52243.589744 # average overall miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 40087.606838 # average overall mshr miss latency @@ -262,34 +262,34 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 394 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 192.975400 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 192.950109 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 44578 # number of cpu cycles simulated +system.cpu.numCycles 44590 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.runCycles 7154 # Number of cycles cpu stages are processed. +system.cpu.runCycles 7168 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 39836 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 4742 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 10.637534 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 40747 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 3831 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 8.593925 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 40491 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 4087 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 9.168200 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 43168 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 39847 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 4743 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 10.636914 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 40758 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 3832 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 8.593855 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 40488 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 4102 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 9.199372 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 43180 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 1410 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.162995 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 40170 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 4408 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 9.888286 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 11304 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-3.utilization 3.162144 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 40181 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 4409 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 9.887867 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 11319 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 2ad70ea48..41a76071a 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -5,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:55:51 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:56:02 -M5 executing on burrito +M5 compiled Feb 18 2011 18:35:15 +M5 revision Unknown +M5 started Feb 18 2011 18:52:36 +M5 executing on m55-001.pool command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 21534000 because target called exit() +Exiting @ tick 21538000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 1e86aa862..ac0fe4aec 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,37 +1,37 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32668 # Simulator instruction rate (inst/s) -host_mem_usage 224608 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 120542676 # Simulator tick rate (ticks/s) +host_inst_rate 94112 # Simulator instruction rate (inst/s) +host_mem_usage 191540 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 346291258 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 21534000 # Number of ticks simulated +sim_ticks 21538000 # Number of ticks simulated system.cpu.AGEN-Unit.agens 2404 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 14.054054 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 26 # Number of BTB hits system.cpu.Branch-Predictor.BTBLookups 185 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 845 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condIncorrect 844 # Number of conditional branches incorrect system.cpu.Branch-Predictor.condPredicted 778 # Number of conditional branches predicted system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups system.cpu.Branch-Predictor.predictedNotTaken 949 # Number of Branches Predicted As Not Taken (False). system.cpu.Branch-Predictor.predictedTaken 117 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 86 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 3963 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 92.148310 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 845 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.executions 3261 # Number of Instructions Executed. +system.cpu.Execution-Unit.mispredictPct 92.139738 # Percentage of Incorrect Branches Predicts +system.cpu.Execution-Unit.mispredicted 844 # Number of Branches Incorrectly Predicted system.cpu.Execution-Unit.predicted 72 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 813 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedNotTakenIncorrect 812 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.Execution-Unit.predictedTakenIncorrect 32 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 10006 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 6596 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 10004 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 6594 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File system.cpu.RegFile-Manager.regForwards 1378 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 13.935777 # Percentage of cycles cpu is active +system.cpu.activity 13.954082 # Percentage of cycles cpu is active system.cpu.comBranches 916 # Number of Branches instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed system.cpu.comInts 2155 # Number of Integer instructions committed @@ -42,17 +42,17 @@ system.cpu.comStores 925 # Nu system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 7.391282 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 7.391282 # CPI: Total CPI of All Threads +system.cpu.cpi 7.392655 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 7.392655 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56681.818182 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53683.908046 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_miss_latency 56676.136364 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53678.160920 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4988000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency 4987500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.075601 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 4670500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency 4670000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) @@ -75,31 +75,31 @@ system.cpu.dcache.blocked_cycles::no_mshrs 0 # system.cpu.dcache.blocked_cycles::no_targets 265500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56298.342541 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53666.666667 # average overall mshr miss latency +system.cpu.dcache.demand_avg_miss_latency 56295.580110 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10190000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency 10189500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.086644 # miss rate for demand accesses system.cpu.dcache.demand_misses 181 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7406000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 7405500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.021745 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 89.066455 # Average occupied blocks per context +system.cpu.dcache.occ_blocks::0 89.067186 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56298.342541 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53666.666667 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56295.580110 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53663.043478 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_hits 1908 # number of overall hits -system.cpu.dcache.overall_miss_latency 10190000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency 10189500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.086644 # miss rate for overall accesses system.cpu.dcache.overall_misses 181 # number of overall misses system.cpu.dcache.overall_mshr_hits 43 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7406000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 7405500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -107,7 +107,7 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 89.066455 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.067186 # Cycle average of tags in use system.cpu.dcache.total_refs 1908 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks @@ -121,14 +121,14 @@ system.cpu.dtb.write_accesses 0 # DT system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.icache.ReadReq_accesses 853 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55526.246719 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53153.605016 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_miss_latency 55527.559055 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53156.739812 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_hits 472 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 21155500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency 21156000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.446659 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses system.cpu.icache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 16956000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 16957000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.373974 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -140,31 +140,31 @@ system.cpu.icache.blocked_cycles::no_mshrs 0 # system.cpu.icache.blocked_cycles::no_targets 62000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.demand_accesses 853 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55526.246719 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53153.605016 # average overall mshr miss latency +system.cpu.icache.demand_avg_miss_latency 55527.559055 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency system.cpu.icache.demand_hits 472 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 21155500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency 21156000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.446659 # miss rate for demand accesses system.cpu.icache.demand_misses 381 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 62 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 16956000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 16957000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.373974 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.070944 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 145.293265 # Average occupied blocks per context +system.cpu.icache.occ_%::0 0.070945 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 145.295903 # Average occupied blocks per context system.cpu.icache.overall_accesses 853 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55526.246719 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53153.605016 # average overall mshr miss latency +system.cpu.icache.overall_avg_miss_latency 55527.559055 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53156.739812 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_hits 472 # number of overall hits -system.cpu.icache.overall_miss_latency 21155500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency 21156000 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.446659 # miss rate for overall accesses system.cpu.icache.overall_misses 381 # number of overall misses system.cpu.icache.overall_mshr_hits 62 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 16956000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 16957000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.373974 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -172,13 +172,13 @@ system.cpu.icache.overall_mshr_uncacheable_misses 0 system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 145.293265 # Cycle average of tags in use +system.cpu.icache.tagsinuse 145.295903 # Cycle average of tags in use system.cpu.icache.total_refs 472 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 37067 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.135295 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.135295 # IPC: Total IPC of All Threads +system.cpu.idleCycles 37066 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.135269 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.135269 # IPC: Total IPC of All Threads system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -198,13 +198,13 @@ system.cpu.l2cache.ReadExReq_mshr_miss_latency 2052000 system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52355.198020 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40152.227723 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency 52357.673267 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40153.465347 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 21151500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency 21152500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 16221500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency 16222000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked @@ -216,31 +216,31 @@ system.cpu.l2cache.blocked_cycles::no_mshrs 0 # system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52368.131868 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40161.538462 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_miss_latency 52370.329670 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23827500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency 23828500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 18273500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency 18274000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.occ_%::0 0.006169 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 202.148379 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::0 202.151439 # Average occupied blocks per context system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52368.131868 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40161.538462 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_miss_latency 52370.329670 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40162.637363 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23827500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency 23828500 # number of overall miss cycles system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses system.cpu.l2cache.overall_misses 455 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 18273500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency 18274000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -248,34 +248,34 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses 0 system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 202.148379 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 202.151439 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 43069 # number of cpu cycles simulated +system.cpu.numCycles 43077 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.runCycles 6002 # Number of cycles cpu stages are processed. +system.cpu.runCycles 6011 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 39196 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 3873 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 8.992547 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 40152 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 2917 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 6.772853 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 40243 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 2826 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 6.561564 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 41749 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.idleCycles 39203 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 3874 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 8.993198 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 40159 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 2918 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 6.773916 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 40245 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 2832 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 6.574274 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 41757 # Number of cycles 0 instructions are processed. system.cpu.stage-3.runCycles 1320 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.064849 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 39866 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.utilization 3.064280 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 39874 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 3203 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 7.436904 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 10184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-4.utilization 7.435522 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 10193 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.timesIdled 427 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout index 0767b9777..1943466e8 100755 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/simout @@ -5,12 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 12 2011 02:22:23 +M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch +M5 started Feb 12 2011 02:22:27 M5 executing on burrito -command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing +command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. Hello world! -Exiting @ tick 13766000 because target called exit() +Exiting @ tick 11421500 because target called exit() diff --git a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt index 182e72d25..c2dfaa3ff 100644 --- a/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 47133 # Simulator instruction rate (inst/s) -host_mem_usage 227692 # Number of bytes of host memory used +host_inst_rate 47598 # Simulator instruction rate (inst/s) +host_mem_usage 231896 # Number of bytes of host memory used host_seconds 0.21 # Real time elapsed on the host -host_tick_rate 66053082 # Simulator tick rate (ticks/s) +host_tick_rate 55349277 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9809 # Number of instructions simulated -sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13766000 # Number of ticks simulated +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 11421500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 772 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1892 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 944 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 2550 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1920 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 1920 # Number of BP lookups +system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 2777 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2777 # Number of BP lookups system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 1214 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 37 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 139 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 15124 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.648572 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.100130 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 11906 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.823870 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.588166 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 9612 63.55% 63.55% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 3088 20.42% 83.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 1220 8.07% 92.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 836 5.53% 97.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 232 1.53% 99.10% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 57 0.38% 99.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 30 0.20% 99.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 12 0.08% 99.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 37 0.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 8274 69.49% 69.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1230 10.33% 79.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 588 4.94% 84.76% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 963 8.09% 92.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 395 3.32% 96.17% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 136 1.14% 97.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 125 1.05% 98.36% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 56 0.47% 98.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 139 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 15124 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 11906 # Number of insts commited each cycle system.cpu.commit.COM:count 9809 # Number of instructions committed system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 0 # Number of function calls committed. @@ -44,415 +44,417 @@ system.cpu.commit.COM:loads 1056 # Nu system.cpu.commit.COM:membars 0 # Number of memory barriers committed system.cpu.commit.COM:refs 1990 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 3832 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9374 # The number of squashed insts skipped by commit system.cpu.committedInsts 9809 # Number of Instructions Simulated system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.806912 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.806912 # CPI: Total CPI of All Threads -system.cpu.dcache.ReadReq_accesses 1244 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37105.263158 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35048.387097 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1168 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2820000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.061093 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 76 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 14 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 2173000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.049839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 62 # number of ReadReq MSHR misses +system.cpu.cpi 2.328882 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.328882 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 1541 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 34473.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35119.402985 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1427 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3930000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.073978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2353000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.043478 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35775.641026 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 34089.456869 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36012.987013 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10670000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2790500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2773000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 12.870504 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 14.321678 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2178 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 33913.881748 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1789 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 13192500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.178604 # miss rate for demand accesses -system.cpu.dcache.demand_misses 389 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 249 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4963500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.064279 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 140 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2475 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34192.037471 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14600000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.172525 # miss rate for demand accesses +system.cpu.dcache.demand_misses 427 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5126000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.058182 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.020744 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 84.965644 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2178 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 33913.881748 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35453.571429 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.020970 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 85.892970 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2475 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34192.037471 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1789 # number of overall hits -system.cpu.dcache.overall_miss_latency 13192500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.178604 # miss rate for overall accesses -system.cpu.dcache.overall_misses 389 # number of overall misses -system.cpu.dcache.overall_mshr_hits 249 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4963500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.064279 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 140 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2048 # number of overall hits +system.cpu.dcache.overall_miss_latency 14600000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.172525 # miss rate for overall accesses +system.cpu.dcache.overall_misses 427 # number of overall misses +system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5126000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.058182 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 139 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 84.965644 # Cycle average of tags in use -system.cpu.dcache.total_refs 1789 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.892970 # Cycle average of tags in use +system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 464 # Number of cycles decode is blocked -system.cpu.decode.DECODE:DecodedInsts 15304 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 6233 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 8371 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 721 # Number of cycles decode is squashing -system.cpu.decode.DECODE:UnblockCycles 56 # Number of cycles decode is unblocking -system.cpu.fetch.Branches 1920 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1255 # Number of cache lines fetched -system.cpu.fetch.Cycles 9031 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 8830 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 469 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.069735 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1255 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 772 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.320706 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 15845 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002083 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.178869 # Number of instructions fetched each cycle (Total) +system.cpu.decode.DECODE:BlockedCycles 1367 # Number of cycles decode is blocked +system.cpu.decode.DECODE:DecodedInsts 22275 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7155 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 3308 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1504 # Number of cycles decode is squashing +system.cpu.decode.DECODE:UnblockCycles 76 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 2777 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1732 # Number of cache lines fetched +system.cpu.fetch.Cycles 3623 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 245 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.121564 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1732 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 944 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.568027 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 13410 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.734526 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.109133 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 7129 44.99% 44.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4489 28.33% 73.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1878 11.85% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2046 12.91% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 57 0.36% 98.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 227 1.43% 99.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9877 73.65% 73.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 162 1.21% 74.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 123 0.92% 75.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.69% 77.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 192 1.43% 78.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 174 1.30% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 266 1.98% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 175 1.30% 83.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2214 16.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15845 # Number of instructions fetched each cycle (Total) -system.cpu.fp_regfile_reads 2 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1255 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 37417.543860 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35040.697674 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 970 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 10664000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.227092 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 285 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 9040500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.205578 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 258 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 13410 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 4 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 1732 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36454.794521 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35105.084746 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 13306000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.210739 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 365 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 10356000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.170323 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 3.759690 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.633898 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1255 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 37417.543860 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency -system.cpu.icache.demand_hits 970 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 10664000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.227092 # miss rate for demand accesses -system.cpu.icache.demand_misses 285 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9040500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.205578 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 258 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1732 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36454.794521 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency +system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 13306000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.210739 # miss rate for demand accesses +system.cpu.icache.demand_misses 365 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 10356000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.170323 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.061525 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 126.002915 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1255 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 37417.543860 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35040.697674 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.070726 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 144.846093 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1732 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36454.794521 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 970 # number of overall hits -system.cpu.icache.overall_miss_latency 10664000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.227092 # miss rate for overall accesses -system.cpu.icache.overall_misses 285 # number of overall misses -system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9040500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.205578 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 258 # number of overall MSHR misses +system.cpu.icache.overall_hits 1367 # number of overall hits +system.cpu.icache.overall_miss_latency 13306000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.210739 # miss rate for overall accesses +system.cpu.icache.overall_misses 365 # number of overall misses +system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 10356000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.170323 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 258 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 126.002915 # Cycle average of tags in use -system.cpu.icache.total_refs 970 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.846093 # Cycle average of tags in use +system.cpu.icache.total_refs 1367 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11688 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1318 # Number of branches executed +system.cpu.idleCycles 9434 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1551 # Number of branches executed system.cpu.iew.EXEC:nop 0 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.434678 # Inst execution rate -system.cpu.iew.EXEC:refs 2353 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1060 # Number of stores executed +system.cpu.iew.EXEC:rate 0.676151 # Inst execution rate +system.cpu.iew.EXEC:refs 2971 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1306 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 10358 # num instructions consuming a value -system.cpu.iew.WB:count 11818 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.702935 # average fanout of values written-back +system.cpu.iew.WB:consumers 14704 # num instructions consuming a value +system.cpu.iew.WB:count 15138 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.679747 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 7281 # num instructions producing a value -system.cpu.iew.WB:rate 0.429230 # insts written-back per cycle -system.cpu.iew.WB:sent 11866 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 487 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 58 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 1535 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 17 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 418 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1238 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 13635 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1293 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 536 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 11968 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 9995 # num instructions producing a value +system.cpu.iew.WB:rate 0.662669 # insts written-back per cycle +system.cpu.iew.WB:sent 15263 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 565 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2105 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 19184 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1665 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 710 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 15446 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1504 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 21 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 479 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 304 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 25083 # number of integer regfile reads -system.cpu.int_regfile_writes 11189 # number of integer regfile writes -system.cpu.ipc 0.356263 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.356263 # IPC: Total IPC of All Threads -system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 10018 80.12% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 1360 10.88% 91.02% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1123 8.98% 100.00% # Type of FU issued +system.cpu.iew.lsq.thread.0.memOrderViolation 31 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1049 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 705 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 496 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 23051 # number of integer regfile reads +system.cpu.int_regfile_writes 14062 # number of integer regfile writes +system.cpu.ipc 0.429391 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.429391 # IPC: Total IPC of All Threads +system.cpu.iq.ISSUE:FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 12967 80.26% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 80.29% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 1786 11.05% 91.34% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1399 8.66% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 12504 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.000320 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 16156 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.008789 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 3 75.00% 75.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1 25.00% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 97 68.31% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 68.31% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 26 18.31% 86.62% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 19 13.38% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 15845 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.789145 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.977935 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 13410 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.204773 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.912582 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8160 51.50% 51.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 4079 25.74% 77.24% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 2594 16.37% 93.61% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 834 5.26% 98.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 157 0.99% 99.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 19 0.12% 99.99% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 2 0.01% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8282 61.76% 61.76% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1307 9.75% 71.51% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 986 7.35% 78.86% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 745 5.56% 84.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 787 5.87% 90.28% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 588 4.38% 94.67% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 498 3.71% 98.38% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 170 1.27% 99.65% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 15845 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.454146 # Inst issue rate -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 12501 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 40849 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 11816 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 16975 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 13618 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 12504 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 17 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 3342 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 5066 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34493.589744 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31326.923077 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2690500 # number of ReadExReq miss cycles +system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::total 13410 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.707232 # Inst issue rate +system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses +system.cpu.iq.fp_inst_queue_reads 9 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes +system.cpu.iq.int_alu_accesses 16289 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 45908 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 15134 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 27963 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 19154 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 16156 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8758 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 11067 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34616.883117 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31389.610390 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2443500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 320 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34188.679245 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.716981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34245.833333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 10872000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.993750 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 318 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 9859500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993750 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 318 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 12328500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.006309 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 398 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34248.737374 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34311.212815 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.994975 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 396 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 14994000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12303000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.994975 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 396 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 13591500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.004816 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 157.820330 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 398 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34248.737374 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.181818 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005436 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 178.138745 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34311.212815 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.994975 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 396 # number of overall misses +system.cpu.l2cache.overall_miss_latency 14994000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 437 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12303000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.994975 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 396 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 13591500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 317 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 157.820330 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.138745 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 1535 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1238 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 5334 # number of misc regfile reads -system.cpu.numCycles 27533 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 24 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2105 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 6857 # number of misc regfile reads +system.cpu.numCycles 22844 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 105 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 565 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 6603 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 38664 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 14745 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 13787 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 8027 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 721 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 108 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4419 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 51 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 7399 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 247 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 44700 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 21187 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 19905 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 3124 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1504 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 378 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 10537 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 38648 # Number of integer rename lookups -system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 20 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 169 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 17 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 28728 # The number of ROB reads -system.cpu.rob.rob_writes 28005 # The number of ROB writes -system.cpu.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:int_rename_lookups 44684 # Number of integer rename lookups +system.cpu.rename.RENAME:serializeStallCycles 440 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 1476 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed +system.cpu.rob.rob_reads 30950 # The number of ROB reads +system.cpu.rob.rob_writes 39896 # The number of ROB writes +system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 11 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout index 09f4d0b50..8fb08388b 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt index 1dca11ec5..cddb4c7b6 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 180423 # Simulator instruction rate (inst/s) -host_mem_usage 219128 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -host_tick_rate 103433649 # Simulator tick rate (ticks/s) +host_inst_rate 992012 # Simulator instruction rate (inst/s) +host_mem_usage 219616 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +host_tick_rate 556721453 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000006 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index a12716c02..569662936 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,7 +34,7 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Feb/07/2011 02:32:13 +Real time: Feb/08/2011 00:58:34 Profiler Stats -------------- @@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.35 -Virtual_time_in_minutes: 0.00583333 -Virtual_time_in_hours: 9.72222e-05 -Virtual_time_in_days: 4.05093e-06 +Virtual_time_in_seconds: 0.26 +Virtual_time_in_minutes: 0.00433333 +Virtual_time_in_hours: 7.22222e-05 +Virtual_time_in_days: 3.00926e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 38.6094 -mbytes_total: 231.508 -resident_ratio: 0.16679 +mbytes_resident: 38.6797 +mbytes_total: 231.98 +resident_ratio: 0.166754 ruby_cycles_executed: [ 276485 ] @@ -125,7 +125,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 10950 +page_reclaims: 11003 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout index 877c8d9b9..ab908eedc 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:13 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index b88df01c5..491eaf1d1 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32378 # Simulator instruction rate (inst/s) -host_mem_usage 237068 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host -host_tick_rate 911908 # Simulator tick rate (ticks/s) +host_inst_rate 81703 # Simulator instruction rate (inst/s) +host_mem_usage 237552 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +host_tick_rate 2292859 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000276 # Number of seconds simulated @@ -24,7 +24,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout index d6afbecf0..43766d7be 100755 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/simout @@ -5,9 +5,9 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 02:32:07 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 02:32:24 +M5 compiled Feb 8 2011 00:58:32 +M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip +M5 started Feb 8 2011 00:58:34 M5 executing on burrito command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt index 0c21882f5..fc7acffe1 100644 --- a/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 594010 # Simulator instruction rate (inst/s) -host_mem_usage 226844 # Number of bytes of host memory used +host_inst_rate 525864 # Simulator instruction rate (inst/s) +host_mem_usage 227336 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host -host_tick_rate 1712507148 # Simulator tick rate (ticks/s) +host_tick_rate 1518719132 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 9810 # Number of instructions simulated sim_seconds 0.000029 # Number of seconds simulated @@ -208,7 +208,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_insts 9810 # Number of instructions executed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_int_insts 9715 # number of integer instructions -system.cpu.num_int_register_reads 26194 # number of times the integer registers were read +system.cpu.num_int_register_reads 21313 # number of times the integer registers were read system.cpu.num_int_register_writes 9368 # number of times the integer registers were written system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_mem_refs 1990 # number of memory refs diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 79021a958..859778cbe 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -7,11 +7,11 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus +children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -167,7 +167,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/chips/pd/randd/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false @@ -187,7 +187,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.clcd.dma +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma [system.iocache] type=BaseCache @@ -217,7 +217,7 @@ tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.iobus.port[24] +cpu_side=system.iobus.port[25] mem_side=system.membus.port[5] [system.l2c] @@ -291,7 +291,7 @@ port=system.membus.port[1] [system.realview] type=RealView -children=aaci_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system @@ -305,6 +305,22 @@ platform=system.realview system=system pio=system.iobus.port[20] +[system.realview.cf0_fake] +type=IsaFake +pio_addr=402653184 +pio_latency=1000 +pio_size=4095 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[24] + [system.realview.clcd] type=Pl111 amba_id=1315089 @@ -317,7 +333,8 @@ pio_addr=268566528 pio_latency=10000 platform=system.realview system=system -dma=system.iobus.port[25] +vnc=system.vncserver +dma=system.iobus.port[26] pio=system.iobus.port[5] [system.realview.dmac_fake] @@ -391,24 +408,28 @@ pio=system.iobus.port[17] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=52 +is_mouse=false pio_addr=268460032 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[6] [system.realview.kmi1] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=53 +is_mouse=true pio_addr=268464128 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[7] [system.realview.l2x0_fake] @@ -594,3 +615,8 @@ use_default_range=false width=64 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.vncserver] +type=VncServer +number=0 +port=5900 + diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr index 122561307..63ac398c9 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr @@ -1,3 +1,5 @@ +warn: Sockets disabled, not accepting vnc client connections +For more information see: http://www.m5sim.org/warn/af6a84f6 warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index ba4c6742c..180619cc1 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:53:13 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:53:26 -M5 executing on burrito +M5 compiled Feb 11 2011 17:53:57 +M5 revision 6c65f7ee86c1 7949 default qtip tip ext/vnc_stats_updates.patch +M5 started Feb 11 2011 17:54:00 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 25821310500 because m5_exit instruction encountered +Exiting @ tick 26073617500 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 0a7542a7c..9854d94df 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 739167 # Simulator instruction rate (inst/s) -host_mem_usage 360776 # Number of bytes of host memory used -host_seconds 68.93 # Real time elapsed on the host -host_tick_rate 374609475 # Simulator tick rate (ticks/s) +host_inst_rate 2481190 # Simulator instruction rate (inst/s) +host_mem_usage 374936 # Number of bytes of host memory used +host_seconds 20.74 # Real time elapsed on the host +host_tick_rate 1257294139 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50949504 # Number of instructions simulated -sim_seconds 0.025821 # Number of seconds simulated -sim_ticks 25821310500 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 96794 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 96794 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits::0 91895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 91895 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050613 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 4899 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4899 # number of LoadLockedReq misses -system.cpu.dcache.ReadReq_accesses::0 7714516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7714516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_hits::0 7482193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7482193 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_rate::0 0.030115 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 232323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 232323 # number of ReadReq misses -system.cpu.dcache.StoreCondReq_accesses::0 96793 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 96793 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 96793 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 96793 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6604860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6604860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_hits::0 6433311 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6433311 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_rate::0 0.025973 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 171549 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 171549 # number of WriteReq misses +sim_insts 51454118 # Number of instructions simulated +sim_seconds 0.026074 # Number of seconds simulated +sim_ticks 26073617500 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits::0 95292 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95292 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051387 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5162 # number of LoadLockedReq misses +system.cpu.dcache.ReadReq_accesses::0 7830681 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7830681 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_hits::0 7594158 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7594158 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_rate::0 0.030205 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 236523 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 236523 # number of ReadReq misses +system.cpu.dcache.StoreCondReq_accesses::0 100453 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100453 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100453 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100453 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6676067 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6676067 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_hits::0 6503881 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6503881 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_rate::0 0.025792 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172186 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172186 # number of WriteReq misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.663994 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.695419 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14319376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14506748 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14319376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 14506748 # number of demand (read+write) accesses system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 13915504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::0 14098039 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13915504 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 14098039 # number of demand (read+write) hits system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028205 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::0 0.028174 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 403872 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 408709 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 403872 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 408709 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -67,26 +67,26 @@ system.cpu.dcache.demand_mshr_misses 0 # nu system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999475 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.731250 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14319376 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.999480 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 511.733850 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14506748 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14319376 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 14506748 # number of overall (read+write) accesses system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 13915504 # number of overall hits +system.cpu.dcache.overall_hits::0 14098039 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 13915504 # number of overall hits +system.cpu.dcache.overall_hits::total 14098039 # number of overall hits system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028205 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.028174 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 403872 # number of overall misses +system.cpu.dcache.overall_misses::0 408709 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 403872 # number of overall misses +system.cpu.dcache.overall_misses::total 408709 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -95,66 +95,66 @@ system.cpu.dcache.overall_mshr_miss_rate::total no_value system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 406424 # number of replacements -system.cpu.dcache.sampled_refs 406936 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 411520 # number of replacements +system.cpu.dcache.sampled_refs 412032 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.731250 # Cycle average of tags in use -system.cpu.dcache.total_refs 14106027 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.733850 # Cycle average of tags in use +system.cpu.dcache.total_refs 14295623 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21760000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 379025 # number of writebacks -system.cpu.dtb.accesses 15336291 # DTB accesses +system.cpu.dcache.writebacks 381867 # number of writebacks +system.cpu.dtb.accesses 15531286 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2242 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2267 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15330762 # DTB hits +system.cpu.dtb.hits 15525735 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5529 # DTB misses +system.cpu.dtb.misses 5551 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 768 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8622893 # DTB read accesses -system.cpu.dtb.read_hits 8618361 # DTB read hits -system.cpu.dtb.read_misses 4532 # DTB read misses -system.cpu.dtb.write_accesses 6713398 # DTB write accesses -system.cpu.dtb.write_hits 6712401 # DTB write hits -system.cpu.dtb.write_misses 997 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41172623 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41172623 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_hits::0 40741841 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 40741841 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_rate::0 0.010463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 430782 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 430782 # number of ReadReq misses +system.cpu.dtb.prefetch_faults 775 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8743013 # DTB read accesses +system.cpu.dtb.read_hits 8738461 # DTB read hits +system.cpu.dtb.read_misses 4552 # DTB read misses +system.cpu.dtb.write_accesses 6788273 # DTB write accesses +system.cpu.dtb.write_hits 6787274 # DTB write hits +system.cpu.dtb.write_misses 999 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41564629 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41564629 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_hits::0 41131432 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41131432 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_rate::0 0.010422 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 433197 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433197 # number of ReadReq misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.576690 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.948781 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41172623 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41564629 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41172623 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 41564629 # number of demand (read+write) accesses system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.demand_hits::0 40741841 # number of demand (read+write) hits +system.cpu.icache.demand_hits::0 41131432 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 40741841 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 41131432 # number of demand (read+write) hits system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010463 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::0 0.010422 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 430782 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 433197 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 430782 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433197 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -164,26 +164,26 @@ system.cpu.icache.demand_mshr_misses 0 # nu system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.929162 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 475.731149 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41172623 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.930040 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 476.180679 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41564629 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41172623 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 41564629 # number of overall (read+write) accesses system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 40741841 # number of overall hits +system.cpu.icache.overall_hits::0 41131432 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 40741841 # number of overall hits +system.cpu.icache.overall_hits::total 41131432 # number of overall hits system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010463 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.010422 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 430782 # number of overall misses +system.cpu.icache.overall_misses::0 433197 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 430782 # number of overall misses +system.cpu.icache.overall_misses::total 433197 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -192,15 +192,15 @@ system.cpu.icache.overall_mshr_miss_rate::total no_value system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 430269 # number of replacements -system.cpu.icache.sampled_refs 430781 # Sample count of references to valid blocks. +system.cpu.icache.replacements 432684 # number of replacements +system.cpu.icache.sampled_refs 433196 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 475.731149 # Cycle average of tags in use -system.cpu.icache.total_refs 40741841 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 476.180679 # Cycle average of tags in use +system.cpu.icache.total_refs 41131432 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 4544230000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 33727 # number of writebacks +system.cpu.icache.writebacks 33708 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41173750 # DTB accesses +system.cpu.itb.accesses 41565756 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -208,9 +208,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41170928 # DTB hits -system.cpu.itb.inst_accesses 41173750 # ITB inst accesses -system.cpu.itb.inst_hits 41170928 # ITB inst hits +system.cpu.itb.hits 41562934 # DTB hits +system.cpu.itb.inst_accesses 41565756 # ITB inst accesses +system.cpu.itb.inst_hits 41562934 # ITB inst hits system.cpu.itb.inst_misses 2822 # ITB inst misses system.cpu.itb.misses 2822 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -224,10 +224,10 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 51642622 # number of cpu cycles simulated +system.cpu.numCycles 52147236 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 51642622 # Number of busy cycles +system.cpu.num_busy_cycles 52147236 # Number of busy cycles system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6059 # Number of float alu accesses system.cpu.num_fp_insts 6059 # number of float instructions @@ -235,14 +235,14 @@ system.cpu.num_fp_register_reads 4227 # nu system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 50949504 # Number of instructions executed -system.cpu.num_int_alu_accesses 41395090 # Number of integer alu accesses -system.cpu.num_int_insts 41395090 # number of integer instructions -system.cpu.num_int_register_reads 128438705 # number of times the integer registers were read -system.cpu.num_int_register_writes 33973128 # number of times the integer registers were written -system.cpu.num_load_insts 9082722 # Number of load instructions -system.cpu.num_mem_refs 16092645 # number of memory refs -system.cpu.num_store_insts 7009923 # Number of store instructions +system.cpu.num_insts 51454118 # Number of instructions executed +system.cpu.num_int_alu_accesses 41848094 # Number of integer alu accesses +system.cpu.num_int_insts 41848094 # number of integer instructions +system.cpu.num_int_register_reads 129780130 # number of times the integer registers were read +system.cpu.num_int_register_writes 34330061 # number of times the integer registers were written +system.cpu.num_load_insts 9213901 # Number of load instructions +system.cpu.num_mem_refs 16300106 # number of memory refs +system.cpu.num_store_insts 7086205 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -310,61 +310,61 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.ReadExReq_accesses::0 169714 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169714 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_hits::0 60310 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 60310 # number of ReadExReq hits -system.l2c.ReadExReq_miss_rate::0 0.644637 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 109404 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 109404 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 665898 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 6073 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 671971 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 648226 # number of ReadReq hits -system.l2c.ReadReq_hits::1 6049 # number of ReadReq hits -system.l2c.ReadReq_hits::total 654275 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.026539 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.003952 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.030491 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 17672 # number of ReadReq misses -system.l2c.ReadReq_misses::1 24 # number of ReadReq misses -system.l2c.ReadReq_misses::total 17696 # number of ReadReq misses -system.l2c.UpgradeReq_accesses::0 1835 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 170347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170347 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_hits::0 60613 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 60613 # number of ReadExReq hits +system.l2c.ReadExReq_miss_rate::0 0.644179 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 109734 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 109734 # number of ReadExReq misses +system.l2c.ReadReq_accesses::0 672769 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 6110 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 678879 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_hits::0 651602 # number of ReadReq hits +system.l2c.ReadReq_hits::1 6087 # number of ReadReq hits +system.l2c.ReadReq_hits::total 657689 # number of ReadReq hits +system.l2c.ReadReq_miss_rate::0 0.031463 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.003764 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.035227 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 21167 # number of ReadReq misses +system.l2c.ReadReq_misses::1 23 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21190 # number of ReadReq misses +system.l2c.UpgradeReq_accesses::0 1839 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1839 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_rate::0 0.990736 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1818 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1818 # number of UpgradeReq misses -system.l2c.Writeback_accesses::0 412752 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 412752 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 412752 # number of Writeback hits -system.l2c.Writeback_hits::total 412752 # number of Writeback hits +system.l2c.UpgradeReq_miss_rate::0 0.990756 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses +system.l2c.Writeback_accesses::0 415575 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 415575 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 415575 # number of Writeback hits +system.l2c.Writeback_hits::total 415575 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.885433 # Average number of references to valid blocks. +system.l2c.avg_refs 6.741439 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 835612 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 6073 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 841685 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 843116 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 6110 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 849226 # number of demand (read+write) accesses system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 708536 # number of demand (read+write) hits -system.l2c.demand_hits::1 6049 # number of demand (read+write) hits -system.l2c.demand_hits::total 714585 # number of demand (read+write) hits +system.l2c.demand_hits::0 712215 # number of demand (read+write) hits +system.l2c.demand_hits::1 6087 # number of demand (read+write) hits +system.l2c.demand_hits::total 718302 # number of demand (read+write) hits system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.152075 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.003952 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.156027 # miss rate for demand accesses -system.l2c.demand_misses::0 127076 # number of demand (read+write) misses -system.l2c.demand_misses::1 24 # number of demand (read+write) misses -system.l2c.demand_misses::total 127100 # number of demand (read+write) misses +system.l2c.demand_miss_rate::0 0.155259 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.003764 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.159023 # miss rate for demand accesses +system.l2c.demand_misses::0 130901 # number of demand (read+write) misses +system.l2c.demand_misses::1 23 # number of demand (read+write) misses +system.l2c.demand_misses::total 130924 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses @@ -374,28 +374,28 @@ system.l2c.demand_mshr_misses 0 # nu system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.072507 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.478199 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 4751.792305 # Average occupied blocks per context -system.l2c.occ_blocks::1 31339.221407 # Average occupied blocks per context -system.l2c.overall_accesses::0 835612 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 6073 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 841685 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.076407 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.476934 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5007.401793 # Average occupied blocks per context +system.l2c.occ_blocks::1 31256.365097 # Average occupied blocks per context +system.l2c.overall_accesses::0 843116 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 6110 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 849226 # number of overall (read+write) accesses system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 708536 # number of overall hits -system.l2c.overall_hits::1 6049 # number of overall hits -system.l2c.overall_hits::total 714585 # number of overall hits +system.l2c.overall_hits::0 712215 # number of overall hits +system.l2c.overall_hits::1 6087 # number of overall hits +system.l2c.overall_hits::total 718302 # number of overall hits system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.152075 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.003952 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.156027 # miss rate for overall accesses -system.l2c.overall_misses::0 127076 # number of overall misses -system.l2c.overall_misses::1 24 # number of overall misses -system.l2c.overall_misses::total 127100 # number of overall misses +system.l2c.overall_miss_rate::0 0.155259 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.003764 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.159023 # miss rate for overall accesses +system.l2c.overall_misses::0 130901 # number of overall misses +system.l2c.overall_misses::1 23 # number of overall misses +system.l2c.overall_misses::total 130924 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses @@ -404,12 +404,12 @@ system.l2c.overall_mshr_miss_rate::total 0 # ms system.l2c.overall_mshr_misses 0 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 95922 # number of replacements -system.l2c.sampled_refs 125830 # Sample count of references to valid blocks. +system.l2c.replacements 97028 # number of replacements +system.l2c.sampled_refs 129660 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36091.013712 # Cycle average of tags in use -system.l2c.total_refs 866394 # Total number of references to valid blocks. +system.l2c.tagsinuse 36263.766890 # Cycle average of tags in use +system.l2c.total_refs 874095 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 90126 # number of writebacks +system.l2c.writebacks 90970 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 4fad32362..49b04d190 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -7,11 +7,11 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus +children=bridge cpu diskmem intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver boot_cpu_frequency=500 boot_osflags=earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps slram=slram0,0x8000000,+0x8000000 mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm +kernel=/chips/pd/randd/dist/binaries/vmlinux.arm load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -164,7 +164,7 @@ type=ExeTracer [system.diskmem] type=PhysicalMemory -file=/dist/m5/system/disks/ael-arm.ext2 +file=/chips/pd/randd/dist/disks/ael-arm.ext2 latency=30000 latency_var=0 null=false @@ -184,7 +184,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.clcd.dma +port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.realview.cf0_fake.pio system.iocache.cpu_side system.realview.clcd.dma [system.iocache] type=BaseCache @@ -214,7 +214,7 @@ tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.iobus.port[24] +cpu_side=system.iobus.port[25] mem_side=system.membus.port[5] [system.l2c] @@ -288,7 +288,7 @@ port=system.membus.port[1] [system.realview] type=RealView -children=aaci_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=aaci_fake cf0_fake clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake intrctrl=system.intrctrl system=system @@ -302,6 +302,22 @@ platform=system.realview system=system pio=system.iobus.port[20] +[system.realview.cf0_fake] +type=IsaFake +pio_addr=402653184 +pio_latency=1000 +pio_size=4095 +platform=system.realview +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.port[24] + [system.realview.clcd] type=Pl111 amba_id=1315089 @@ -314,7 +330,8 @@ pio_addr=268566528 pio_latency=10000 platform=system.realview system=system -dma=system.iobus.port[25] +vnc=system.vncserver +dma=system.iobus.port[26] pio=system.iobus.port[5] [system.realview.dmac_fake] @@ -388,24 +405,28 @@ pio=system.iobus.port[17] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=52 +is_mouse=false pio_addr=268460032 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[6] [system.realview.kmi1] type=Pl050 amba_id=1314896 gic=system.realview.gic -int_delay=100000 +int_delay=1000000 int_num=53 +is_mouse=true pio_addr=268464128 pio_latency=1000 platform=system.realview system=system +vnc=system.vncserver pio=system.iobus.port[7] [system.realview.l2x0_fake] @@ -591,3 +612,8 @@ use_default_range=false width=64 port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.vncserver] +type=VncServer +number=0 +port=5900 + diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index e76a50eec..1cff4671c 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -1,3 +1,5 @@ +warn: Sockets disabled, not accepting vnc client connections +For more information see: http://www.m5sim.org/warn/af6a84f6 warn: Sockets disabled, not accepting terminal connections For more information see: http://www.m5sim.org/warn/8742226b warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 994dfb6a2..2a456e7be 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -5,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Feb 7 2011 01:53:13 -M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip -M5 started Feb 7 2011 01:53:26 -M5 executing on burrito +M5 compiled Feb 11 2011 17:53:57 +M5 revision 6c65f7ee86c1 7949 default qtip tip ext/vnc_stats_updates.patch +M5 started Feb 11 2011 17:54:00 +M5 executing on u200439-lin.austin.arm.com command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 114721074000 because m5_exit instruction encountered +Exiting @ tick 114726567000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 85fb99220..c96422cfa 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,254 +1,254 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 433208 # Simulator instruction rate (inst/s) -host_mem_usage 360908 # Number of bytes of host memory used -host_seconds 116.74 # Real time elapsed on the host -host_tick_rate 982709659 # Simulator tick rate (ticks/s) +host_inst_rate 1425483 # Simulator instruction rate (inst/s) +host_mem_usage 374960 # Number of bytes of host memory used +host_seconds 35.49 # Real time elapsed on the host +host_tick_rate 3232752918 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 50572425 # Number of instructions simulated -sim_seconds 0.114721 # Number of seconds simulated -sim_ticks 114721074000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 100214 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 100214 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15147.115385 # average LoadLockedReq miss latency +sim_insts 50588397 # Number of instructions simulated +sim_seconds 0.114727 # Number of seconds simulated +sim_ticks 114726567000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100290 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100290 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14562.978560 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12147.115385 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11562.978560 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.cpu.dcache.LoadLockedReq_hits::0 95014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 95014 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 78765000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.051889 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5200 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5200 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63165000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.051889 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_hits::0 95066 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95066 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 76077000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052089 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5224 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5224 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60405000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052089 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5200 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_accesses::0 7824780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7824780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15798.342892 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5224 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310532000 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_accesses::0 7828656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7828656 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15679.539912 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12798.015358 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12679.195749 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7588163 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7588163 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3738156500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030239 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 236617 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 236617 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3028228000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030239 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7590397 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7590397 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3735791500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030434 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 238259 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 238259 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3020932500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030434 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 236617 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38190415500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 100213 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 100213 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 100213 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 100213 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6671860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6671860 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40836.063764 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 238259 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191771500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 100289 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100289 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100289 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100289 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6674369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6674369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40728.962545 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37835.781907 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37728.712808 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6499787 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499787 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7026784000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.025791 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172073 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172073 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6510516500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025791 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 6502188 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6502188 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7012753500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172181 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172181 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6496167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025797 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 172073 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926046500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 172181 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927436000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.660375 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.529769 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14496640 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14503025 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14496640 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26340.112310 # average overall miss latency +system.cpu.dcache.demand_accesses::total 14503025 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26187.859370 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14087950 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14092585 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14087950 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10764940500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028192 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 14092585 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10748545000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028300 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 408690 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 410440 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 408690 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 410440 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9538744500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028192 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 9517100000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028300 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 408690 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 410440 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 509.199113 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14496640 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 509.199247 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14503025 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14496640 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26340.112310 # average overall miss latency +system.cpu.dcache.overall_accesses::total 14503025 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26187.859370 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23339.804008 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14087950 # number of overall hits +system.cpu.dcache.overall_hits::0 14092585 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14087950 # number of overall hits -system.cpu.dcache.overall_miss_latency 10764940500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028192 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 14092585 # number of overall hits +system.cpu.dcache.overall_miss_latency 10748545000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028300 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 408690 # number of overall misses +system.cpu.dcache.overall_misses::0 410440 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 408690 # number of overall misses +system.cpu.dcache.overall_misses::total 410440 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9538744500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028192 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 9517100000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028300 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 408690 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39116462000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 410440 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39119207500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 411628 # number of replacements -system.cpu.dcache.sampled_refs 412140 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 413327 # number of replacements +system.cpu.dcache.sampled_refs 413839 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.199113 # Cycle average of tags in use -system.cpu.dcache.total_refs 14284927 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 509.199247 # Cycle average of tags in use +system.cpu.dcache.total_refs 14289765 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 382676 # number of writebacks -system.cpu.dtb.accesses 15524935 # DTB accesses +system.cpu.dcache.writebacks 381698 # number of writebacks +system.cpu.dtb.accesses 15531532 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2199 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2220 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15519414 # DTB hits +system.cpu.dtb.hits 15525999 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5521 # DTB misses +system.cpu.dtb.misses 5533 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 756 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8740303 # DTB read accesses -system.cpu.dtb.read_hits 8735762 # DTB read hits -system.cpu.dtb.read_misses 4541 # DTB read misses -system.cpu.dtb.write_accesses 6784632 # DTB write accesses -system.cpu.dtb.write_hits 6783652 # DTB write hits -system.cpu.dtb.write_misses 980 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41543801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41543801 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14800.791885 # average ReadReq miss latency +system.cpu.dtb.prefetch_faults 757 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8744287 # DTB read accesses +system.cpu.dtb.read_hits 8739733 # DTB read hits +system.cpu.dtb.read_misses 4554 # DTB read misses +system.cpu.dtb.write_accesses 6787245 # DTB write accesses +system.cpu.dtb.write_hits 6786266 # DTB write hits +system.cpu.dtb.write_misses 979 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41555414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41555414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14790.398445 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11799.492843 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11789.103925 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 41110405 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41110405 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6414604000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010432 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 433396 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433396 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5113853000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010432 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 41121276 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41121276 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6421074000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010447 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 434138 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 434138 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5118098000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010447 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 433396 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 434138 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.856667 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.719366 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41543801 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41555414 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41543801 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14800.791885 # average overall miss latency +system.cpu.icache.demand_accesses::total 41555414 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14790.398445 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41110405 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 41121276 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41110405 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6414604000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010432 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 41121276 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6421074000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010447 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 433396 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 434138 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433396 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 434138 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5113853000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010432 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 5118098000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010447 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 433396 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 434138 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.945788 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 484.243503 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41543801 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.946115 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 484.411008 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41555414 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41543801 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14800.791885 # average overall miss latency +system.cpu.icache.overall_accesses::total 41555414 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14790.398445 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11799.492843 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41110405 # number of overall hits +system.cpu.icache.overall_hits::0 41121276 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41110405 # number of overall hits -system.cpu.icache.overall_miss_latency 6414604000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010432 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 41121276 # number of overall hits +system.cpu.icache.overall_miss_latency 6421074000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010447 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 433396 # number of overall misses +system.cpu.icache.overall_misses::0 434138 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 433396 # number of overall misses +system.cpu.icache.overall_misses::total 434138 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5113853000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010432 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 5118098000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010447 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 433396 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 434138 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 432883 # number of replacements -system.cpu.icache.sampled_refs 433395 # Sample count of references to valid blocks. +system.cpu.icache.replacements 433626 # number of replacements +system.cpu.icache.sampled_refs 434138 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 484.243503 # Cycle average of tags in use -system.cpu.icache.total_refs 41110405 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 484.411008 # Cycle average of tags in use +system.cpu.icache.total_refs 41121276 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 33555 # number of writebacks +system.cpu.icache.writebacks 34007 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41546620 # DTB accesses +system.cpu.itb.accesses 41558233 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -256,9 +256,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41543801 # DTB hits -system.cpu.itb.inst_accesses 41546620 # ITB inst accesses -system.cpu.itb.inst_hits 41543801 # ITB inst hits +system.cpu.itb.hits 41555414 # DTB hits +system.cpu.itb.inst_accesses 41558233 # ITB inst accesses +system.cpu.itb.inst_hits 41555414 # ITB inst hits system.cpu.itb.inst_misses 2819 # ITB inst misses system.cpu.itb.misses 2819 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -272,10 +272,10 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 229442148 # number of cpu cycles simulated +system.cpu.numCycles 229453134 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 229442148 # Number of busy cycles +system.cpu.num_busy_cycles 229453134 # Number of busy cycles system.cpu.num_conditional_control_insts 0 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses system.cpu.num_fp_insts 6058 # number of float instructions @@ -283,14 +283,14 @@ system.cpu.num_fp_register_reads 4226 # nu system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 50572425 # Number of instructions executed -system.cpu.num_int_alu_accesses 41827211 # Number of integer alu accesses -system.cpu.num_int_insts 41827211 # number of integer instructions -system.cpu.num_int_register_reads 137988684 # number of times the integer registers were read -system.cpu.num_int_register_writes 34313952 # number of times the integer registers were written -system.cpu.num_load_insts 9208240 # Number of load instructions -system.cpu.num_mem_refs 16289993 # number of memory refs -system.cpu.num_store_insts 7081753 # Number of store instructions +system.cpu.num_insts 50588397 # Number of instructions executed +system.cpu.num_int_alu_accesses 41841366 # Number of integer alu accesses +system.cpu.num_int_insts 41841366 # number of integer instructions +system.cpu.num_int_register_reads 138034734 # number of times the integer registers were read +system.cpu.num_int_register_writes 34325875 # number of times the integer registers were written +system.cpu.num_load_insts 9211791 # Number of load instructions +system.cpu.num_mem_refs 16296219 # number of memory refs +system.cpu.num_store_insts 7084428 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -359,141 +359,141 @@ system.iocache.total_refs 0 # To system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.ReadExReq_accesses::0 170323 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170323 # number of ReadExReq accesses(hits+misses) +system.l2c.LoadLockedReq_mshr_uncacheable_latency 234360000 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.ReadExReq_accesses::0 170356 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170356 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 62071 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 62071 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.635569 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 108252 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.635569 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_hits::0 62546 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 62546 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5606120000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.632851 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107810 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107810 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4312400000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.632851 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 673101 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 5652 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 678753 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52096.523258 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 28127657.142857 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 28179753.666115 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 107810 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 675489 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 5600 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 681089 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52080.437900 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 33725803.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 33777884.009328 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 654204 # number of ReadReq hits -system.l2c.ReadReq_hits::1 5617 # number of ReadReq hits -system.l2c.ReadReq_hits::total 659821 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 984468000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.028075 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.006192 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.034267 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 18897 # number of ReadReq misses -system.l2c.ReadReq_misses::1 35 # number of ReadReq misses -system.l2c.ReadReq_misses::total 18932 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 757280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.028127 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 3.349611 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.377737 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 18932 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 29199338000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1750 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1750 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 660.126947 # average UpgradeReq miss latency +system.l2c.ReadReq_hits::0 657357 # number of ReadReq hits +system.l2c.ReadReq_hits::1 5572 # number of ReadReq hits +system.l2c.ReadReq_hits::total 662929 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 944322500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.026843 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.005000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.031843 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18132 # number of ReadReq misses +system.l2c.ReadReq_misses::1 28 # number of ReadReq misses +system.l2c.ReadReq_misses::total 18160 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 726400000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026884 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 3.242857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.269741 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18160 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 29200446000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1825 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 489.208633 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 1144000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.990286 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1733 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 69320000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.990286 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.990137 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1807 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1807 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 72280000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.990137 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1733 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1807 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 416231 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 416231 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 416231 # number of Writeback hits -system.l2c.Writeback_hits::total 416231 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 740884000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 415705 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 415705 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 415705 # number of Writeback hits +system.l2c.Writeback_hits::total 415705 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 6.975292 # Average number of references to valid blocks. +system.l2c.avg_refs 7.060757 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 843424 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 5652 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 849076 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52014.345374 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 188959200 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 189011214.345374 # average overall miss latency +system.l2c.demand_accesses::0 845845 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 5600 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 851445 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52011.580728 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 233944375 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 233996386.580728 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 716275 # number of demand (read+write) hits -system.l2c.demand_hits::1 5617 # number of demand (read+write) hits -system.l2c.demand_hits::total 721892 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6613572000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.150753 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.006192 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.156946 # miss rate for demand accesses -system.l2c.demand_misses::0 127149 # number of demand (read+write) misses -system.l2c.demand_misses::1 35 # number of demand (read+write) misses -system.l2c.demand_misses::total 127184 # number of demand (read+write) misses +system.l2c.demand_hits::0 719903 # number of demand (read+write) hits +system.l2c.demand_hits::1 5572 # number of demand (read+write) hits +system.l2c.demand_hits::total 725475 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6550442500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.148895 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.005000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.153895 # miss rate for demand accesses +system.l2c.demand_misses::0 125942 # number of demand (read+write) misses +system.l2c.demand_misses::1 28 # number of demand (read+write) misses +system.l2c.demand_misses::total 125970 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5087360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.150795 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 22.502477 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 22.653272 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 127184 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 5038800000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.148928 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 22.494643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 22.643571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 125970 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.086431 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.477933 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5664.361976 # Average occupied blocks per context -system.l2c.occ_blocks::1 31321.847814 # Average occupied blocks per context -system.l2c.overall_accesses::0 843424 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 5652 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 849076 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52014.345374 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 188959200 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 189011214.345374 # average overall miss latency +system.l2c.occ_%::0 0.081481 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.477898 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5339.953820 # Average occupied blocks per context +system.l2c.occ_blocks::1 31319.548737 # Average occupied blocks per context +system.l2c.overall_accesses::0 845845 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 5600 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 851445 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52011.580728 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 233944375 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 233996386.580728 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 716275 # number of overall hits -system.l2c.overall_hits::1 5617 # number of overall hits -system.l2c.overall_hits::total 721892 # number of overall hits -system.l2c.overall_miss_latency 6613572000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.150753 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.006192 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.156946 # miss rate for overall accesses -system.l2c.overall_misses::0 127149 # number of overall misses -system.l2c.overall_misses::1 35 # number of overall misses -system.l2c.overall_misses::total 127184 # number of overall misses +system.l2c.overall_hits::0 719903 # number of overall hits +system.l2c.overall_hits::1 5572 # number of overall hits +system.l2c.overall_hits::total 725475 # number of overall hits +system.l2c.overall_miss_latency 6550442500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.148895 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.005000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.153895 # miss rate for overall accesses +system.l2c.overall_misses::0 125942 # number of overall misses +system.l2c.overall_misses::1 28 # number of overall misses +system.l2c.overall_misses::total 125970 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5087360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.150795 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 22.502477 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 22.653272 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 127184 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29939182000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 5038800000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.148928 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 22.494643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 22.643571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 125970 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29941330000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 94170 # number of replacements -system.l2c.sampled_refs 125831 # Sample count of references to valid blocks. +system.l2c.replacements 93233 # number of replacements +system.l2c.sampled_refs 124676 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36986.209790 # Cycle average of tags in use -system.l2c.total_refs 877708 # Total number of references to valid blocks. +system.l2c.tagsinuse 36659.502556 # Cycle average of tags in use +system.l2c.total_refs 880307 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87626 # number of writebacks +system.l2c.writebacks 87349 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal Binary files differindex f3053783c..3921585df 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal |