diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/quick | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/quick')
39 files changed, 27119 insertions, 27283 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 7159169af..4c75131c1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962843 # Number of seconds simulated -sim_ticks 1962842856000 # Number of ticks simulated -final_tick 1962842856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962613 # Number of seconds simulated +sim_ticks 1962612686500 # Number of ticks simulated +final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1228880 # Simulator instruction rate (inst/s) -host_op_rate 1228880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39594262798 # Simulator tick rate (ticks/s) -host_mem_usage 373652 # Number of bytes of host memory used -host_seconds 49.57 # Real time elapsed on the host -sim_insts 60920382 # Number of instructions simulated -sim_ops 60920382 # Number of ops (including micro ops) simulated +host_inst_rate 1121045 # Simulator instruction rate (inst/s) +host_op_rate 1121044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36128483856 # Simulator tick rate (ticks/s) +host_mem_usage 373592 # Number of bytes of host memory used +host_seconds 54.32 # Real time elapsed on the host +sim_insts 60898638 # Number of instructions simulated +sim_ops 60898638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 823232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24883392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 41664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 386496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26135744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 823232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 41664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7759040 # Number of bytes written to this memory -system.physmem.bytes_written::total 7759040 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12863 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6039 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26038464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 836288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 28736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7702400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7702400 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6809 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408371 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121235 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121235 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 419408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12677221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 196906 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 406851 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120350 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120350 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 426110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12603966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222039 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13315250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 419408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3952960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3952960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3952960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 419408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12677221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 196906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13267245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 426110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3924564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3924564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3924564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 426110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12603966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222039 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17268211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408371 # Number of read requests accepted -system.physmem.writeReqs 162787 # Number of write requests accepted -system.physmem.readBursts 408371 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 162787 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26128640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 10277440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26135744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10418368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2175 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7051 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25705 # Per bank write bursts -system.physmem.perBankRdBursts::1 25985 # Per bank write bursts -system.physmem.perBankRdBursts::2 25737 # Per bank write bursts -system.physmem.perBankRdBursts::3 25534 # Per bank write bursts -system.physmem.perBankRdBursts::4 24847 # Per bank write bursts -system.physmem.perBankRdBursts::5 24754 # Per bank write bursts -system.physmem.perBankRdBursts::6 25534 # Per bank write bursts -system.physmem.perBankRdBursts::7 25489 # Per bank write bursts -system.physmem.perBankRdBursts::8 25150 # Per bank write bursts -system.physmem.perBankRdBursts::9 25518 # Per bank write bursts -system.physmem.perBankRdBursts::10 25462 # Per bank write bursts -system.physmem.perBankRdBursts::11 25296 # Per bank write bursts -system.physmem.perBankRdBursts::12 25577 # Per bank write bursts -system.physmem.perBankRdBursts::13 25454 # Per bank write bursts -system.physmem.perBankRdBursts::14 26241 # Per bank write bursts -system.physmem.perBankRdBursts::15 25977 # Per bank write bursts -system.physmem.perBankWrBursts::0 10598 # Per bank write bursts -system.physmem.perBankWrBursts::1 10761 # Per bank write bursts -system.physmem.perBankWrBursts::2 9727 # Per bank write bursts -system.physmem.perBankWrBursts::3 9433 # Per bank write bursts -system.physmem.perBankWrBursts::4 8910 # Per bank write bursts -system.physmem.perBankWrBursts::5 9140 # Per bank write bursts -system.physmem.perBankWrBursts::6 9908 # Per bank write bursts -system.physmem.perBankWrBursts::7 9771 # Per bank write bursts -system.physmem.perBankWrBursts::8 9710 # Per bank write bursts -system.physmem.perBankWrBursts::9 9867 # Per bank write bursts -system.physmem.perBankWrBursts::10 9923 # Per bank write bursts -system.physmem.perBankWrBursts::11 10306 # Per bank write bursts -system.physmem.perBankWrBursts::12 10733 # Per bank write bursts -system.physmem.perBankWrBursts::13 10678 # Per bank write bursts -system.physmem.perBankWrBursts::14 10553 # Per bank write bursts -system.physmem.perBankWrBursts::15 10567 # Per bank write bursts +system.physmem.bw_total::total 17191810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406851 # Number of read requests accepted +system.physmem.writeReqs 161902 # Number of write requests accepted +system.physmem.readBursts 406851 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 161902 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26031872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 8721536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26038464 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10361728 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25609 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 6974 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25141 # Per bank write bursts +system.physmem.perBankRdBursts::1 25398 # Per bank write bursts +system.physmem.perBankRdBursts::2 25524 # Per bank write bursts +system.physmem.perBankRdBursts::3 24918 # Per bank write bursts +system.physmem.perBankRdBursts::4 25169 # Per bank write bursts +system.physmem.perBankRdBursts::5 25258 # Per bank write bursts +system.physmem.perBankRdBursts::6 25808 # Per bank write bursts +system.physmem.perBankRdBursts::7 25541 # Per bank write bursts +system.physmem.perBankRdBursts::8 25675 # Per bank write bursts +system.physmem.perBankRdBursts::9 25330 # Per bank write bursts +system.physmem.perBankRdBursts::10 25284 # Per bank write bursts +system.physmem.perBankRdBursts::11 25615 # Per bank write bursts +system.physmem.perBankRdBursts::12 25647 # Per bank write bursts +system.physmem.perBankRdBursts::13 25653 # Per bank write bursts +system.physmem.perBankRdBursts::14 25754 # Per bank write bursts +system.physmem.perBankRdBursts::15 25033 # Per bank write bursts +system.physmem.perBankWrBursts::0 8965 # Per bank write bursts +system.physmem.perBankWrBursts::1 8625 # Per bank write bursts +system.physmem.perBankWrBursts::2 8456 # Per bank write bursts +system.physmem.perBankWrBursts::3 7799 # Per bank write bursts +system.physmem.perBankWrBursts::4 8065 # Per bank write bursts +system.physmem.perBankWrBursts::5 8041 # Per bank write bursts +system.physmem.perBankWrBursts::6 8610 # Per bank write bursts +system.physmem.perBankWrBursts::7 8172 # Per bank write bursts +system.physmem.perBankWrBursts::8 8465 # Per bank write bursts +system.physmem.perBankWrBursts::9 8053 # Per bank write bursts +system.physmem.perBankWrBursts::10 8222 # Per bank write bursts +system.physmem.perBankWrBursts::11 8481 # Per bank write bursts +system.physmem.perBankWrBursts::12 8850 # Per bank write bursts +system.physmem.perBankWrBursts::13 9510 # Per bank write bursts +system.physmem.perBankWrBursts::14 9309 # Per bank write bursts +system.physmem.perBankWrBursts::15 8651 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1962837817500 # Total gap between requests +system.physmem.numWrRetry 56 # Number of times write queue was full causing retry +system.physmem.totGap 1962566141500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408371 # Read request sizes (log2) +system.physmem.readPktSize::6 406851 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 162787 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see +system.physmem.writePktSize::6 161902 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,185 +158,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 525.203843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 317.866807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.347675 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16137 23.28% 23.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12161 17.54% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5284 7.62% 48.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3087 4.45% 52.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3309 4.77% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1757 2.53% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1519 2.19% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1296 1.87% 64.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24768 35.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69318 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5881 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.418466 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2107.784288 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5876 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5881 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5881 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.305730 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.811619 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.369719 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4828 82.09% 82.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 189 3.21% 85.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 283 4.81% 90.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 60 1.02% 91.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 106 1.80% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 43 0.73% 93.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.29% 93.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 8 0.14% 94.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 22 0.37% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.12% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 14 0.24% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.05% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 16 0.27% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.03% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 15 0.26% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 48 0.82% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 18 0.31% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 12 0.20% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 85 1.45% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 44 0.75% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 9 0.15% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 24 0.41% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.17% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5881 # Writes before turning the bus around for reads -system.physmem.totQLat 2189518000 # Total ticks spent queuing -system.physmem.totMemAccLat 9844393000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2041300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5363.05 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67633 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 513.852823 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 307.797069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.051196 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16141 23.87% 23.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12717 18.80% 42.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5311 7.85% 50.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2897 4.28% 54.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2115 3.13% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1690 2.50% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2144 3.17% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1403 2.07% 65.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23215 34.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67633 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4988 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 81.544306 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2972.635603 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4985 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4988 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4988 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.320369 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.529999 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.006905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4741 95.05% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 52 1.04% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 5 0.10% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 6 0.12% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 4 0.08% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 12 0.24% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 26 0.52% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 19 0.38% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 10 0.20% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 13 0.26% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 3 0.06% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.08% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.04% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 5 0.10% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.10% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 12 0.24% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 16 0.32% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 4 0.08% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 10 0.20% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 4 0.08% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 10 0.20% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads +system.physmem.totQLat 2137453500 # Total ticks spent queuing +system.physmem.totMemAccLat 9763978500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5254.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24113.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24004.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing -system.physmem.readRowHits 365775 # Number of row buffer hits during reads -system.physmem.writeRowHits 133752 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.28 # Row buffer hit rate for writes -system.physmem.avgGap 3436593.41 # Average gap between requests -system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 258098400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140827500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1587963000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 507047040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 65554579665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1120197596250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316449002255 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.687203 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1863305388500 # Time in different power states -system.physmem_0.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing +system.physmem.readRowHits 364433 # Number of row buffer hits during reads +system.physmem.writeRowHits 110956 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes +system.physmem.avgGap 3450647.54 # Average gap between requests +system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 66287825100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1119418909500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316300550825 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.688732 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1862013795212 # Time in different power states +system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33987247750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35060566038 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 265945680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145109250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1596465000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 533543760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65970100260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119833096250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316547150600 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.737211 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1862702158750 # Time in different power states -system.physmem_1.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66523569975 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119212115750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316364135345 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.721130 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1861673243216 # Time in different power states +system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34590463750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35401118034 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7535038 # DTB read hits -system.cpu0.dtb.read_misses 7765 # DTB read misses +system.cpu0.dtb.read_hits 7492205 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5127057 # DTB write hits -system.cpu0.dtb.write_misses 910 # DTB write misses -system.cpu0.dtb.write_acv 133 # DTB write access violations -system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12662095 # DTB hits -system.cpu0.dtb.data_misses 8675 # DTB misses -system.cpu0.dtb.data_acv 343 # DTB access violations -system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3654300 # ITB hits -system.cpu0.itb.fetch_misses 3984 # ITB misses +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 5067323 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.write_acv 134 # DTB write access violations +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.data_hits 12559528 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.data_acv 344 # DTB access violations +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3501951 # ITB hits +system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3658284 # ITB accesses +system.cpu0.itb.fetch_accesses 3505822 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -349,241 +354,240 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925685712 # number of cpu cycles simulated +system.cpu0.numCycles 3923838766 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47981838 # Number of instructions committed -system.cpu0.committedOps 47981838 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44508329 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses -system.cpu0.num_func_calls 1202945 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5633344 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44508329 # number of integer instructions -system.cpu0.num_fp_insts 212945 # number of float instructions -system.cpu0.num_int_register_reads 61205329 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33143507 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written -system.cpu0.num_mem_refs 12703139 # number of memory refs -system.cpu0.num_load_insts 7562835 # Number of load instructions -system.cpu0.num_store_insts 5140304 # Number of store instructions -system.cpu0.num_idle_cycles 3702094605.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223591106.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles -system.cpu0.Branches 7224625 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2734428 5.70% 5.70% # Class of executed instruction -system.cpu0.op_class::IntAlu 31547561 65.74% 71.43% # Class of executed instruction -system.cpu0.op_class::IntMult 52422 0.11% 71.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::MemRead 7738872 16.13% 87.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 5146421 10.72% 98.45% # Class of executed instruction -system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction +system.cpu0.committedInsts 47743384 # Number of instructions committed +system.cpu0.committedOps 47743384 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44279734 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210698 # Number of float alu accesses +system.cpu0.num_func_calls 1202353 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5609016 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44279734 # number of integer instructions +system.cpu0.num_fp_insts 210698 # number of float instructions +system.cpu0.num_int_register_reads 60867436 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32999466 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102334 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104190 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599731 # number of memory refs +system.cpu0.num_load_insts 7519361 # Number of load instructions +system.cpu0.num_store_insts 5080370 # Number of store instructions +system.cpu0.num_idle_cycles 3698952400.393103 # Number of idle cycles +system.cpu0.num_busy_cycles 224886365.606898 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057313 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942687 # Percentage of idle cycles +system.cpu0.Branches 7198745 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2727567 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31426598 65.81% 71.52% # Class of executed instruction +system.cpu0.op_class::IntMult 52886 0.11% 71.63% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25715 0.05% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::MemRead 7694830 16.11% 87.81% # Class of executed instruction +system.cpu0.op_class::MemWrite 5086464 10.65% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 736268 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47990856 # Class of executed instruction +system.cpu0.op_class::total 47751984 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164994 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56858 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 421 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82092 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141475 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56322 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903333022000 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94388000 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 768238500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314332500 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58332103000 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962842084000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 421 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55901 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114748 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900658476000 96.88% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90840500 0.00% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 754578500 0.04% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 304090000 0.02% 96.94% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60111368000 3.06% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961919353000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990573 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.680956 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811083 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed -system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149871 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches +system.cpu0.kern.callpal::swpctx 3067 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134616 89.86% 92.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149812 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6888 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186121 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959061538500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3780541000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313831 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958151397500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3535867500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3098 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1190069 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.197532 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11466522 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1190581 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.631031 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.197532 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986714 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986714 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51892703 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51892703 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6451021 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6451021 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4712504 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4712504 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140772 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140772 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148353 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148353 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11163525 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11163525 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11163525 # number of overall hits -system.cpu0.dcache.overall_hits::total 11163525 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942274 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942274 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 257633 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 257633 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13709 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13709 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5579 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5579 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1199907 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1199907 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1199907 # number of overall misses -system.cpu0.dcache.overall_misses::total 1199907 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27224956000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27224956000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10342084186 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10342084186 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150000000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150000000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42703895 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 42703895 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37567040186 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37567040186 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37567040186 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37567040186 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7393295 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7393295 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970137 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4970137 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154481 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154481 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153932 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153932 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12363432 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12363432 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12363432 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12363432 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127450 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127450 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088742 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088742 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036243 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036243 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097053 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097053 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097053 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097053 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28892.823107 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28892.823107 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40142.699833 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40142.699833 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.717120 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.717120 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7654.399534 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7654.399534 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31308.293214 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31308.293214 # average overall miss latency +system.cpu0.kern.swap_context 3068 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1180939 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.262035 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11368359 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1181356 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.623144 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.262035 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986840 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986840 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51471280 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51471280 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6411907 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6411907 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4659091 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4659091 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140391 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140391 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148074 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148074 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11070998 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11070998 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11070998 # number of overall hits +system.cpu0.dcache.overall_hits::total 11070998 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938638 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938638 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251661 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251661 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13662 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1190299 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1190299 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1190299 # number of overall misses +system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906399185 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10906399185 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 39966790184 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 39966790184 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 39966790184 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 39966790184 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4910752 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154053 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154053 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12261297 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12261297 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12261297 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12261297 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127696 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127696 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051247 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051247 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088684 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088684 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035374 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035374 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097078 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097078 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097078 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097078 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.661318 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.661318 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8936.536280 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8936.536280 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33577.101370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33577.101370 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,62 +596,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 685914 # number of writebacks -system.cpu0.dcache.writebacks::total 685914 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942274 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 942274 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257633 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 257633 # 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average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 679102 # number of writebacks +system.cpu0.dcache.writebacks::total 679102 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938638 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938638 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251661 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251661 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13662 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13662 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1190299 # 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number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003531316 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38003531316 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003531316 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38003531316 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293895500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293895500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768311500 # 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Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48691282 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48691282 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47290432 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47290432 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47290432 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47290432 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47290432 # number of overall hits -system.cpu0.icache.overall_hits::total 47290432 # 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number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47990857 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47990857 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47990857 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47990857 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47990857 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47990857 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14228.438085 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14228.438085 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14228.438085 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14228.438085 # average overall miss latency +system.cpu0.icache.tags.replacements 698758 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47052596 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 699270 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.288166 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42435665250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.155937 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992492 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992492 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 48451372 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48451372 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47052596 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47052596 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47052596 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47052596 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47052596 # number of overall hits +system.cpu0.icache.overall_hits::total 47052596 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 699388 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 699388 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 699388 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 699388 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 699388 # number of overall misses +system.cpu0.icache.overall_misses::total 699388 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10012837997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10012837997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10012837997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10012837997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10012837997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10012837997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47751984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47751984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47751984 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47751984 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47751984 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47751984 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014646 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014646 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014646 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014646 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014646 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014646 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14316.571055 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14316.571055 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,51 +718,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700425 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700425 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700425 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700425 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700425 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700425 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8560109254 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8560109254 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8560109254 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8560109254 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8560109254 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8560109254 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.307426 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699388 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 699388 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 699388 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 699388 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 699388 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 699388 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8958710003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8958710003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8958710003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8958710003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8958710003 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8958710003 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014646 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014646 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2381610 # DTB read hits -system.cpu1.dtb.read_misses 2620 # DTB read misses +system.cpu1.dtb.read_hits 2419579 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1701782 # DTB write hits -system.cpu1.dtb.write_misses 235 # DTB write misses -system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4083392 # DTB hits -system.cpu1.dtb.data_misses 2855 # DTB misses -system.cpu1.dtb.data_acv 24 # DTB access violations -system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1808769 # ITB hits -system.cpu1.itb.fetch_misses 1064 # ITB misses +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.write_hits 1757217 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.write_acv 29 # DTB write access violations +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.data_hits 4176796 # DTB hits +system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.data_acv 29 # DTB access violations +system.cpu1.dtb.data_accesses 344610 # DTB accesses +system.cpu1.itb.fetch_hits 1964101 # ITB hits +system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1809833 # ITB accesses +system.cpu1.itb.fetch_accesses 1965317 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -773,219 +775,220 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923834021 # number of cpu cycles simulated +system.cpu1.numCycles 3925225373 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12938544 # Number of instructions committed -system.cpu1.committedOps 12938544 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11924615 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses -system.cpu1.num_func_calls 411382 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1282019 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11924615 # number of integer instructions -system.cpu1.num_fp_insts 171199 # number of float instructions -system.cpu1.num_int_register_reads 16391744 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8774012 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written -system.cpu1.num_mem_refs 4106042 # number of memory refs -system.cpu1.num_load_insts 2395192 # Number of load instructions -system.cpu1.num_store_insts 1710850 # Number of store instructions -system.cpu1.num_idle_cycles 3874343491.006502 # Number of idle cycles -system.cpu1.num_busy_cycles 49490529.993498 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles -system.cpu1.Branches 1847277 # Number of branches fetched -system.cpu1.op_class::No_OpClass 699299 5.40% 5.40% # Class of executed instruction -system.cpu1.op_class::IntAlu 7669413 59.26% 64.67% # Class of executed instruction -system.cpu1.op_class::IntMult 22263 0.17% 64.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13113 0.10% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::MemRead 2466523 19.06% 84.01% # Class of executed instruction -system.cpu1.op_class::MemWrite 1711831 13.23% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 357222 2.76% 100.00% # Class of executed instruction +system.cpu1.committedInsts 13155254 # Number of instructions committed +system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses +system.cpu1.num_func_calls 411301 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12132982 # number of integer instructions +system.cpu1.num_fp_insts 173111 # number of float instructions +system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written +system.cpu1.num_mem_refs 4200357 # number of memory refs +system.cpu1.num_load_insts 2433886 # Number of load instructions +system.cpu1.num_store_insts 1766471 # Number of store instructions +system.cpu1.num_idle_cycles 3876126897.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49098475.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles +system.cpu1.Branches 1871330 # Number of branches fetched +system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction +system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction +system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 12941423 # Class of executed instruction +system.cpu1.op_class::total 13158616 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77895 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26463 38.26% 38.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40215 58.15% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69160 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25619 48.15% 48.15% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25107 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53208 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1910451046000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 701160000 0.04% 97.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 358891000 0.02% 97.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50405883500 2.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961916980500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968106 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.624319 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769346 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62985 88.13% 91.49% # number of callpals executed -system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed +system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71468 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches -system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 804 -system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 436 -system.cpu1.kern.mode_switch_good::kernel 0.418097 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71473 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 890 +system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.mode_good::idle 427 +system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309648 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17982324500 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1495094500 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941563117500 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1968 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 157282 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.069018 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3911225 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 157609 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.816000 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048852201500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.069018 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949354 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949354 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16556980 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16556980 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2220683 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2220683 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1590246 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1590246 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47776 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47776 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50237 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50237 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3810929 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3810929 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3810929 # number of overall hits -system.cpu1.dcache.overall_hits::total 3810929 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 57138 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 57138 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8903 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5967 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5967 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 172235 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 172235 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 172235 # number of overall misses -system.cpu1.dcache.overall_misses::total 172235 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1388298999 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1388298999 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079375302 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1079375302 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80583500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80583500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43835417 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 43835417 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2467674301 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2467674301 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2467674301 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2467674301 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2335780 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2335780 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647384 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1647384 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56679 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 56679 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56204 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56204 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3983164 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3983164 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3983164 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3983164 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049276 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049276 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034684 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034684 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157078 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157078 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106167 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106167 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043241 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043241 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043241 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043241 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.991181 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.991181 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18890.673492 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18890.673492 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9051.274851 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9051.274851 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.307525 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.307525 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14327.368427 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14327.368427 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.148418 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329386 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17700699500 0.90% 0.90% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1706728000 0.09% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1943204535000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1998 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 166165 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.164459 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4008469 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 166677 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.049323 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 79256927000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.164459 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947587 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16941101 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16941101 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2255044 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2255044 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1640007 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1640007 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48683 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48683 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50718 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50718 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3895051 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3895051 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3895051 # number of overall hits +system.cpu1.dcache.overall_hits::total 3895051 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118164 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118164 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62534 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62534 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8914 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8914 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5850 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5850 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses +system.cpu1.dcache.overall_misses::total 180698 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81194500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 81194500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1702541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1702541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56568 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56568 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4075749 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4075749 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4075749 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4075749 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049791 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049791 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036730 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036730 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154765 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154765 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103415 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103415 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.649316 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.649316 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -994,62 +997,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 107942 # number of writebacks -system.cpu1.dcache.writebacks::total 107942 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57138 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 57138 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8903 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8903 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5967 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5967 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 172235 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 172235 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 172235 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 172235 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1158014001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1158014001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962534698 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962534698 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62777500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62777500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31899583 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31899583 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2120548699 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2120548699 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2120548699 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2120548699 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726754500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726754500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749201000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749201000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049276 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049276 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034684 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034684 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157078 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157078 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106167 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043241 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043241 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.200561 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.200561 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16845.789107 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16845.789107 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7051.274851 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7051.274851 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5346.000168 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5346.000168 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 114146 # number of writebacks +system.cpu1.dcache.writebacks::total 114146 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118164 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118164 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62534 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62534 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67823500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67823500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18864000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18864000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716373000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716373000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735237000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735237000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.649316 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.649316 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1057,58 +1060,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 318148 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.541580 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12622723 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 318660 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.611884 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1956986313500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541580 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 315648 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870960 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870960 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13260123 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13260123 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12622723 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12622723 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12622723 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12622723 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12622723 # number of overall hits -system.cpu1.icache.overall_hits::total 12622723 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 318700 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 318700 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 318700 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 318700 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 318700 # number of overall misses -system.cpu1.icache.overall_misses::total 318700 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4202225742 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4202225742 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4202225742 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4202225742 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4202225742 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4202225742 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12941423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12941423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12941423 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12941423 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12941423 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12941423 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024626 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024626 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024626 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024626 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024626 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024626 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13185.521625 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13185.521625 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13185.521625 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13185.521625 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13474819 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13474819 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12842415 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12842415 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12842415 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12842415 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12842415 # number of overall hits +system.cpu1.icache.overall_hits::total 12842415 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316202 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316202 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316202 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316202 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316202 # number of overall misses +system.cpu1.icache.overall_misses::total 316202 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4145253739 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4145253739 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4145253739 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4145253739 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4145253739 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4145253739 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13158617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13158617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13158617 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13158617 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13158617 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13158617 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024030 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024030 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024030 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024030 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024030 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1117,30 +1121,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318700 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 318700 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 318700 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 318700 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 318700 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 318700 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3564575258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3564575258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3564575258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3564575258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3564575258 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3564575258 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024626 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024626 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024626 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11184.735670 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316202 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316202 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316202 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316202 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316202 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316202 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3670775261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3670775261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3670775261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1156,11 +1160,11 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55631 # Transaction distribution -system.iobus.trans_dist::WriteResp 14079 # Transaction distribution +system.iobus.trans_dist::WriteReq 55604 # Transaction distribution +system.iobus.trans_dist::WriteResp 14052 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1171,12 +1175,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1187,13 +1191,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82034 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743666 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13305000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 81834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743450 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13247000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1213,52 +1217,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406213784 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242106937 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28473000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28450000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42027500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.577776 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.567924 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755504098000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.577776 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.036111 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.036111 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756483552000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.567924 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035495 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035495 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses -system.iocache.demand_misses::total 176 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 176 # number of overall misses -system.iocache.overall_misses::total 176 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634467901 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634467901 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses +system.iocache.demand_misses::total 174 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 174 # number of overall misses +system.iocache.overall_misses::total 174 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21822883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21822883 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775454554 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8775454554 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21822883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21822883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21822883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21822883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1267,40 +1271,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328130.244056 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328130.244056 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206274 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125418.867816 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125418.867816 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125418.867816 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72753 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23554 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9972 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.757493 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.295728 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473763901 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473763901 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12615883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12615883 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6614750554 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6614750554 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12615883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12615883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12615883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12615883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1309,189 +1313,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276130.244056 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276130.244056 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 342765 # number of replacements -system.l2c.tags.tagsinuse 65220.427494 # Cycle average of tags in use -system.l2c.tags.total_refs 2449404 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407938 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.004354 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55273.007246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4809.132503 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4932.058830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 161.965185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 44.263730 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073382 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002471 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 767 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7222 # 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number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 129887 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 42518 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172405 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 687538 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 798040 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 318040 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 147752 # number of demand (read+write) hits -system.l2c.demand_hits::total 1951370 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 687538 # number of overall hits -system.l2c.overall_hits::cpu0.data 798040 # number of overall hits -system.l2c.overall_hits::cpu1.inst 318040 # number of overall hits -system.l2c.overall_hits::cpu1.data 147752 # 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number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 21179000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18676711000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1101962 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10166561 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11268523 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 873463 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 278988 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1152451 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8137748269 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 426449979 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8564198248 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 942533250 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 105527 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2064334 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 793856 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 793856 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3137 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2324 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5461 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 938 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 940 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1878 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 247869 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 48299 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296168 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 700404 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1187573 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 318699 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 153826 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2360502 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 700404 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1187573 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 318699 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 153826 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2360502 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018369 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.288975 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.002068 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002777 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138238 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942939 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.766781 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.867973 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.954158 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975532 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.964856 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.475985 # 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average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65053.255190 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72416.160850 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 72283.276451 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 65447.581903 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 372.536173 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5705.140853 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2377.325527 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 975.936313 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 304.239913 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 636.010486 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68974.489914 # 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number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15561750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 17240533500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51864446 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 30663235 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 82527681 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15769892 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15706897 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 31476789 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347142739 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457723764 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7804866503 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 888765750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 23652210239 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 31138500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 473285514 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 25045400003 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 888765750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 23652210239 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 31138500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 473285514 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 25045400003 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1374876000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17618000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1392494000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153053500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674538500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2827592000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527929500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4220086000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290186 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002148 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138498 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941571 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768142 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868880 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961207 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967550 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477466 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122420 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412904 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172964 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172964 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60025.429251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66503.205128 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60411.279811 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17587.129875 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.757020 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.249779 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1626,96 +1630,96 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292731 # Transaction distribution -system.membus.trans_dist::ReadResp 292731 # Transaction distribution -system.membus.trans_dist::WriteReq 14079 # Transaction distribution -system.membus.trans_dist::WriteResp 14079 # Transaction distribution -system.membus.trans_dist::Writeback 121235 # Transaction distribution +system.membus.trans_dist::ReadReq 292759 # Transaction distribution +system.membus.trans_dist::ReadResp 292759 # Transaction distribution +system.membus.trans_dist::WriteReq 14052 # Transaction distribution +system.membus.trans_dist::WriteResp 14052 # Transaction distribution +system.membus.trans_dist::Writeback 120350 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16420 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11480 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7054 # Transaction distribution -system.membus.trans_dist::ReadExReq 124107 # Transaction distribution -system.membus.trans_dist::ReadExResp 123261 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932487 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 975039 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1099854 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31236544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31318578 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution +system.membus.trans_dist::ReadExReq 122543 # Transaction distribution +system.membus.trans_dist::ReadExResp 121713 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36636146 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22119 # Total snoops (count) -system.membus.snoop_fanout::samples 600328 # Request fanout histogram +system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21558 # Total snoops (count) +system.membus.snoop_fanout::samples 597341 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600328 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600328 # Request fanout histogram -system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 597341 # Request fanout histogram +system.membus.reqLayer0.occupancy 40208500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1915022000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3840524699 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2189522527 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2106481 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106466 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793856 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16639 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11546 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28185 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298132 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298132 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400829 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132611 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637399 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5629835 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44825856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119969536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20396736 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201971250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 99473 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3261009 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112394 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 98552 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3219281 98.72% 98.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3261009 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4802800383 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3154409746 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5532665081 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1434275242 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 787817718 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1901998576 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 474390739 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 282399146 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5c3a9c7d0..d63246d54 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920419 # Number of seconds simulated -sim_ticks 1920418772000 # Number of ticks simulated -final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.922414 # Number of seconds simulated +sim_ticks 1922413663500 # Number of ticks simulated +final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1235696 # Simulator instruction rate (inst/s) -host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42298287542 # Simulator tick rate (ticks/s) -host_mem_usage 370580 # Number of bytes of host memory used -host_seconds 45.40 # Real time elapsed on the host -sim_insts 56102800 # Number of instructions simulated -sim_ops 56102800 # Number of ops (including micro ops) simulated +host_inst_rate 1122927 # Simulator instruction rate (inst/s) +host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38428929684 # Simulator tick rate (ticks/s) +host_mem_usage 370248 # Number of bytes of host memory used +host_seconds 50.03 # Real time elapsed on the host +sim_insts 56174594 # Number of instructions simulated +sim_ops 56174594 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory -system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388431 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401711 # Number of read requests accepted -system.physmem.writeReqs 157234 # Number of write requests accepted -system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue -system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one +system.physmem.num_reads::total 401737 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12931444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13374420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442477 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442477 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3851591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3851591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3851591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12931444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17226012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401737 # Number of read requests accepted +system.physmem.writeReqs 157245 # Number of write requests accepted +system.physmem.readBursts 401737 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157245 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25705152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue +system.physmem.bytesWritten 8387264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25711168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10063680 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26167 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25160 # Per bank write bursts -system.physmem.perBankRdBursts::1 25539 # Per bank write bursts -system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::0 25230 # Per bank write bursts +system.physmem.perBankRdBursts::1 25660 # Per bank write bursts +system.physmem.perBankRdBursts::2 25603 # Per bank write bursts system.physmem.perBankRdBursts::3 25523 # Per bank write bursts -system.physmem.perBankRdBursts::4 24974 # Per bank write bursts -system.physmem.perBankRdBursts::5 24969 # Per bank write bursts -system.physmem.perBankRdBursts::6 24210 # Per bank write bursts -system.physmem.perBankRdBursts::7 24487 # Per bank write bursts -system.physmem.perBankRdBursts::8 25140 # Per bank write bursts -system.physmem.perBankRdBursts::9 24800 # Per bank write bursts -system.physmem.perBankRdBursts::10 25360 # Per bank write bursts -system.physmem.perBankRdBursts::11 24834 # Per bank write bursts -system.physmem.perBankRdBursts::12 24395 # Per bank write bursts -system.physmem.perBankRdBursts::13 25368 # Per bank write bursts -system.physmem.perBankRdBursts::14 25772 # Per bank write bursts -system.physmem.perBankRdBursts::15 25477 # Per bank write bursts -system.physmem.perBankWrBursts::0 10048 # Per bank write bursts -system.physmem.perBankWrBursts::1 9910 # Per bank write bursts -system.physmem.perBankWrBursts::2 10442 # Per bank write bursts -system.physmem.perBankWrBursts::3 9959 # Per bank write bursts -system.physmem.perBankWrBursts::4 9552 # Per bank write bursts -system.physmem.perBankWrBursts::5 9342 # Per bank write bursts -system.physmem.perBankWrBursts::6 8789 # Per bank write bursts -system.physmem.perBankWrBursts::7 8561 # Per bank write bursts -system.physmem.perBankWrBursts::8 9905 # Per bank write bursts -system.physmem.perBankWrBursts::9 8742 # Per bank write bursts -system.physmem.perBankWrBursts::10 9526 # Per bank write bursts -system.physmem.perBankWrBursts::11 9262 # Per bank write bursts -system.physmem.perBankWrBursts::12 9811 # Per bank write bursts -system.physmem.perBankWrBursts::13 10568 # Per bank write bursts -system.physmem.perBankWrBursts::14 10305 # Per bank write bursts -system.physmem.perBankWrBursts::15 10316 # Per bank write bursts +system.physmem.perBankRdBursts::4 24970 # Per bank write bursts +system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.perBankRdBursts::6 24206 # Per bank write bursts +system.physmem.perBankRdBursts::7 24492 # Per bank write bursts +system.physmem.perBankRdBursts::8 25173 # Per bank write bursts +system.physmem.perBankRdBursts::9 24777 # Per bank write bursts +system.physmem.perBankRdBursts::10 25267 # Per bank write bursts +system.physmem.perBankRdBursts::11 24875 # Per bank write bursts +system.physmem.perBankRdBursts::12 24505 # Per bank write bursts +system.physmem.perBankRdBursts::13 25378 # Per bank write bursts +system.physmem.perBankRdBursts::14 25651 # Per bank write bursts +system.physmem.perBankRdBursts::15 25357 # Per bank write bursts +system.physmem.perBankWrBursts::0 8677 # Per bank write bursts +system.physmem.perBankWrBursts::1 8490 # Per bank write bursts +system.physmem.perBankWrBursts::2 8972 # Per bank write bursts +system.physmem.perBankWrBursts::3 8549 # Per bank write bursts +system.physmem.perBankWrBursts::4 8030 # Per bank write bursts +system.physmem.perBankWrBursts::5 7962 # Per bank write bursts +system.physmem.perBankWrBursts::6 7256 # Per bank write bursts +system.physmem.perBankWrBursts::7 7133 # Per bank write bursts +system.physmem.perBankWrBursts::8 8241 # Per bank write bursts +system.physmem.perBankWrBursts::9 7447 # Per bank write bursts +system.physmem.perBankWrBursts::10 7887 # Per bank write bursts +system.physmem.perBankWrBursts::11 7738 # Per bank write bursts +system.physmem.perBankWrBursts::12 8187 # Per bank write bursts +system.physmem.perBankWrBursts::13 8962 # Per bank write bursts +system.physmem.perBankWrBursts::14 8876 # Per bank write bursts +system.physmem.perBankWrBursts::15 8644 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1920406851000 # Total gap between requests +system.physmem.numWrRetry 46 # Number of times write queue was full causing retry +system.physmem.totGap 1922401791500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401711 # Read request sizes (log2) +system.physmem.readPktSize::6 401737 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157234 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401596 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157245 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401629 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,184 +148,189 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15015 22.60% 22.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11499 17.30% 39.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4712 7.09% 46.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3144 4.73% 51.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3072 4.62% 56.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1860 2.80% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1297 1.95% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1463 2.20% 63.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5539 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5536 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.491275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.634857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.364161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14682 22.67% 22.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11626 17.95% 40.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5040 7.78% 48.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3263 5.04% 53.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2595 4.01% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1540 2.38% 59.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1251 1.93% 61.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1707 2.64% 64.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23050 35.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64754 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4707 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 85.326110 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3076.141166 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4704 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5539 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5539 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.990251 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.086567 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.704660 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4497 81.19% 81.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 178 3.21% 84.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 301 5.43% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 51 0.92% 90.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 99 1.79% 92.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 47 0.85% 93.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.31% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.20% 93.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 12 0.22% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.07% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 17 0.31% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 7 0.13% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 6 0.11% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 9 0.16% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 38 0.69% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.29% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.34% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 88 1.59% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.20% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 20 0.36% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.18% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.07% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads -system.physmem.totQLat 2115529750 # Total ticks spent queuing -system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4707 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.841725 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.684188 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.214453 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4459 94.73% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 47 1.00% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 10 0.21% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 2 0.04% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 12 0.25% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 3 0.06% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 7 0.15% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.36% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 21 0.45% 97.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 12 0.25% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 17 0.36% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 2 0.04% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.11% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.06% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.02% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.04% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.08% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 11 0.23% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 21 0.45% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 6 0.13% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.13% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 6 0.13% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 8 0.17% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.04% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.11% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 3 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::800-815 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::832-847 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4707 # Writes before turning the bus around for reads +system.physmem.totQLat 2057087750 # Total ticks spent queuing +system.physmem.totMemAccLat 9587894000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2008215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5121.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23871.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.23 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing -system.physmem.readRowHits 359951 # Number of row buffer hits during reads -system.physmem.writeRowHits 130246 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes -system.physmem.avgGap 3435770.69 # Average gap between requests -system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.686102 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states -system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem.avgWrQLen 25.61 # Average write queue length when enqueuing +system.physmem.readRowHits 360176 # Number of row buffer hits during reads +system.physmem.writeRowHits 107764 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.21 # Row buffer hit rate for writes +system.physmem.avgGap 3439112.16 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 240309720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131121375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1565148000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 421647120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64744742475 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1096652245500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1289317661070 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.677845 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1824141880650 # Time in different power states +system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34074451850 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.730762 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states -system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem_1.actEnergy 249230520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135988875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567667400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 427563360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65411599725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1096067283000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1289421779760 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.732006 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1823167298902 # Time in different power states +system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35049033598 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052701 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9063642 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6349364 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6355525 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15402065 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15419167 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973977 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4974414 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978974 # ITB accesses +system.cpu.itb.fetch_accesses 4979424 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -338,87 +343,87 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840837544 # number of cpu cycles simulated +system.cpu.numCycles 3844827327 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56102800 # Number of instructions committed -system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1481300 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls -system.cpu.num_int_insts 51978055 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read -system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15454652 # number of memory refs -system.cpu.num_load_insts 9089529 # Number of load instructions -system.cpu.num_store_insts 6365123 # Number of store instructions -system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934485 # Percentage of idle cycles -system.cpu.Branches 8412940 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction +system.cpu.committedInsts 56174594 # Number of instructions committed +system.cpu.committedOps 56174594 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52047018 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1483106 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6467546 # number of instructions that are conditional controls +system.cpu.num_int_insts 52047018 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71310653 # number of times the integer registers were read +system.cpu.num_int_register_writes 38515122 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15471782 # number of memory refs +system.cpu.num_load_insts 9100493 # Number of load instructions +system.cpu.num_store_insts 6371289 # Number of store instructions +system.cpu.num_idle_cycles 3587399919.998134 # Number of idle cycles +system.cpu.num_busy_cycles 257427407.001866 # Number of busy cycles +system.cpu.not_idle_fraction 0.066954 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933046 # Percentage of idle cycles +system.cpu.Branches 8421188 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200330 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36225212 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61016 0.11% 70.28% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::MemRead 9327578 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6377363 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953205 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56114619 # Class of executed instruction +system.cpu.op_class::total 56186427 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211986 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106213 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149113 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857939859000 96.65% 96.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91692000 0.00% 96.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 740049500 0.04% 96.69% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 63641329000 3.31% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1922412929500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692241 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814078 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -454,10 +459,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175947 91.21% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -466,101 +471,101 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192900 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1743 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1743 +system.cpu.kern.callpal::total 192894 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323455 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1389979 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392197 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46428613000 2.42% 2.42% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5237727500 0.27% 2.69% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1870746587000 97.31% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1391374 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978196 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14046325 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391886 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.091577 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978196 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7802731 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845607 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183026 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13648338 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13648338 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13648338 # number of overall hits -system.cpu.dcache.overall_hits::total 13648338 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304189 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304189 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17217 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17217 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373292 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373292 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373292 # number of overall misses -system.cpu.dcache.overall_misses::total 1373292 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29000817500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29000817500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906930630 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10906930630 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228178000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228178000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39907748130 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39907748130 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39907748130 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39907748130 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8871834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8871834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6149796 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6149796 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15021630 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15021630 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15021630 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15021630 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120505 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120505 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049463 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049463 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085981 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085981 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091421 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091421 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091421 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091421 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27126.308223 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.769374 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13253.063832 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29059.914519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63144735 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63144735 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7812525 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7812525 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5851580 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5851580 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182969 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182969 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199234 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199234 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13664105 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13664105 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13664105 # number of overall hits +system.cpu.dcache.overall_hits::total 13664105 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1070248 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1070248 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304369 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304369 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17287 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17287 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374617 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374617 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374617 # number of overall misses +system.cpu.dcache.overall_misses::total 1374617 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30897353500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30897353500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11699394130 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11699394130 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229714500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229714500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42596747630 # 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miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091405 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091405 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38438.192227 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13288.280211 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30988.084412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30988.084412 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -569,54 +574,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834368 # number of writebacks -system.cpu.dcache.writebacks::total 834368 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069103 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245884370 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36982839870 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36982839870 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36982839870 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36982839870 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424272500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424272500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009399000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009399000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433671500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433671500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049463 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049463 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091421 # 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average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835634 # number of writebacks +system.cpu.dcache.writebacks::total 835634 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1070248 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1070248 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17287 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17287 # 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number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40356234870 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40356234870 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2025445000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2025445000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3458204000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3458204000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086325 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086325 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091405 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091405 # 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average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -624,59 +629,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 927664 # number of replacements -system.cpu.icache.tags.tagsinuse 508.305908 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55186285 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928175 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.456767 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.305908 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992785 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992785 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928205 # number of replacements +system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55257552 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928716 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.498869 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42087191250 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23773879119 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24671360619 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 897481500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23773879119 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24671360619 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1335739000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1335739000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1899995000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1899995000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3235734000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3235734000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141468 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -889,41 +894,41 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41901 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41937 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113522 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41761 1.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -996,23 +1001,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1026,14 +1031,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1050,19 +1055,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1076,14 +1081,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1092,57 +1097,57 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292351 # Transaction distribution -system.membus.trans_dist::ReadResp 292351 # Transaction distribution +system.membus.trans_dist::ReadReq 292358 # Transaction distribution +system.membus.trans_dist::ReadResp 292358 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115682 # Transaction distribution +system.membus.trans_dist::Writeback 115693 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116719 # Transaction distribution -system.membus.trans_dist::ReadExResp 116719 # Transaction distribution +system.membus.trans_dist::ReadExReq 116738 # Transaction distribution +system.membus.trans_dist::ReadExResp 116738 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 559506 # Request fanout histogram +system.membus.snoop_fanout::samples 559589 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 559506 # Request fanout histogram -system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 559589 # Request fanout histogram +system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index def60114c..cb5fe02ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.802895 # Number of seconds simulated -sim_ticks 2802895103500 # Number of ticks simulated -final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2802894699500 # Number of ticks simulated +final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 834307 # Simulator instruction rate (inst/s) -host_op_rate 1016590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15926512431 # Simulator tick rate (ticks/s) -host_mem_usage 572876 # Number of bytes of host memory used -host_seconds 175.99 # Real time elapsed on the host -sim_insts 146829031 # Number of instructions simulated -sim_ops 178908942 # Number of ops (including micro ops) simulated +host_inst_rate 1337323 # Simulator instruction rate (inst/s) +host_op_rate 1629508 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25528979782 # Simulator tick rate (ticks/s) +host_mem_usage 626168 # Number of bytes of host memory used +host_seconds 109.79 # Real time elapsed on the host +sim_insts 146828240 # Number of instructions simulated +sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1117604 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9440956 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 152404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1082016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 152020 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081568 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11794004 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1117540 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 152404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1269944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8387200 # Number of bytes written to this memory +system.physmem.bytes_read::total 11793812 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1117604 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 152020 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1269624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8390656 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8404944 # Number of bytes written to this memory +system.physmem.bytes_written::total 8408400 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25915 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 148040 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2536 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16930 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16923 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131050 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193435 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131104 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135486 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135540 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 398709 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3368082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 398732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3368288 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385875 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4207794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 398709 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54374 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 453083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2992335 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4207726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 398732 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 452969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2993568 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2998665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2992335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2999899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2993568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 398709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3374398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 398732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3374604 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 385890 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7206459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7207624 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -142,9 +142,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339962 # DTB read hits +system.cpu0.dtb.read_hits 20339720 # DTB read hits system.cpu0.dtb.read_misses 6874 # DTB read misses -system.cpu0.dtb.write_hits 16391171 # DTB write hits +system.cpu0.dtb.write_hits 16391078 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -155,12 +155,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346836 # DTB read accesses -system.cpu0.dtb.write_accesses 16392264 # DTB write accesses +system.cpu0.dtb.read_accesses 20346594 # DTB read accesses +system.cpu0.dtb.write_accesses 16392171 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36731133 # DTB hits +system.cpu0.dtb.hits 36730798 # DTB hits system.cpu0.dtb.misses 7967 # DTB misses -system.cpu0.dtb.accesses 36739100 # DTB accesses +system.cpu0.dtb.accesses 36738765 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -208,7 +208,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 97440315 # ITB inst hits +system.cpu0.itb.inst_hits 97439331 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -225,37 +225,37 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97443673 # ITB inst accesses -system.cpu0.itb.hits 97440315 # DTB hits +system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses +system.cpu0.itb.hits 97439331 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97443673 # DTB accesses -system.cpu0.numCycles 5605792176 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442689 # DTB accesses +system.cpu0.numCycles 5605791368 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 95427853 # Number of instructions committed -system.cpu0.committedOps 115561498 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100763618 # Number of integer alu accesses +system.cpu0.committedInsts 95426926 # Number of instructions committed +system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000324 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204344 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100763618 # number of integer instructions +system.cpu0.num_func_calls 8000180 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762696 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182459108 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69136203 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349974767 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907843 # number of times the CC registers were written -system.cpu0.num_mem_refs 37874145 # number of memory refs -system.cpu0.num_load_insts 20597552 # Number of load instructions -system.cpu0.num_store_insts 17276593 # Number of store instructions -system.cpu0.num_idle_cycles 5488206556.246817 # Number of idle cycles -system.cpu0.num_busy_cycles 117585619.753183 # Number of busy cycles +system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873810 # number of memory refs +system.cpu0.num_load_insts 20597310 # Number of load instructions +system.cpu0.num_store_insts 17276500 # Number of store instructions +system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles +system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941792 # Number of branches fetched +system.cpu0.Branches 21941499 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78888049 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction @@ -284,20 +284,20 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597552 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276593 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116883193 # Class of executed instruction +system.cpu0.op_class::total 116882065 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 693476 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853661 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932684 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693988 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.777097 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 693477 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853657 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932369 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693989 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.776569 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853661 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853657 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -305,50 +305,50 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74114402 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74114402 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108775 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108775 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690454 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690454 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 74113775 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113775 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108539 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108539 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690376 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690376 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363052 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363052 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34799229 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34799229 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145322 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145322 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373098 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373098 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295765 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295765 # number of WriteReq misses +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363049 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363049 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798915 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798915 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145008 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145008 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373099 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373099 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295764 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295764 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18433 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18433 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18436 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18436 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 668863 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 769184 # number of overall misses system.cpu0.dcache.overall_misses::total 769184 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481873 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481873 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986219 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986219 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481638 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481638 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986140 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986140 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35468092 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35468092 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914506 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914506 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 35467778 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467778 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses @@ -357,8 +357,8 @@ system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048319 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048319 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048327 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048327 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses @@ -371,14 +371,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511648 # number of writebacks -system.cpu0.dcache.writebacks::total 511648 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511896 # number of writebacks +system.cpu0.dcache.writebacks::total 511896 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1109742 # number of replacements +system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96332394 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1110254 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.766086 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy @@ -388,26 +388,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195995577 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195995577 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96332394 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96332394 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96332394 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96332394 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96332394 # number of overall hits -system.cpu0.icache.overall_hits::total 96332394 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1110263 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1110263 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1110263 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1110263 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1110263 # number of overall misses -system.cpu0.icache.overall_misses::total 1110263 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97442657 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97442657 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97442657 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97442657 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97442657 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97442657 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits +system.cpu0.icache.overall_hits::total 96331417 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses +system.cpu0.icache.overall_misses::total 1110256 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses @@ -429,123 +429,123 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 252403 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268606 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.739470 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 252330 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16129.294754 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1810154 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 268529 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.741000 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8068.095549 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.185761 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.086115 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.591048 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.325333 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.492437 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289831 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201985 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984453 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 8067.926153 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.192846 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.094111 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.670375 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.411269 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.492427 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289836 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201990 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984454 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16192 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5587 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7674 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2571 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5555 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7641 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2632 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39450391 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39450391 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7605 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3248 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065251 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 352125 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1428229 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511648 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511648 # number of Writeback hits +system.cpu0.l2cache.tags.tag_accesses 39452382 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39452382 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7540 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3225 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065497 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 351995 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1428257 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 511896 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511896 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94130 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94130 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7605 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3248 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1065251 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446255 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1522359 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7605 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3248 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1065251 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446255 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1522359 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 134 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 45012 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 128036 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 173407 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18433 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18433 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175387 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175387 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 134 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 45012 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303423 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348794 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 225 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 134 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 45012 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303423 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348794 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7830 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3382 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110263 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480161 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1601636 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511648 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511648 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18433 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18433 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94089 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94089 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7540 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3225 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1065497 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446084 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1522346 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7540 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3225 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1065497 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446084 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1522346 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 210 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44759 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 128167 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 173260 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26230 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26230 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18436 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18436 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175428 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175428 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 210 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 44759 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303595 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 348688 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 210 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 44759 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303595 # number of overall misses +system.cpu0.l2cache.overall_misses::total 348688 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7750 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3349 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110256 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480162 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1601517 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511896 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511896 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26247 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26247 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18436 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18436 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7830 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3382 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1110263 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1871153 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7830 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3382 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1110263 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1871153 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039622 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040542 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266652 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.108269 # miss rate for ReadReq accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7750 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3349 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749679 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1871034 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7750 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3349 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749679 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1871034 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037026 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040314 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266924 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.108185 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650746 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650746 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039622 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040542 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404738 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186406 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039622 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040542 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404738 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186406 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650898 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650898 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037026 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040314 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404967 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037026 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040314 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404967 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -554,45 +554,43 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192841 # number of writebacks -system.cpu0.l2cache.writebacks::total 192841 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192974 # number of writebacks +system.cpu0.l2cache.writebacks::total 192974 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1651853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511648 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18433 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44681 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1651840 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651840 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28386 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28386 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511896 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26247 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18436 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44683 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238570 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220344 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220556 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4500550 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092920 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80915642 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4500748 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80931536 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152091834 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 322042 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2656528 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.082604 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.275283 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152107280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 322019 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2656743 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.082586 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.275256 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 2437332 91.74% 91.74% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 219411 8.26% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2656743 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -642,9 +640,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173884 # DTB read hits +system.cpu1.dtb.read_hits 12173916 # DTB read hits system.cpu1.dtb.read_misses 2852 # DTB read misses -system.cpu1.dtb.write_hits 7587193 # DTB write hits +system.cpu1.dtb.write_hits 7587209 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -655,12 +653,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176736 # DTB read accesses -system.cpu1.dtb.write_accesses 7587699 # DTB write accesses +system.cpu1.dtb.read_accesses 12176768 # DTB read accesses +system.cpu1.dtb.write_accesses 7587715 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761077 # DTB hits +system.cpu1.dtb.hits 19761125 # DTB hits system.cpu1.dtb.misses 3358 # DTB misses -system.cpu1.dtb.accesses 19764435 # DTB accesses +system.cpu1.dtb.accesses 19764483 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -708,7 +706,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 53671431 # ITB inst hits +system.cpu1.itb.inst_hits 53671575 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -725,37 +723,37 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673165 # ITB inst accesses -system.cpu1.itb.hits 53671431 # DTB hits +system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses +system.cpu1.itb.hits 53671575 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673165 # DTB accesses -system.cpu1.numCycles 5605321082 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673309 # DTB accesses +system.cpu1.numCycles 5605320274 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51401178 # Number of instructions committed -system.cpu1.committedOps 63347444 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984089 # Number of integer alu accesses +system.cpu1.committedInsts 51401314 # Number of instructions committed +system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170823 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967084 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984089 # number of integer instructions +system.cpu1.num_func_calls 9170855 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984241 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110674435 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298241 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196268127 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894317 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026333 # number of memory refs -system.cpu1.num_load_insts 12289505 # Number of load instructions -system.cpu1.num_store_insts 7736828 # Number of store instructions -system.cpu1.num_idle_cycles 5539707743.549846 # Number of idle cycles -system.cpu1.num_busy_cycles 65613338.450155 # Number of busy cycles +system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026381 # number of memory refs +system.cpu1.num_load_insts 12289537 # Number of load instructions +system.cpu1.num_store_insts 7736844 # Number of store instructions +system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles +system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217445 # Number of branches fetched +system.cpu1.Branches 15217493 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401182 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction @@ -784,70 +782,70 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289505 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736828 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459288 # Class of executed instruction +system.cpu1.op_class::total 65459464 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed system.cpu1.dcache.tags.replacements 191938 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.735401 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503461 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.426274 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735401 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39751883 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39751883 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858662 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858662 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397475 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397475 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397494 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397494 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72435 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72435 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256137 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256137 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306236 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306236 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72460 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72460 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256188 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256188 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306287 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306287 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92471 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92471 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92468 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92468 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22544 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22544 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229101 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229101 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259820 # number of overall misses -system.cpu1.dcache.overall_misses::total 259820 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995292 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995292 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489946 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489946 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22519 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22519 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229098 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229098 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses +system.cpu1.dcache.overall_misses::total 259817 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485238 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485238 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566056 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566056 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses @@ -856,10 +854,10 @@ system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237358 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237358 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237095 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237095 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -870,42 +868,42 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120709 # number of writebacks -system.cpu1.dcache.writebacks::total 120709 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120855 # number of writebacks +system.cpu1.dcache.writebacks::total 120855 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.711131 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148636 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.450960 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711131 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107868927 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107868927 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148636 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148636 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148636 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148636 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148636 # number of overall hits -system.cpu1.icache.overall_hits::total 53148636 # number of overall hits +system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits +system.cpu1.icache.overall_hits::total 53148780 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses system.cpu1.icache.overall_misses::total 523885 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672521 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672521 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672521 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672521 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672521 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672521 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses @@ -927,88 +925,88 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 48598 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48604 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15305.333897 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 716708 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.298662 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030831 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.951411 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.465503 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809694 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.091002 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.023143 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.979607 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.430451 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200131 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225370 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934164 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14799 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000250 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200133 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225368 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.934163 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14807 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9279 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4981 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903259 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15211446 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15211446 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3145 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1724 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510078 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 99331 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 614278 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120709 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120709 # number of Writeback hits +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9357 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4911 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903748 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15213345 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15213345 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3151 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1735 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510036 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 99375 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 614297 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120855 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120855 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19802 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19802 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3145 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1724 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510078 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119133 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634080 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3145 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1724 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510078 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119133 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634080 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13807 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73336 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 87759 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28847 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28847 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22544 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22544 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43814 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43814 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13807 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117150 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13807 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117150 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19784 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19784 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3151 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1735 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510036 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119159 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634081 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3151 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1735 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510036 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119159 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634081 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 261 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13849 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73292 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 87740 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28844 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28844 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22519 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22519 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43832 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43832 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 261 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13849 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117124 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131572 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 261 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13849 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117124 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131572 # number of overall misses system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3489 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 702037 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120709 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120709 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28855 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28855 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22544 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22544 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120855 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120855 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28852 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28852 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22519 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22519 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3489 # number of demand (read+write) accesses @@ -1021,27 +1019,27 @@ system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 765653 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136273 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026355 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424725 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.125006 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.130762 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026435 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424470 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.124979 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688726 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688726 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136273 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026355 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495804 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171844 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136273 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026355 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495804 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171844 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689009 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689009 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.130762 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026435 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495694 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171843 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.130762 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026435 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495694 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171843 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1050,51 +1048,49 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32919 # number of writebacks -system.cpu1.l2cache.writebacks::total 32919 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32977 # number of writebacks +system.cpu1.l2cache.writebacks::total 32977 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120709 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51399 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120855 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28852 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22519 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51371 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707533 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707623 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1774351 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1774441 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866670 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22876014 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56433406 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 499587 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1371557 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.313464 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.463901 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56442750 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 499492 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1371571 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.313385 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.463870 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 941623 68.65% 68.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 429934 31.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 941741 68.66% 68.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 429830 31.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1371557 # Request fanout histogram -system.iobus.trans_dist::ReadReq 31002 # Transaction distribution -system.iobus.trans_dist::ReadResp 31002 # Transaction distribution -system.iobus.trans_dist::WriteReq 59433 # Transaction distribution -system.iobus.trans_dist::WriteResp 23209 # Transaction distribution +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1371571 # Request fanout histogram +system.iobus.trans_dist::ReadReq 30995 # Transaction distribution +system.iobus.trans_dist::ReadResp 30995 # Transaction distribution +system.iobus.trans_dist::WriteReq 59419 # Transaction distribution +system.iobus.trans_dist::WriteResp 23195 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1115,11 +1111,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1140,10 +1136,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36442 # number of replacements system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1193,21 +1189,21 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 107620 # number of replacements -system.l2c.tags.tagsinuse 62052.354763 # Cycle average of tags in use -system.l2c.tags.total_refs 207975 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168018 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.237814 # Average number of references to valid blocks. +system.l2c.tags.replacements 107683 # number of replacements +system.l2c.tags.tagsinuse 62052.473518 # Cycle average of tags in use +system.l2c.tags.total_refs 207875 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168125 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.236431 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48595.577563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.970677 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48595.677496 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972785 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030393 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7329.733330 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3756.722499 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7329.722723 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3756.747244 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1654.519056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 710.978017 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741510 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 1654.505866 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 710.993782 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.741511 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.111843 # Average percentage of cache occupancy @@ -1215,161 +1211,161 @@ system.l2c.tags.occ_percent::cpu0.data 0.057323 # Av system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.025246 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.946844 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1918 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45390 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 41 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 20 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13849 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12528 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 158721 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 225951 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225951 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10506 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3353 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13859 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 816 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1189 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150733 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18934 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169667 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 78 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 44759 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 238114 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13849 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31462 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328388 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 78 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44759 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238114 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13849 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31462 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328388 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.377600 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.129468 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.170770 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.089240 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.199772 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.953646 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980614 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.960170 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.921569 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.991590 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.963092 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.907532 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.835640 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899509 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.377600 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.622005 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.170770 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.538427 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.561302 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.377600 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.622005 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.170770 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.538427 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.561302 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1378,49 +1374,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 94860 # number of writebacks -system.l2c.writebacks::total 94860 # number of writebacks +system.l2c.writebacks::writebacks 94914 # number of writebacks +system.l2c.writebacks::total 94914 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 75978 # Transaction distribution -system.membus.trans_dist::ReadResp 75978 # Transaction distribution -system.membus.trans_dist::WriteReq 30905 # Transaction distribution -system.membus.trans_dist::WriteResp 30905 # Transaction distribution -system.membus.trans_dist::Writeback 131050 # Transaction distribution +system.membus.trans_dist::ReadReq 75966 # Transaction distribution +system.membus.trans_dist::ReadResp 75966 # Transaction distribution +system.membus.trans_dist::WriteReq 30891 # Transaction distribution +system.membus.trans_dist::WriteResp 30891 # Transaction distribution +system.membus.trans_dist::Writeback 131104 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60385 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40916 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15642 # Transaction distribution -system.membus.trans_dist::ReadExReq 196304 # Transaction distribution -system.membus.trans_dist::ReadExResp 152218 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 60393 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40881 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15635 # Transaction distribution +system.membus.trans_dist::ReadExReq 196339 # Transaction distribution +system.membus.trans_dist::ReadExResp 152220 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773592 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 882729 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 882734 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17899556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18089380 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17902820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18092602 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22740004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22743226 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 496844 # Request fanout histogram +system.membus.snoop_fanout::samples 496901 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 496844 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 496901 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 496844 # Request fanout histogram +system.membus.snoop_fanout::total 496901 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1452,33 +1448,33 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 305179 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305179 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225760 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60554 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40977 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101531 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213725 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213725 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117779 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 305006 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305006 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30891 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30891 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225951 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40955 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101503 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117662 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1528440 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34662706 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45088420 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1528323 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664008 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10429874 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45093882 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 838658 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.043493 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.203965 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 838716 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.043490 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.203958 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 802182 95.65% 95.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 802240 95.65% 95.65% # Request fanout histogram system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 838658 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 838716 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index fb9bec115..20c993e31 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867165000 # Number of ticks simulated -final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783867052000 # Number of ticks simulated +final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1374338 # Simulator instruction rate (inst/s) -host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26797569978 # Simulator tick rate (ticks/s) -host_mem_usage 615488 # Number of bytes of host memory used -host_seconds 103.89 # Real time elapsed on the host -sim_insts 142773109 # Number of instructions simulated -sim_ops 173803334 # Number of ops (including micro ops) simulated +host_inst_rate 1378466 # Simulator instruction rate (inst/s) +host_op_rate 1678062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26878113924 # Simulator tick rate (ticks/s) +host_mem_usage 614624 # Number of bytes of host memory used +host_seconds 103.57 # Real time elapsed on the host +sim_insts 142772879 # Number of instructions simulated +sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory +system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory +system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526301 # DTB read hits +system.cpu.dtb.read_hits 31526223 # DTB read hits system.cpu.dtb.read_misses 8581 # DTB read misses -system.cpu.dtb.write_hits 23124463 # DTB write hits +system.cpu.dtb.write_hits 23124452 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534882 # DTB read accesses -system.cpu.dtb.write_accesses 23125911 # DTB write accesses +system.cpu.dtb.read_accesses 31534804 # DTB read accesses +system.cpu.dtb.write_accesses 23125900 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650764 # DTB hits +system.cpu.dtb.hits 54650675 # DTB hits system.cpu.dtb.misses 10029 # DTB misses -system.cpu.dtb.accesses 54660793 # DTB accesses +system.cpu.dtb.accesses 54660704 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147039592 # ITB inst hits +system.cpu.itb.inst_hits 147039346 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -202,37 +202,37 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147044354 # ITB inst accesses -system.cpu.itb.hits 147039592 # DTB hits +system.cpu.itb.inst_accesses 147044108 # ITB inst accesses +system.cpu.itb.hits 147039346 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147044354 # DTB accesses -system.cpu.numCycles 5567737414 # number of cpu cycles simulated +system.cpu.itb.accesses 147044108 # DTB accesses +system.cpu.numCycles 5567737188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 142773109 # Number of instructions committed -system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses +system.cpu.committedInsts 142772879 # Number of instructions committed +system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873879 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls -system.cpu.num_int_insts 153162826 # number of integer instructions +system.cpu.num_func_calls 16873899 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls +system.cpu.num_int_insts 153162683 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read -system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written +system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read +system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written -system.cpu.num_mem_refs 55939365 # number of memory refs -system.cpu.num_load_insts 31855962 # Number of load instructions -system.cpu.num_store_insts 24083403 # Number of store instructions -system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles -system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles +system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written +system.cpu.num_mem_refs 55939276 # number of memory refs +system.cpu.num_load_insts 31855884 # Number of load instructions +system.cpu.num_store_insts 24083392 # Number of store instructions +system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles +system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36397028 # Number of branches fetched +system.cpu.Branches 36396981 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction @@ -261,18 +261,18 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177220138 # Class of executed instruction +system.cpu.op_class::total 177219912 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 819403 # number of replacements +system.cpu.dcache.tags.replacements 819402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,24 +282,24 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits -system.cpu.dcache.overall_hits::total 52864309 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits +system.cpu.dcache.overall_hits::total 52864242 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses @@ -308,24 +308,24 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses -system.cpu.dcache.overall_misses::total 814075 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses +system.cpu.dcache.overall_misses::total 814074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses @@ -348,14 +348,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks -system.cpu.dcache.writebacks::total 682060 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks +system.cpu.dcache.writebacks::total 682059 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699220 # number of replacements +system.cpu.icache.tags.replacements 1699214 # number of replacements system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy @@ -366,26 +366,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits -system.cpu.icache.overall_hits::total 145342961 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses -system.cpu.icache.overall_misses::total 1699738 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits +system.cpu.icache.overall_hits::total 145342721 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses +system.cpu.icache.overall_misses::total 1699732 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses @@ -401,17 +401,17 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 110027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 110026 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -428,34 +428,34 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits -system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits +system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses @@ -464,21 +464,21 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses -system.cpu.l2cache.overall_misses::total 181765 # number of overall misses +system.cpu.l2cache.overall_misses::total 181764 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) @@ -487,19 +487,19 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses @@ -508,12 +508,12 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -524,51 +524,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks -system.cpu.l2cache.writebacks::total 101898 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks +system.cpu.l2cache.writebacks::total 101897 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram -system.iobus.trans_dist::ReadReq 30171 # Transaction distribution -system.iobus.trans_dist::ReadResp 30171 # Transaction distribution -system.iobus.trans_dist::WriteReq 59016 # Transaction distribution -system.iobus.trans_dist::WriteResp 22792 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram +system.iobus.trans_dist::ReadReq 30164 # Transaction distribution +system.iobus.trans_dist::ReadResp 30164 # Transaction distribution +system.iobus.trans_dist::WriteReq 59002 # Transaction distribution +system.iobus.trans_dist::WriteResp 22778 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -589,11 +587,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -614,17 +612,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -667,11 +665,11 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74235 # Transaction distribution -system.membus.trans_dist::ReadResp 74235 # Transaction distribution -system.membus.trans_dist::WriteReq 27560 # Transaction distribution -system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 138088 # Transaction distribution +system.membus.trans_dist::ReadReq 74227 # Transaction distribution +system.membus.trans_dist::ReadResp 74227 # Transaction distribution +system.membus.trans_dist::WriteReq 27546 # Transaction distribution +system.membus.trans_dist::WriteResp 27546 # Transaction distribution +system.membus.trans_dist::Writeback 138087 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -679,34 +677,34 @@ system.membus.trans_dist::SCUpgradeReq 2 # Tr system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 359047 # Request fanout histogram +system.membus.snoop_fanout::samples 359045 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 359047 # Request fanout histogram +system.membus.snoop_fanout::total 359045 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 391769400..64a01b6e7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,160 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.868319 # Number of seconds simulated -sim_ticks 2868318696500 # Number of ticks simulated -final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868581 # Number of seconds simulated +sim_ticks 2868581440500 # Number of ticks simulated +final_tick 2868581440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 534652 # Simulator instruction rate (inst/s) -host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11631340017 # Simulator tick rate (ticks/s) -host_mem_usage 586476 # Number of bytes of host memory used -host_seconds 246.60 # Real time elapsed on the host -sim_insts 131846562 # Number of instructions simulated -sim_ops 159471778 # Number of ops (including micro ops) simulated +host_inst_rate 717360 # Simulator instruction rate (inst/s) +host_op_rate 867708 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15647358559 # Simulator tick rate (ticks/s) +host_mem_usage 639748 # Number of bytes of host memory used +host_seconds 183.33 # Real time elapsed on the host +sim_insts 131511324 # Number of instructions simulated +sim_ops 159074269 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1161572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1227520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8321088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 141140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 467936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 345792 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory +system.physmem.bytes_read::total 11666584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1161572 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 141140 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1302712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8208384 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory +system.physmem.bytes_written::total 8226128 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5403 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory +system.physmem.num_reads::total 191448 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 128256 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory +system.physmem.num_writes::total 132692 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 404929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 427919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2900768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 163125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 120545 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4067022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 404929 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49202 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2861478 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2867664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2861478 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 404929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 434091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2900768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 163138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 120545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200214 # Number of read requests accepted -system.physmem.writeReqs 175885 # Number of write requests accepted -system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12188 # Per bank write bursts -system.physmem.perBankRdBursts::1 12046 # Per bank write bursts -system.physmem.perBankRdBursts::2 12591 # Per bank write bursts -system.physmem.perBankRdBursts::3 12330 # Per bank write bursts -system.physmem.perBankRdBursts::4 20750 # Per bank write bursts -system.physmem.perBankRdBursts::5 12582 # Per bank write bursts -system.physmem.perBankRdBursts::6 12043 # Per bank write bursts -system.physmem.perBankRdBursts::7 12246 # Per bank write bursts -system.physmem.perBankRdBursts::8 12442 # Per bank write bursts -system.physmem.perBankRdBursts::9 12402 # Per bank write bursts -system.physmem.perBankRdBursts::10 11722 # Per bank write bursts -system.physmem.perBankRdBursts::11 11146 # Per bank write bursts -system.physmem.perBankRdBursts::12 11467 # Per bank write bursts -system.physmem.perBankRdBursts::13 11916 # Per bank write bursts -system.physmem.perBankRdBursts::14 10852 # Per bank write bursts -system.physmem.perBankRdBursts::15 11341 # Per bank write bursts -system.physmem.perBankWrBursts::0 10835 # Per bank write bursts -system.physmem.perBankWrBursts::1 11264 # Per bank write bursts -system.physmem.perBankWrBursts::2 11493 # Per bank write bursts -system.physmem.perBankWrBursts::3 10899 # Per bank write bursts -system.physmem.perBankWrBursts::4 10487 # Per bank write bursts -system.physmem.perBankWrBursts::5 11152 # Per bank write bursts -system.physmem.perBankWrBursts::6 11024 # Per bank write bursts -system.physmem.perBankWrBursts::7 10595 # Per bank write bursts -system.physmem.perBankWrBursts::8 10782 # Per bank write bursts -system.physmem.perBankWrBursts::9 10958 # Per bank write bursts -system.physmem.perBankWrBursts::10 10716 # Per bank write bursts -system.physmem.perBankWrBursts::11 10408 # Per bank write bursts -system.physmem.perBankWrBursts::12 10444 # Per bank write bursts -system.physmem.perBankWrBursts::13 9906 # Per bank write bursts -system.physmem.perBankWrBursts::14 9416 # Per bank write bursts -system.physmem.perBankWrBursts::15 9817 # Per bank write bursts +system.physmem.bw_total::total 6934686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 191448 # Number of read requests accepted +system.physmem.writeReqs 168916 # Number of write requests accepted +system.physmem.readBursts 191448 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 168916 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12244160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue +system.physmem.bytesWritten 9286016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11666584 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10544464 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23799 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13043 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11402 # Per bank write bursts +system.physmem.perBankRdBursts::1 11523 # Per bank write bursts +system.physmem.perBankRdBursts::2 11617 # Per bank write bursts +system.physmem.perBankRdBursts::3 11771 # Per bank write bursts +system.physmem.perBankRdBursts::4 20348 # Per bank write bursts +system.physmem.perBankRdBursts::5 12097 # Per bank write bursts +system.physmem.perBankRdBursts::6 11123 # Per bank write bursts +system.physmem.perBankRdBursts::7 11241 # Per bank write bursts +system.physmem.perBankRdBursts::8 11419 # Per bank write bursts +system.physmem.perBankRdBursts::9 11532 # Per bank write bursts +system.physmem.perBankRdBursts::10 11480 # Per bank write bursts +system.physmem.perBankRdBursts::11 10715 # Per bank write bursts +system.physmem.perBankRdBursts::12 11252 # Per bank write bursts +system.physmem.perBankRdBursts::13 11225 # Per bank write bursts +system.physmem.perBankRdBursts::14 11052 # Per bank write bursts +system.physmem.perBankRdBursts::15 11518 # Per bank write bursts +system.physmem.perBankWrBursts::0 9249 # Per bank write bursts +system.physmem.perBankWrBursts::1 9496 # Per bank write bursts +system.physmem.perBankWrBursts::2 9535 # Per bank write bursts +system.physmem.perBankWrBursts::3 9435 # Per bank write bursts +system.physmem.perBankWrBursts::4 8870 # Per bank write bursts +system.physmem.perBankWrBursts::5 9467 # Per bank write bursts +system.physmem.perBankWrBursts::6 9116 # Per bank write bursts +system.physmem.perBankWrBursts::7 8737 # Per bank write bursts +system.physmem.perBankWrBursts::8 8796 # Per bank write bursts +system.physmem.perBankWrBursts::9 9230 # Per bank write bursts +system.physmem.perBankWrBursts::10 9164 # Per bank write bursts +system.physmem.perBankWrBursts::11 8822 # Per bank write bursts +system.physmem.perBankWrBursts::12 9029 # Per bank write bursts +system.physmem.perBankWrBursts::13 8642 # Per bank write bursts +system.physmem.perBankWrBursts::14 8756 # Per bank write bursts +system.physmem.perBankWrBursts::15 8750 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2868318254500 # Total gap between requests +system.physmem.numWrRetry 83 # Number of times write queue was full causing retry +system.physmem.totGap 2868581033500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190444 # Read request sizes (log2) +system.physmem.readPktSize::6 181678 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 171449 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see +system.physmem.writePktSize::6 164480 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 134188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 9686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 47 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,178 +180,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads -system.physmem.totQLat 4855930250 # Total ticks spent queuing -system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 81717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 263.471640 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.531290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.110863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41089 50.28% 50.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16342 20.00% 70.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5746 7.03% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3516 4.30% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2447 2.99% 84.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1416 1.73% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 997 1.22% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 891 1.09% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9273 11.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 81717 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5972 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.034494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 599.214233 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5970 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5972 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.295713 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.853114 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 39.858214 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5595 93.69% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 97 1.62% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 24 0.40% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 14 0.23% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 35 0.59% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 43 0.72% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 25 0.42% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 12 0.20% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 18 0.30% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.08% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 30 0.50% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 15 0.25% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.12% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.07% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.05% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 7 0.12% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.10% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.12% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5972 # Writes before turning the bus around for reads +system.physmem.totQLat 4538980935 # Total ticks spent queuing +system.physmem.totMemAccLat 8126137185 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 956575000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23725.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42475.17 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing -system.physmem.readRowHits 167229 # Number of row buffer hits during reads -system.physmem.writeRowHits 112615 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes -system.physmem.avgGap 7626497.96 # Average gap between requests -system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.622475 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states -system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing +system.physmem.readRowHits 160412 # Number of row buffer hits during reads +system.physmem.writeRowHits 94279 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 64.97 # Row buffer hit rate for writes +system.physmem.avgGap 7960231.97 # Average gap between requests +system.physmem.pageHitRate 75.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 319183200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 174157500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 788743800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 478904400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83526196590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647879002250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920527828700 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.504870 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2741264066617 # Time in different power states +system.physmem_0.memoryStateTime::REF 95788160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31529102383 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.527135 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_1.actEnergy 298597320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 162925125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 703505400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 461304720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82377359595 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648886754000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920252087120 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.408745 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742945725805 # Time in different power states +system.physmem_1.memoryStateTime::REF 95788160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29845454195 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -411,57 +391,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7749 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 7634 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7634 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1372 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7634 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6240 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9567.588141 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8440.173252 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5686.595019 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6084 97.50% 97.50% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 143 2.29% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 8 0.13% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6240 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1121059000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1121059000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1121059000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4907 78.64% 78.64% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1333 21.36% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6240 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7634 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7634 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6240 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6240 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 13874 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 19044092 # DTB read hits -system.cpu0.dtb.read_misses 6608 # DTB read misses -system.cpu0.dtb.write_hits 15688894 # DTB write hits -system.cpu0.dtb.write_misses 1141 # DTB write misses +system.cpu0.dtb.read_hits 25111402 # DTB read hits +system.cpu0.dtb.read_misses 6533 # DTB read misses +system.cpu0.dtb.write_hits 18719047 # DTB write hits +system.cpu0.dtb.write_misses 1101 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1785 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 19050700 # DTB read accesses -system.cpu0.dtb.write_accesses 15690035 # DTB write accesses +system.cpu0.dtb.read_accesses 25117935 # DTB read accesses +system.cpu0.dtb.write_accesses 18720148 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 34732986 # DTB hits -system.cpu0.dtb.misses 7749 # DTB misses -system.cpu0.dtb.accesses 34740735 # DTB accesses +system.cpu0.dtb.hits 43830449 # DTB hits +system.cpu0.dtb.misses 7634 # DTB misses +system.cpu0.dtb.accesses 43838083 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -499,20 +480,20 @@ system.cpu0.itb.walker.walkWaitTime::samples 3348 system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9914.451115 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8640.132285 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5844.480359 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 848 36.36% 36.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1427 61.19% 97.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.68% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 51 2.19% 99.87% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::samples 1120687000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1120687000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1120687000 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated @@ -523,7 +504,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 91510827 # ITB inst hits +system.cpu0.itb.inst_hits 118783416 # ITB inst hits system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -540,172 +521,172 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses -system.cpu0.itb.hits 91510827 # DTB hits +system.cpu0.itb.inst_accesses 118786764 # ITB inst accesses +system.cpu0.itb.hits 118783416 # DTB hits system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 91514175 # DTB accesses -system.cpu0.numCycles 5736637393 # number of cpu cycles simulated +system.cpu0.itb.accesses 118786764 # DTB accesses +system.cpu0.numCycles 5737162881 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 89363678 # Number of instructions committed -system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses +system.cpu0.committedInsts 115118664 # Number of instructions committed +system.cpu0.committedOps 139117689 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123147620 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 6606472 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls -system.cpu0.num_int_insts 94350928 # number of integer instructions +system.cpu0.num_func_calls 12673072 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15652345 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123147620 # number of integer instructions system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read -system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written +system.cpu0.num_int_register_reads 226729132 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85574900 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written -system.cpu0.num_mem_refs 35866705 # number of memory refs -system.cpu0.num_load_insts 19295047 # Number of load instructions -system.cpu0.num_store_insts 16571658 # Number of store instructions -system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles -system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles -system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles -system.cpu0.Branches 19970568 # Number of branches fetched +system.cpu0.num_cc_register_reads 504016583 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52146919 # number of times the CC registers were written +system.cpu0.num_mem_refs 44965604 # number of memory refs +system.cpu0.num_load_insts 25362826 # Number of load instructions +system.cpu0.num_store_insts 19602778 # Number of store instructions +system.cpu0.num_idle_cycles 5466015382.984095 # Number of idle cycles +system.cpu0.num_busy_cycles 271147498.015905 # Number of busy cycles +system.cpu0.not_idle_fraction 0.047262 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.952738 # Percentage of idle cycles +system.cpu0.Branches 29061799 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction -system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction -system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 97796607 68.45% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 109233 0.08% 68.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8187 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::MemRead 25362826 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19602778 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 109543126 # Class of executed instruction +system.cpu0.op_class::total 142881904 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 690539 # number of replacements -system.cpu0.dcache.tags.tagsinuse 487.185772 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 33864824 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 691051 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.004812 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1015908000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.185772 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951535 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.951535 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 688886 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.817079 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42962889 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 689398 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.319428 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1149671500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.817079 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966440 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966440 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 70103571 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 70103571 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 17785791 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 17785791 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14958877 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14958877 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318525 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 318525 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364927 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 364927 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361705 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361705 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 32744668 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 32744668 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 33063193 # number of overall hits -system.cpu0.dcache.overall_hits::total 33063193 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 394905 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 394905 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324481 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324481 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127732 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127732 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21710 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21710 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20007 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20007 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 719386 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 719386 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 847118 # number of overall misses -system.cpu0.dcache.overall_misses::total 847118 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4990872752 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4990872752 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4944330313 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4944330313 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327573000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 327573000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444426745 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 444426745 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1572500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1572500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 9935203065 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 9935203065 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 9935203065 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 9935203065 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 18180696 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 18180696 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15283358 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15283358 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446257 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446257 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386637 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386637 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381712 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381712 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 33464054 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 33464054 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 33910311 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 33910311 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.021721 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.021721 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.021231 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.021231 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.286230 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.286230 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052414 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052414 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.021497 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.021497 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.024981 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.024981 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12638.160449 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12638.160449 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15237.657407 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15237.657407 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15088.576693 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15088.576693 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22213.562503 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22213.562503 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88293922 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88293922 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23854264 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23854264 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17989541 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17989541 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318725 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 318725 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364533 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 364533 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361797 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361797 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41843805 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41843805 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42162530 # number of overall hits +system.cpu0.dcache.overall_hits::total 42162530 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 393288 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 393288 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 323540 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 323540 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127427 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127427 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21927 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21927 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19722 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19722 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 716828 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 716828 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 844255 # number of overall misses +system.cpu0.dcache.overall_misses::total 844255 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5012719236 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5012719236 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5098069375 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5098069375 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 332035250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 332035250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435652050 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 435652050 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1835500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1835500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10110788611 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10110788611 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10110788611 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10110788611 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24247552 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24247552 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18313081 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18313081 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446152 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446152 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386460 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386460 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42560633 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42560633 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43006785 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43006785 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016220 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016220 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017667 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017667 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285613 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285613 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056738 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056738 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051693 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051693 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016843 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016843 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019631 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019631 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12745.670440 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12745.670440 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15757.153289 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15757.153289 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15142.757787 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15142.757787 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22089.648616 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22089.648616 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14104.901889 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14104.901889 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11975.989021 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11975.989021 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -714,82 +695,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks -system.cpu0.dcache.writebacks::total 504116 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25128 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25128 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25128 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25128 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369777 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369777 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324481 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324481 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100470 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100470 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 694258 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 504121 # number of writebacks +system.cpu0.dcache.writebacks::total 504121 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25265 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25265 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15169 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15169 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25265 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25265 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368023 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 368023 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323540 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323540 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100320 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100320 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6758 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6758 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19722 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19722 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 691563 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 691563 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 791883 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 791883 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4066612315 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4066612315 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4601719625 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4601719625 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1548565203 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1548565203 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97840500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97840500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 405700950 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 405700950 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1754500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1754500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8668331940 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8668331940 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10216897143 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10216897143 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6181726750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6181726750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4820424000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4820424000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11002150750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11002150750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224856 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224856 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051693 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051693 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018413 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018413 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11049.886325 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11049.886325 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14223.031542 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14223.031542 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15436.256011 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15436.256011 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14477.730098 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14477.730098 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20570.984180 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20570.984180 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12534.406757 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12534.406757 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12902.028637 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12902.028637 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -797,58 +778,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1099798 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1101309 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.453846 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117681586 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1101821 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.806447 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13496302250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.453846 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998933 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998933 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits -system.cpu0.icache.overall_hits::total 90410508 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses -system.cpu0.icache.overall_misses::total 1100319 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 238668662 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 238668662 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 117681586 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117681586 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117681586 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117681586 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117681586 # number of overall hits +system.cpu0.icache.overall_hits::total 117681586 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1101830 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1101830 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1101830 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1101830 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1101830 # number of overall misses +system.cpu0.icache.overall_misses::total 1101830 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10869872254 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10869872254 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10869872254 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10869872254 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10869872254 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10869872254 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 118783416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 118783416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 118783416 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 118783416 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 118783416 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 118783416 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009276 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009276 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009276 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009276 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9865.289794 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9865.289794 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9865.289794 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9865.289794 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -857,223 +838,224 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100319 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1100319 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100319 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1100319 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100319 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1100319 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9082830507 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9082830507 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9082830507 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9082830507 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9082830507 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9082830507 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012024 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012024 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012024 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8254.724773 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1101830 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1101830 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1101830 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1101830 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1101830 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1101830 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9761619746 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9761619746 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9761619746 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9761619746 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9761619746 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9761619746 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 802157500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 802157500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 802157500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 802157500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009276 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009276 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8859.460848 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8859.460848 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8859.460848 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853283 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1853292 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1839936 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1839962 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 238164 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 268426 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16093.899190 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1968322 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 284663 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.914569 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 237006 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 267761 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16103.938258 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1970214 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 284001 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.937349 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7921.036071 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.357121 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.109776 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4473.771805 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1953.197848 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1743.426570 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.483462 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000144 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.273057 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119214 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.106410 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982294 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1127 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15106 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 288 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 7915.761025 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.539297 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.155291 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4574.741605 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1897.934094 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1714.806946 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.483140 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000033 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.279220 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.115841 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104664 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982906 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1117 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15115 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 261 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 418 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 118 # 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number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4606674000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 730253500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10533882500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11264136000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.198255 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089176 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.483452 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.483452 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914996 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.914996 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.480767 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.480767 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911032 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.911032 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150199 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150199 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098416 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158963 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158963 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.099287 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230592 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22742.345957 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29542.690680 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55320.103445 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19621.173082 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19621.173082 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14375.037581 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14375.037581 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 192571 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192571 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36152.288892 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36152.288892 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31075.910829 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44881.149122 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1213,57 +1195,55 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1733379 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1686259 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28500 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28500 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 504119 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 307885 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42217 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 297195 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284749 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2221704 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2362865 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10199 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22165 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4616933 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70553208 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84179104 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 15204 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 33076 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 154780592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 633519 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2968459 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.176473 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.381222 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 2444606 82.35% 82.35% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 523853 17.65% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2968459 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1775328997 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114507000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1667097754 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1206509407 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 13896250 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1294,59 +1274,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3332 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 3283 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3283 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 611 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2672 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3283 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3283 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3283 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2513 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9027.258257 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8086.769918 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4736.776885 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 485 19.30% 19.30% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 533 21.21% 40.51% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1045 41.58% 82.09% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 324 12.89% 94.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 44 1.75% 96.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 19 0.76% 97.49% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 51 2.03% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 8 0.32% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2513 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1651557968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1651557968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1651557968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1910 76.00% 76.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 603 24.00% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2513 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3283 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3283 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2513 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2513 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5796 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10115566 # DTB read hits -system.cpu1.dtb.read_misses 2828 # DTB read misses -system.cpu1.dtb.write_hits 6544640 # DTB write hits -system.cpu1.dtb.write_misses 504 # DTB write misses +system.cpu1.dtb.read_hits 3974119 # DTB read hits +system.cpu1.dtb.read_misses 2776 # DTB read misses +system.cpu1.dtb.write_hits 3444686 # DTB write hits +system.cpu1.dtb.write_misses 507 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 362 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10118394 # DTB read accesses -system.cpu1.dtb.write_accesses 6545144 # DTB write accesses +system.cpu1.dtb.read_accesses 3976895 # DTB read accesses +system.cpu1.dtb.write_accesses 3445193 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16660206 # DTB hits -system.cpu1.dtb.misses 3332 # DTB misses -system.cpu1.dtb.accesses 16663538 # DTB accesses +system.cpu1.dtb.hits 7418805 # DTB hits +system.cpu1.dtb.misses 3283 # DTB misses +system.cpu1.dtb.accesses 7422088 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1376,42 +1359,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1746 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1740 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1740 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 164 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1576 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1740 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1740 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1740 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9655.767484 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8490.755174 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5670.300287 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 219 19.89% 19.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 163 14.80% 34.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 463 42.05% 76.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 25 2.27% 97.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.91% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1651010968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1651010968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1651010968 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 937 85.10% 85.10% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 164 14.90% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1101 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1740 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1740 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 44359905 # ITB inst hits -system.cpu1.itb.inst_misses 1746 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2841 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 16749094 # ITB inst hits +system.cpu1.itb.inst_misses 1740 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1420,178 +1404,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1142 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses -system.cpu1.itb.hits 44359905 # DTB hits -system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 44361651 # DTB accesses -system.cpu1.numCycles 5735725430 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 16750834 # ITB inst accesses +system.cpu1.itb.hits 16749094 # DTB hits +system.cpu1.itb.misses 1740 # DTB misses +system.cpu1.itb.accesses 16750834 # DTB accesses +system.cpu1.numCycles 5736248293 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 42482884 # Number of instructions committed -system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses +system.cpu1.committedInsts 16392660 # Number of instructions committed +system.cpu1.committedOps 19956580 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17976734 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 7121857 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls -system.cpu1.num_int_insts 47161467 # number of integer instructions +system.cpu1.num_func_calls 1033061 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1853914 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17976734 # number of integer instructions system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read -system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written +system.cpu1.num_int_register_reads 32611379 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12600410 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written -system.cpu1.num_mem_refs 16924073 # number of memory refs -system.cpu1.num_load_insts 10229886 # Number of load instructions -system.cpu1.num_store_insts 6694187 # Number of store instructions -system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles -system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles -system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles -system.cpu1.Branches 12116511 # Number of branches fetched +system.cpu1.num_cc_register_reads 72918750 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6543930 # number of times the CC registers were written +system.cpu1.num_mem_refs 7653523 # number of memory refs +system.cpu1.num_load_insts 4085696 # Number of load instructions +system.cpu1.num_store_insts 3567827 # Number of store instructions +system.cpu1.num_idle_cycles 5685220667.433728 # Number of idle cycles +system.cpu1.num_busy_cycles 51027625.566272 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008896 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991104 # Percentage of idle cycles +system.cpu1.Branches 2968133 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction -system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction -system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 12626391 62.17% 62.17% # Class of executed instruction +system.cpu1.op_class::IntMult 25909 0.13% 62.30% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3321 0.02% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::MemRead 4085696 20.12% 82.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 3567827 17.57% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 54073981 # Class of executed instruction +system.cpu1.op_class::total 20309210 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2789 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 191058 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 33541448 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 33541448 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9797337 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9797337 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6353174 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6353174 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49731 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49731 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79655 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79655 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71640 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71640 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 16150511 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 16150511 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 16200242 # number of overall hits -system.cpu1.dcache.overall_hits::total 16200242 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 137366 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 137366 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 93147 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 93147 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30426 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30426 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17223 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23379 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23379 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 230513 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 230513 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 260939 # number of overall misses -system.cpu1.dcache.overall_misses::total 260939 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1997360003 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1997360003 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2352005341 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2352005341 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 320800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539390293 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 539390293 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1691000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1691000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4349365344 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4349365344 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4349365344 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4349365344 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9934703 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9934703 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6446321 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6446321 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80157 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80157 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96878 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96878 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95019 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95019 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16381024 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16381024 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16461181 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16461181 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013827 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013827 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014450 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.014450 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379580 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379580 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177780 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177780 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246046 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246046 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014072 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.014072 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.015852 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.015852 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14540.424872 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14540.424872 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25250.467981 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25250.467981 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18626.255588 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18626.255588 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23071.572480 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2726 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 187627 # number of replacements +system.cpu1.dcache.tags.tagsinuse 465.215072 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7146939 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187994 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.016846 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104853894000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 465.215072 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.908623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.908623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 52 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 15057330 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15057330 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3659340 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3659340 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3255921 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3255921 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49714 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49714 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79782 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79782 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71812 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71812 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6915261 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6915261 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6964975 # number of overall hits +system.cpu1.dcache.overall_hits::total 6964975 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 134401 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 134401 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 90853 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 90853 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30496 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30496 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17326 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23466 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23466 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 225254 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 225254 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255750 # number of overall misses +system.cpu1.dcache.overall_misses::total 255750 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1931922000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1931922000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2253615359 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2253615359 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317972750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 317972750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 552026738 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 552026738 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2980000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2980000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4185537359 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4185537359 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4185537359 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4185537359 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3793741 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3793741 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3346774 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3346774 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80210 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80210 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97108 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97108 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95278 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95278 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7140515 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7140515 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7220725 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7220725 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035427 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035427 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027146 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027146 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380202 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380202 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178420 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178420 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246290 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246290 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031546 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031546 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035419 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035419 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14374.312691 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14374.312691 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24805.073679 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24805.073679 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18352.346185 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18352.346185 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23524.534987 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23524.534987 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18581.411913 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18581.411913 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16365.737474 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16365.737474 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1600,82 +1584,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 118649 # number of writebacks -system.cpu1.dcache.writebacks::total 118649 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 239 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12076 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12076 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 239 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 239 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 137127 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 137127 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93147 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 93147 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29658 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29658 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5147 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5147 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23379 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23379 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 230274 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 230274 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259932 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259932 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1715737747 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1715737747 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2159697659 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2159697659 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 467259500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 467259500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82226250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82226250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491497707 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491497707 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1621000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1621000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3875435406 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3875435406 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4342694906 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4342694906 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 525084500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 525084500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 379956000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 379956000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 905040500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246046 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246046 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014057 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014057 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015791 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015791 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.034443 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23185.906782 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23185.906782 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 117066 # number of writebacks +system.cpu1.dcache.writebacks::total 117066 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 249 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12071 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12071 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 249 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 249 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 249 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134152 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 134152 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90853 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90853 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29793 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29793 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5255 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5255 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23466 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23466 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225005 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225005 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254798 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254798 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724213250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724213250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2112235141 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2112235141 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 459472252 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 459472252 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82571000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82571000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 515647762 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 515647762 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2900500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2900500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3836448391 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3836448391 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4295920643 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4295920643 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406973750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406973750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 280407500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 280407500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 687381250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 687381250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.371437 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.371437 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246290 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246290 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031511 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031511 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035287 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035287 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12852.683896 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12852.683896 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23248.931142 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23248.931142 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.154600 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15422.154600 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15712.844910 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15712.844910 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21974.250490 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21974.250490 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16829.669898 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16829.669898 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16707.042250 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16707.042250 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17050.502838 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17050.502838 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16860.103466 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16860.103466 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1683,58 +1667,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 526723 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.608741 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 43832665 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 527235 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 83.136865 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 84507534000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.608741 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973845 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973845 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 506368 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.574535 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16242209 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 506880 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 32.043499 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 84702777500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.574535 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973778 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973778 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 89247035 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 89247035 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 43832665 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 43832665 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 43832665 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 43832665 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 43832665 # number of overall hits -system.cpu1.icache.overall_hits::total 43832665 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 527235 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 527235 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 527235 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 527235 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 527235 # number of overall misses -system.cpu1.icache.overall_misses::total 527235 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4617960760 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4617960760 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4617960760 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4617960760 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4617960760 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4617960760 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 44359900 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 44359900 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 44359900 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 44359900 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 44359900 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 44359900 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011885 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011885 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011885 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011885 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011885 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011885 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8758.828151 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8758.828151 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8758.828151 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8758.828151 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 34005058 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 34005058 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 16242209 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16242209 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16242209 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16242209 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16242209 # number of overall hits +system.cpu1.icache.overall_hits::total 16242209 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 506880 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 506880 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 506880 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 506880 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 506880 # 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number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16749089 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16749089 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030263 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030263 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030263 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030263 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030263 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030263 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8761.635918 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8761.635918 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8761.635918 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8761.635918 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1743,219 +1727,220 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 527235 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 527235 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 527235 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 527235 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 527235 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 527235 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3826248740 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3826248740 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3826248740 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3826248740 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3826248740 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3826248740 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13994500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13994500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13994500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13994500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011885 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011885 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011885 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7257.197910 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506880 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 506880 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 506880 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 506880 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 506880 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 506880 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3933409986 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3933409986 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3933409986 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3933409986 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3933409986 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3933409986 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15446750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15446750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15446750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15446750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030263 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030263 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030263 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7760.041797 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 194594 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 194618 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 47689 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15083.724459 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 731618 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62301 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.743279 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58318 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 39568 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14853.795199 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 710508 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 54174 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 13.115295 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8757.920968 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.140482 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.100736 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.623984 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2111.182929 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 939.755359 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.534541 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199562 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128856 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057358 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.920637 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1198 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13391 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 29 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1169 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8945.748297 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.024093 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.068283 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3300.044649 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1917.167815 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 684.742061 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.546005 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000246 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201419 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.117015 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.041793 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.906604 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1123 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13469 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1075 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1514 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11595 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073120 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.817322 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15244499 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15244499 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3091 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1729 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 513133 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 102720 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 620673 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 118649 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 118649 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1485 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1485 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 867 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 867 # 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number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14041750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 644355250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 658397000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.394781 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.118261 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950208 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950208 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962911 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962911 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.963379 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.963379 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961163 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961163 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554427 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554427 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154991 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.547314 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.547314 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153972 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.184497 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14916.725302 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17218.998796 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31238.473506 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15749.026272 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15749.026272 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15082.397676 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15082.397676 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 278111.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 278111.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 28967.204738 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 28967.204738 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20694.834000 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22439.264722 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2093,64 +2078,62 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1026038 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 726618 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2443 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2443 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 117066 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 27637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75553 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41371 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85405 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 84221 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66421 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1014114 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 770781 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5251 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9223 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1799369 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32441028 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25029390 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7740 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13072 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 57491230 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 567913 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1404964 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.347502 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.476177 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 916736 65.25% 65.25% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 488228 34.75% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1404964 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 579509000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80431999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 760939764 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 380431845 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3316000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 5955000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31024 # Transaction distribution -system.iobus.trans_dist::ReadResp 31024 # Transaction distribution -system.iobus.trans_dist::WriteReq 59440 # Transaction distribution -system.iobus.trans_dist::WriteResp 23216 # Transaction distribution +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::WriteReq 59423 # Transaction distribution +system.iobus.trans_dist::WriteResp 23199 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2171,11 +2154,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2196,11 +2179,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2240,23 +2223,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198981721 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36787516 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.385318 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 288337625000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.385318 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899082 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899082 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2270,14 +2253,14 @@ system.iocache.demand_misses::realview.ide 255 # system.iocache.demand_misses::total 255 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 255 # number of overall misses system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32669377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32669377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649988828 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6649988828 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32669377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32669377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32669377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32669377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -2294,19 +2277,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128115.203922 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128115.203922 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183579.638582 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183579.638582 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128115.203922 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128115.203922 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22637 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3456 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.550058 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2320,14 +2303,14 @@ system.iocache.demand_mshr_misses::realview.ide 255 system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19398377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19398377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766308860 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766308860 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19398377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19398377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19398377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19398377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2336,303 +2319,290 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76072.066667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76072.066667 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131578.756073 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131578.756073 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 130735 # number of replacements -system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use -system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. +system.l2c.tags.replacements 120296 # number of replacements +system.l2c.tags.tagsinuse 63905.436039 # Cycle average of tags in use +system.l2c.tags.total_refs 339434 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 184689 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.837868 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12083.139597 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.938906 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.007553 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6678.027236 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2760.487108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38360.306045 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955640 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1552.248405 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 535.801693 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1990.692549 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.184374 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.101899 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.585332 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.023685 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008176 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.976053 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32989 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31331 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4524 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 28295 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1895 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29170 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.503372 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.478073 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4931105 # Number of tag accesses -system.l2c.tags.data_accesses 4931105 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 82 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 29372 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 45566 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 34 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 41 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 8537 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5785 # number of ReadReq hits -system.l2c.ReadReq_hits::total 146639 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 227719 # number of Writeback hits -system.l2c.Writeback_hits::total 227719 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 770 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3132 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3862 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1497 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5359 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 82 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 29372 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49428 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 10034 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5785 # number of demand (read+write) hits -system.l2c.demand_hits::total 151998 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 82 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu0.inst 29372 # number of overall hits -system.l2c.overall_hits::cpu0.data 49428 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45492 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11667 # number of overall hits -system.l2c.overall_hits::cpu1.data 10034 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5785 # number of overall hits -system.l2c.overall_hits::total 151998 # number of overall hits +system.l2c.tags.occ_blocks::writebacks 11082.113172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.011404 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.058569 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7219.690376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2883.100910 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39595.862719 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1402.790170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 257.162663 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1460.646056 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.169100 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.110164 # 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number of overall MSHR misses +system.l2c.overall_mshr_misses::total 182121 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 462250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 140000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1200652248 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 648693692 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 154097993 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 45421500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 13719540491 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 153128559 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47338644 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 200467203 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8146450 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22467762 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 30614212 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 815815573 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457532278 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1273347851 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 462250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1200652248 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1464509265 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 154097993 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 502953778 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 14992888342 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 462250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1200652248 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1464509265 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 154097993 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 502953778 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 14992888342 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 549810500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5306549000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10505750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 321692750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6188558000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4079142000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 216691500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4295833500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 549810500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9385691000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10505750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538384250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10484391500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.162142 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071665 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.530177 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.760617 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.785334 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.766319 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.748760 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.881901 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.842338 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.719940 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.770275 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.738682 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281942 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.433731 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.544865 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281942 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.433731 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.544865 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74043.338888 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77776.541096 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 83286.026000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.231729 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17823.284639 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17843.097730 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17983.333333 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.297940 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17850.852478 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76674.395959 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67752.447505 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73210.363422 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2835,58 +2793,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 215303 # Transaction distribution -system.membus.trans_dist::ReadResp 215303 # Transaction distribution -system.membus.trans_dist::WriteReq 30982 # Transaction distribution -system.membus.trans_dist::WriteResp 30982 # Transaction distribution -system.membus.trans_dist::Writeback 135225 # Transaction distribution +system.membus.trans_dist::ReadReq 209058 # Transaction distribution +system.membus.trans_dist::ReadResp 209058 # Transaction distribution +system.membus.trans_dist::WriteReq 30943 # Transaction distribution +system.membus.trans_dist::WriteResp 30943 # Transaction distribution +system.membus.trans_dist::Writeback 128256 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 40350 # Transaction distribution -system.membus.trans_dist::ReadExResp 19836 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40095 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13060 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.membus.trans_dist::ReadExReq 37613 # Transaction distribution +system.membus.trans_dist::ReadExResp 17283 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13672 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 634735 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 756359 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 865267 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17575592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17765802 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123675 # Total snoops (count) -system.membus.snoop_fanout::samples 499419 # Request fanout histogram +system.membus.pkt_size::total 22401258 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125085 # Total snoops (count) +system.membus.snoop_fanout::samples 484369 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 484369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 499419 # Request fanout histogram -system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 484369 # Request fanout histogram +system.membus.reqLayer0.occupancy 88115000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1105573957 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1100453088 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37520484 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2919,44 +2877,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 286323 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 476594 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 476579 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30943 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30943 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 220623 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80382 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40416 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 120798 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 107 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50330 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50330 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1064234 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 261111 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1325345 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31566808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4207570 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 35774378 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 289326 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 860656 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.042449 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.201611 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 824122 95.76% 95.76% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36534 4.24% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 860656 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 750507689 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 653714719 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 219646363 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index b3648bdab..08c475a80 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.902862 # Number of seconds simulated -sim_ticks 2902861767000 # Number of ticks simulated -final_tick 2902861767000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903548 # Number of seconds simulated +sim_ticks 2903547931500 # Number of ticks simulated +final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 747193 # Simulator instruction rate (inst/s) -host_op_rate 900893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19275657141 # Simulator tick rate (ticks/s) -host_mem_usage 615228 # Number of bytes of host memory used -host_seconds 150.60 # Real time elapsed on the host -sim_insts 112525269 # Number of instructions simulated -sim_ops 135672104 # Number of ops (including micro ops) simulated +host_inst_rate 732027 # Simulator instruction rate (inst/s) +host_op_rate 882601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18897780106 # Simulator tick rate (ticks/s) +host_mem_usage 614620 # Number of bytes of host memory used +host_seconds 153.65 # Real time elapsed on the host +sim_insts 112472279 # Number of instructions simulated +sim_ops 135607130 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1191332 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1191972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9040292 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10178696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1191332 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1191332 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7576000 # Number of bytes written to this memory +system.physmem.bytes_read::total 10233800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1191972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1191972 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7641920 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7593524 # Number of bytes written to this memory +system.physmem.bytes_written::total 7659444 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27078 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141774 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168015 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118375 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168876 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119405 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122756 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123786 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 410399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3095507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 410523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3113533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3506435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 410399 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 410399 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2609838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2615875 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2609838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3524584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 410523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 410523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2631925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2637960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2631925 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 410399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3101543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 410523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3119568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6122310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168015 # Number of read requests accepted -system.physmem.writeReqs 158980 # Number of write requests accepted -system.physmem.readBursts 168015 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 158980 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10745280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 9814400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10178696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9911860 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5603 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4500 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9689 # Per bank write bursts -system.physmem.perBankRdBursts::1 9230 # Per bank write bursts -system.physmem.perBankRdBursts::2 10198 # Per bank write bursts -system.physmem.perBankRdBursts::3 10267 # Per bank write bursts -system.physmem.perBankRdBursts::4 18984 # Per bank write bursts -system.physmem.perBankRdBursts::5 10226 # Per bank write bursts -system.physmem.perBankRdBursts::6 10551 # Per bank write bursts -system.physmem.perBankRdBursts::7 10350 # Per bank write bursts -system.physmem.perBankRdBursts::8 9702 # Per bank write bursts -system.physmem.perBankRdBursts::9 9930 # Per bank write bursts -system.physmem.perBankRdBursts::10 9908 # Per bank write bursts -system.physmem.perBankRdBursts::11 8848 # Per bank write bursts -system.physmem.perBankRdBursts::12 9929 # Per bank write bursts -system.physmem.perBankRdBursts::13 10408 # Per bank write bursts -system.physmem.perBankRdBursts::14 9925 # Per bank write bursts -system.physmem.perBankRdBursts::15 9750 # Per bank write bursts -system.physmem.perBankWrBursts::0 9389 # Per bank write bursts -system.physmem.perBankWrBursts::1 8975 # Per bank write bursts -system.physmem.perBankWrBursts::2 10251 # Per bank write bursts -system.physmem.perBankWrBursts::3 9953 # Per bank write bursts -system.physmem.perBankWrBursts::4 9418 # Per bank write bursts -system.physmem.perBankWrBursts::5 9499 # Per bank write bursts -system.physmem.perBankWrBursts::6 9770 # Per bank write bursts -system.physmem.perBankWrBursts::7 9764 # Per bank write bursts -system.physmem.perBankWrBursts::8 9682 # Per bank write bursts -system.physmem.perBankWrBursts::9 9836 # Per bank write bursts -system.physmem.perBankWrBursts::10 9791 # Per bank write bursts -system.physmem.perBankWrBursts::11 9091 # Per bank write bursts -system.physmem.perBankWrBursts::12 9681 # Per bank write bursts -system.physmem.perBankWrBursts::13 9852 # Per bank write bursts -system.physmem.perBankWrBursts::14 9372 # Per bank write bursts -system.physmem.perBankWrBursts::15 9026 # Per bank write bursts +system.physmem.bw_total::total 6162545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168876 # Number of read requests accepted +system.physmem.writeReqs 160010 # Number of write requests accepted +system.physmem.readBursts 168876 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 160010 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10798592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 8731520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10233800 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9977780 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23557 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4508 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10030 # Per bank write bursts +system.physmem.perBankRdBursts::1 9665 # Per bank write bursts +system.physmem.perBankRdBursts::2 10302 # Per bank write bursts +system.physmem.perBankRdBursts::3 9920 # Per bank write bursts +system.physmem.perBankRdBursts::4 18863 # Per bank write bursts +system.physmem.perBankRdBursts::5 10093 # Per bank write bursts +system.physmem.perBankRdBursts::6 10296 # Per bank write bursts +system.physmem.perBankRdBursts::7 10601 # Per bank write bursts +system.physmem.perBankRdBursts::8 9928 # Per bank write bursts +system.physmem.perBankRdBursts::9 10198 # Per bank write bursts +system.physmem.perBankRdBursts::10 9956 # Per bank write bursts +system.physmem.perBankRdBursts::11 9036 # Per bank write bursts +system.physmem.perBankRdBursts::12 9857 # Per bank write bursts +system.physmem.perBankRdBursts::13 10481 # Per bank write bursts +system.physmem.perBankRdBursts::14 9974 # Per bank write bursts +system.physmem.perBankRdBursts::15 9528 # Per bank write bursts +system.physmem.perBankWrBursts::0 8313 # Per bank write bursts +system.physmem.perBankWrBursts::1 8253 # Per bank write bursts +system.physmem.perBankWrBursts::2 9067 # Per bank write bursts +system.physmem.perBankWrBursts::3 8494 # Per bank write bursts +system.physmem.perBankWrBursts::4 8419 # Per bank write bursts +system.physmem.perBankWrBursts::5 8394 # Per bank write bursts +system.physmem.perBankWrBursts::6 8676 # Per bank write bursts +system.physmem.perBankWrBursts::7 8975 # Per bank write bursts +system.physmem.perBankWrBursts::8 8824 # Per bank write bursts +system.physmem.perBankWrBursts::9 8984 # Per bank write bursts +system.physmem.perBankWrBursts::10 8586 # Per bank write bursts +system.physmem.perBankWrBursts::11 8136 # Per bank write bursts +system.physmem.perBankWrBursts::12 8548 # Per bank write bursts +system.physmem.perBankWrBursts::13 8715 # Per bank write bursts +system.physmem.perBankWrBursts::14 8203 # Per bank write bursts +system.physmem.perBankWrBursts::15 7843 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2902861390500 # Total gap between requests +system.physmem.numWrRetry 46 # Number of times write queue was full causing retry +system.physmem.totGap 2903547607000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158443 # Read request sizes (log2) +system.physmem.readPktSize::6 159304 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 154599 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 246 # What read queue length does an incoming req see +system.physmem.writePktSize::6 155629 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 242 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,178 +159,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 337.252977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.461800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 352.629111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21587 35.41% 35.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14795 24.27% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5550 9.10% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3419 5.61% 74.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2349 3.85% 78.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.59% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1011 1.66% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1092 1.79% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9583 15.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60962 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6214 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.016254 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 542.923852 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6212 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6318 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 324.004977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.393020 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.651376 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21725 36.04% 36.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14933 24.77% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5631 9.34% 70.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3281 5.44% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2561 4.25% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1497 2.48% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1055 1.75% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1109 1.84% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8485 14.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60277 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.709319 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 577.316613 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5492 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6214 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6214 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.678146 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.366342 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.738225 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5089 81.90% 81.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 32 0.51% 82.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.39% 82.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 212 3.41% 86.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 128 2.06% 88.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 65 1.05% 89.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 41 0.66% 89.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 30 0.48% 90.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 138 2.22% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.26% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 13 0.21% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.26% 93.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 29 0.47% 93.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 17 0.27% 94.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 11 0.18% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 29 0.47% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 66 1.06% 95.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.13% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.05% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 17 0.27% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 91 1.46% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 15 0.24% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 8 0.13% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 6 0.10% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.18% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 39 0.63% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.11% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.14% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.05% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.08% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.08% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 4 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6214 # Writes before turning the bus around for reads -system.physmem.totQLat 1487834250 # Total ticks spent queuing -system.physmem.totMemAccLat 4635865500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 839475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8861.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5494 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5494 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.832545 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.556239 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 46.623010 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5170 94.10% 94.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 87 1.58% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.31% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.22% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 19 0.35% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 28 0.51% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 22 0.40% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 14 0.25% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 9 0.16% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 4 0.07% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 29 0.53% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 12 0.22% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 6 0.11% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 2 0.04% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.04% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.13% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 8 0.15% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 4 0.07% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 4 0.07% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 10 0.18% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 6 0.11% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5494 # Writes before turning the bus around for reads +system.physmem.totQLat 1499821694 # Total ticks spent queuing +system.physmem.totMemAccLat 4663471694 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 843640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8888.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27611.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27638.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing -system.physmem.readRowHits 138089 # Number of row buffer hits during reads -system.physmem.writeRowHits 122193 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.67 # Row buffer hit rate for writes -system.physmem.avgGap 8877387.70 # Average gap between requests -system.physmem.pageHitRate 81.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 235320120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128398875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 698061000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 499083120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86740865775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665624160500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943526211470 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.522458 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770750790000 # Time in different power states -system.physmem_0.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing +system.physmem.readRowHits 138826 # Number of row buffer hits during reads +system.physmem.writeRowHits 106054 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.72 # Row buffer hit rate for writes +system.physmem.avgGap 8828431.76 # Average gap between requests +system.physmem.pageHitRate 80.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 233551080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127433625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 700206000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 444469680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87280455420 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665566622000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1943998321725 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.525264 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770655896974 # Time in different power states +system.physmem_0.memoryStateTime::REF 96955820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35170942500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35935671776 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 225552600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123069375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 611512200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 494624880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85548905145 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666669740000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943273726280 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.435479 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772511956000 # Time in different power states -system.physmem_1.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_1.actEnergy 222143040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121209000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 615864600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 439596720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85782200445 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1666880880750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943707478475 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.425095 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2772857314224 # Time in different power states +system.physmem_1.memoryStateTime::REF 96955820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33417040500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33734699276 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -380,57 +365,57 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9552 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9552 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1261 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9552 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9552 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7388 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9945.756632 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7345.780525 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7322.338006 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 5745 77.76% 77.76% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1639 22.18% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-81919 2 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7388 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 809108000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 809108000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 809108000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6174 83.57% 83.57% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1214 16.43% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7388 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 9545 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9545 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1267 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8278 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9545 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9545 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9545 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7381 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10696.619699 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8418.408390 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7914.312600 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7376 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 1 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7381 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6161 83.47% 83.47% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1220 16.53% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7381 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9545 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9545 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7381 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16940 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7381 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16926 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24537663 # DTB read hits -system.cpu.dtb.read_misses 8142 # DTB read misses -system.cpu.dtb.write_hits 19618927 # DTB write hits -system.cpu.dtb.write_misses 1410 # DTB write misses +system.cpu.dtb.read_hits 24524755 # DTB read hits +system.cpu.dtb.read_misses 8132 # DTB read misses +system.cpu.dtb.write_hits 19610055 # DTB write hits +system.cpu.dtb.write_misses 1413 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1664 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1678 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24545805 # DTB read accesses -system.cpu.dtb.write_accesses 19620337 # DTB write accesses +system.cpu.dtb.read_accesses 24532887 # DTB read accesses +system.cpu.dtb.write_accesses 19611468 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44156590 # DTB hits -system.cpu.dtb.misses 9552 # DTB misses -system.cpu.dtb.accesses 44166142 # DTB accesses +system.cpu.dtb.hits 44134810 # DTB hits +system.cpu.dtb.misses 9545 # DTB misses +system.cpu.dtb.accesses 44144355 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,18 +453,18 @@ system.cpu.itb.walker.walkWaitTime::samples 4762 # system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 9893.949147 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7210.941913 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7351.443657 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1400 45.06% 45.06% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1004 32.31% 77.37% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 701 22.56% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10683.778565 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8326.699765 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7409.739384 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1442 46.41% 46.41% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 985 31.70% 78.11% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 678 21.82% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated @@ -490,7 +475,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115624412 # ITB inst hits +system.cpu.itb.inst_hits 115569545 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -507,38 +492,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115629174 # ITB inst accesses -system.cpu.itb.hits 115624412 # DTB hits +system.cpu.itb.inst_accesses 115574307 # ITB inst accesses +system.cpu.itb.hits 115569545 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115629174 # DTB accesses -system.cpu.numCycles 5805723534 # number of cpu cycles simulated +system.cpu.itb.accesses 115574307 # DTB accesses +system.cpu.numCycles 5807095863 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112525269 # Number of instructions committed -system.cpu.committedOps 135672104 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119969678 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses -system.cpu.num_func_calls 9899985 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15238216 # number of instructions that are conditional controls -system.cpu.num_int_insts 119969678 # number of integer instructions -system.cpu.num_fp_insts 11290 # number of float instructions -system.cpu.num_int_register_reads 218203287 # number of times the integer registers were read -system.cpu.num_int_register_writes 82701548 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read +system.cpu.committedInsts 112472279 # Number of instructions committed +system.cpu.committedOps 135607130 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119910547 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses +system.cpu.num_func_calls 9892504 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15232384 # number of instructions that are conditional controls +system.cpu.num_int_insts 119910547 # number of integer instructions +system.cpu.num_fp_insts 11161 # number of float instructions +system.cpu.num_int_register_reads 218091200 # number of times the integer registers were read +system.cpu.num_int_register_writes 82658465 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 490054820 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51921339 # number of times the CC registers were written -system.cpu.num_mem_refs 45438019 # number of memory refs -system.cpu.num_load_insts 24860597 # Number of load instructions -system.cpu.num_store_insts 20577422 # Number of store instructions -system.cpu.num_idle_cycles 5386825418.146145 # Number of idle cycles -system.cpu.num_busy_cycles 418898115.853856 # Number of busy cycles -system.cpu.not_idle_fraction 0.072153 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927847 # Percentage of idle cycles -system.cpu.Branches 25932360 # Number of branches fetched +system.cpu.num_cc_register_reads 489812948 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51900975 # number of times the CC registers were written +system.cpu.num_mem_refs 45415290 # number of memory refs +system.cpu.num_load_insts 24846976 # Number of load instructions +system.cpu.num_store_insts 20568314 # Number of store instructions +system.cpu.num_idle_cycles 5385642355.670145 # Number of idle cycles +system.cpu.num_busy_cycles 421453507.329855 # Number of busy cycles +system.cpu.not_idle_fraction 0.072576 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927424 # Percentage of idle cycles +system.cpu.Branches 25918910 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93231199 67.17% 67.17% # Class of executed instruction -system.cpu.op_class::IntMult 114517 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93186875 67.17% 67.17% # Class of executed instruction +system.cpu.op_class::IntMult 114498 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -562,194 +547,194 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8515 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8463 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24860597 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20577422 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24846976 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20568314 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138794587 # Class of executed instruction +system.cpu.op_class::total 138727463 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 823321 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.850573 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43261398 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 823833 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.512339 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.850573 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 820494 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.827736 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43242693 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821006 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.670374 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1008712250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.827736 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177233078 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177233078 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23126684 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23126684 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18835651 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18835651 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392122 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392122 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443636 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443636 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460570 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460570 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41962335 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41962335 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42354457 # number of overall hits -system.cpu.dcache.overall_hits::total 42354457 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 402703 # 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average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26595.118287 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26595.118287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22746.698915 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22746.698915 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.294118 # 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number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483461242 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17483461242 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18953838790 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18953838790 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5833129500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5833129500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4513032000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4513032000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346161500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346161500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227594 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227594 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018323 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018323 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016433 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016433 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018949 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018949 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.667797 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.667797 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36769.808106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36769.808106 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699137 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1699137 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1699137 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56095 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995819 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26260695 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26260695 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6986 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3658 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1683931 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 515395 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2209970 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63605.607515 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.002083 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10067.420664 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10067.420664 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56394.202727 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56394.202727 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442752 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442752 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063766 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063766 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68170.652715 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70318.591529 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69043.889596 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17820.823139 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17820.823139 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63935.576709 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63935.576709 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1119,61 +1104,59 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2297061 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2297046 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 686487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2733 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 683915 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2737 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3422037 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108963064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96860105 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205865781 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53107 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3278617 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011120 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104863 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295956 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3416297 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2449150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12768 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5902843 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108779512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96514397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14212 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53413 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3242159 98.89% 98.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3278617 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2355272500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2567431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2563126749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1312657000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1308606460 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17843250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17823250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1194,11 +1177,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1219,11 +1202,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1263,23 +1246,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347060139 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198904691 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804507 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36849506 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134613 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.079220 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 298400039000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134613 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309085643000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.079220 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067451 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067451 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1293,14 +1276,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9587408255 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9587408255 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28886876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28886876 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649316309 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6649316309 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28886876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28886876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28886876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28886876 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1317,19 +1300,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55358 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123448.188034 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123448.188034 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183561.073018 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183561.073018 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123448.188034 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123448.188034 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22762 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7146 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.746711 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.636152 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1343,14 +1326,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7703746269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7703746269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16499876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16499876 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4765656321 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4765656321 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16499876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16499876 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16499876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16499876 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1359,66 +1342,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70512.290598 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70512.290598 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131560.742077 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131560.742077 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70661 # Transaction distribution -system.membus.trans_dist::ReadResp 70661 # Transaction distribution -system.membus.trans_dist::WriteReq 27618 # Transaction distribution -system.membus.trans_dist::WriteResp 27618 # Transaction distribution -system.membus.trans_dist::Writeback 118375 # Transaction distribution +system.membus.trans_dist::ReadReq 70719 # Transaction distribution +system.membus.trans_dist::ReadResp 70719 # Transaction distribution +system.membus.trans_dist::WriteReq 27589 # Transaction distribution +system.membus.trans_dist::WriteResp 27589 # Transaction distribution +system.membus.trans_dist::Writeback 119405 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4508 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution -system.membus.trans_dist::ReadExReq 128454 # Transaction distribution -system.membus.trans_dist::ReadExResp 128454 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4510 # Transaction distribution +system.membus.trans_dist::ReadExReq 129241 # Transaction distribution +system.membus.trans_dist::ReadExResp 129241 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436226 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546586 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 652795 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 655473 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15455100 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15618561 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15576124 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15739477 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20254017 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 318040 # Request fanout histogram +system.membus.snoop_fanout::samples 319985 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 318040 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 318040 # Request fanout histogram -system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 319985 # Request fanout histogram +system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1758500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1589750000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594947750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38337493 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 980923653 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 964658040 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37509494 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index f0c87683a..33aa26eaf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867165000 # Number of ticks simulated -final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783867052000 # Number of ticks simulated +final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1311458 # Simulator instruction rate (inst/s) -host_op_rate 1596489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25571502260 # Simulator tick rate (ticks/s) -host_mem_usage 616488 # Number of bytes of host memory used -host_seconds 108.87 # Real time elapsed on the host -sim_insts 142773109 # Number of instructions simulated -sim_ops 173803334 # Number of ops (including micro ops) simulated +host_inst_rate 1291395 # Simulator instruction rate (inst/s) +host_op_rate 1572066 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25180347721 # Simulator tick rate (ticks/s) +host_mem_usage 616688 # Number of bytes of host memory used +host_seconds 110.56 # Real time elapsed on the host +sim_insts 142772879 # Number of instructions simulated +sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 728420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 728356 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 4660384 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 482432 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 5667588 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11540296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 728420 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 11540232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 728356 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 482432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8837248 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8837184 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8854772 # Number of bytes written to this memory +system.physmem.bytes_written::total 8854708 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19835 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19834 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 73337 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 7538 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 88557 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189290 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138082 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189289 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138081 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142463 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142462 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 261658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 261635 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 1674068 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 173296 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 2035869 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4145419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 261658 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4145396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 261635 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 173296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3174450 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3174427 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3180745 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3174450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3180722 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3174427 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 261658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 261635 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 1680360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 173296 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 2035872 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7326164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7326119 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -116,45 +116,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5682 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5682 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5682 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5682 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 5683 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5683 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5683 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5683 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5683 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.42% 65.42% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1612 34.58% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4661 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.40% 65.40% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1613 34.60% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4662 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5683 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5682 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5683 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4662 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4661 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10343 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4662 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10345 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15994592 # DTB read hits -system.cpu0.dtb.read_misses 4787 # DTB read misses -system.cpu0.dtb.write_hits 11285776 # DTB write hits +system.cpu0.dtb.read_hits 15994593 # DTB read hits +system.cpu0.dtb.read_misses 4788 # DTB read misses +system.cpu0.dtb.write_hits 11285810 # DTB write hits system.cpu0.dtb.write_misses 895 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 394 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3233 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3234 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 774 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 773 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 200 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 15999379 # DTB read accesses -system.cpu0.dtb.write_accesses 11286671 # DTB write accesses +system.cpu0.dtb.read_accesses 15999381 # DTB read accesses +system.cpu0.dtb.write_accesses 11286705 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27280368 # DTB hits -system.cpu0.dtb.misses 5682 # DTB misses -system.cpu0.dtb.accesses 27286050 # DTB accesses +system.cpu0.dtb.hits 27280403 # DTB hits +system.cpu0.dtb.misses 5683 # DTB misses +system.cpu0.dtb.accesses 27286086 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -202,7 +202,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74779253 # ITB inst hits +system.cpu0.itb.inst_hits 74779098 # ITB inst hits system.cpu0.itb.inst_misses 2611 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -219,38 +219,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74781864 # ITB inst accesses -system.cpu0.itb.hits 74779253 # DTB hits +system.cpu0.itb.inst_accesses 74781709 # ITB inst accesses +system.cpu0.itb.hits 74779098 # DTB hits system.cpu0.itb.misses 2611 # DTB misses -system.cpu0.itb.accesses 74781864 # DTB accesses -system.cpu0.numCycles 5536444795 # number of cpu cycles simulated +system.cpu0.itb.accesses 74781709 # DTB accesses +system.cpu0.numCycles 5536444792 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72626511 # Number of instructions committed -system.cpu0.committedOps 87972361 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77485845 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5272 # Number of float alu accesses -system.cpu0.num_func_calls 8692455 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9458284 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77485845 # number of integer instructions -system.cpu0.num_fp_insts 5272 # number of float instructions -system.cpu0.num_int_register_reads 144065543 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54441741 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4114 # number of times the floating registers were read +system.cpu0.committedInsts 72626333 # Number of instructions committed +system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5256 # Number of float alu accesses +system.cpu0.num_func_calls 8692525 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9458276 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77485858 # number of integer instructions +system.cpu0.num_fp_insts 5256 # number of float instructions +system.cpu0.num_int_register_reads 144065688 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54441738 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4098 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1160 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268855206 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31825195 # number of times the CC registers were written -system.cpu0.num_mem_refs 27911692 # number of memory refs -system.cpu0.num_load_insts 16162187 # Number of load instructions -system.cpu0.num_store_insts 11749505 # Number of store instructions -system.cpu0.num_idle_cycles 5353607103.050808 # Number of idle cycles -system.cpu0.num_busy_cycles 182837691.949192 # Number of busy cycles +system.cpu0.num_cc_register_reads 268855171 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31825079 # number of times the CC registers were written +system.cpu0.num_mem_refs 27911721 # number of memory refs +system.cpu0.num_load_insts 16162181 # Number of load instructions +system.cpu0.num_store_insts 11749540 # Number of store instructions +system.cpu0.num_idle_cycles 5353607317.458248 # Number of idle cycles +system.cpu0.num_busy_cycles 182837474.541752 # Number of busy cycles system.cpu0.not_idle_fraction 0.033024 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.966976 # Percentage of idle cycles -system.cpu0.Branches 18597060 # Number of branches fetched +system.cpu0.Branches 18597106 # Number of branches fetched system.cpu0.op_class::No_OpClass 2189 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61764761 68.82% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59661 0.07% 68.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 61764727 68.82% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59660 0.07% 68.89% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction @@ -274,25 +274,25 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.89% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4406 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4403 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16162187 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11749505 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16162181 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89742709 # Class of executed instruction +system.cpu0.op_class::total 89742700 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 819403 # number of replacements +system.cpu0.dcache.tags.replacements 819402 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53784478 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597627 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597629 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821680 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175494 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821817 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175357 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929339 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070655 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy @@ -301,86 +301,86 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219237567 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219237567 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15302739 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14826353 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30129092 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10898468 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11441639 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186053 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209002 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395055 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235062 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222268 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 219237306 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219237306 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15302738 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14826284 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30129022 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10898497 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11441613 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186051 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209007 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395058 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235059 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222271 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 457330 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236768 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223368 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236765 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223371 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26201207 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26267992 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52469199 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26387260 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26476994 # number of overall hits -system.cpu0.dcache.overall_hits::total 52864254 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197067 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 199240 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396307 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137729 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 163949 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 26201235 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26267897 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52469132 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26387286 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26476904 # number of overall hits +system.cpu0.dcache.overall_hits::total 52864190 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197065 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 199241 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396306 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137741 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 163937 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 301678 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54389 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61684 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54401 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61672 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 116073 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4662 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3967 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334796 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 363189 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697985 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389185 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424873 # number of overall misses -system.cpu0.dcache.overall_misses::total 814058 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15499806 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15025593 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11036197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11605588 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240442 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270686 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511128 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239724 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226235 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 334806 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 363178 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697984 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389207 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424850 # number of overall misses +system.cpu0.dcache.overall_misses::total 814057 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15499803 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15025525 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11036238 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11605550 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240452 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270679 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511131 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239721 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226238 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236768 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223370 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236765 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223373 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26536003 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631181 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26776445 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26901867 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53678312 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26536041 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631075 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26776493 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26901754 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53678247 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012714 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013260 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012480 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014127 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012481 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014126 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226204 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227880 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227092 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019447 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226245 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227842 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227091 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019448 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017535 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012617 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013638 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013637 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014535 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015793 # miss rate for overall accesses @@ -393,19 +393,19 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682284 # number of writebacks -system.cpu0.dcache.writebacks::total 682284 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682283 # number of writebacks +system.cpu0.dcache.writebacks::total 682283 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1699220 # number of replacements +system.cpu0.icache.tags.replacements 1699214 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145342961 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 145342721 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127365 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536315 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127325 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536356 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888921 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110422 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110423 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id @@ -413,43 +413,43 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148742437 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148742437 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73936562 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71406399 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145342961 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73936562 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71406399 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145342961 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73936562 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71406399 # number of overall hits -system.cpu0.icache.overall_hits::total 145342961 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844577 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855161 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699738 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844577 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855161 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699738 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844577 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855161 # number of overall misses -system.cpu0.icache.overall_misses::total 1699738 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74781139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261560 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74781139 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72261560 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74781139 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72261560 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 148742185 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148742185 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73936444 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71406277 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145342721 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73936444 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71406277 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145342721 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73936444 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71406277 # number of overall hits +system.cpu0.icache.overall_hits::total 145342721 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844540 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855192 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699732 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844540 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855192 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699732 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844540 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855192 # number of overall misses +system.cpu0.icache.overall_misses::total 1699732 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74780984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261469 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74780984 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72261469 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74780984 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72261469 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011294 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011834 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011835 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011294 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011834 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011835 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011294 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011834 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011835 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -509,25 +509,25 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060 system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15530019 # DTB read hits -system.cpu1.dtb.read_misses 5412 # DTB read misses -system.cpu1.dtb.write_hits 11838449 # DTB write hits -system.cpu1.dtb.write_misses 791 # DTB write misses +system.cpu1.dtb.read_hits 15529940 # DTB read hits +system.cpu1.dtb.read_misses 5414 # DTB read misses +system.cpu1.dtb.write_hits 11838406 # DTB write hits +system.cpu1.dtb.write_misses 789 # DTB write misses system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 3183 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 911 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 909 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15535431 # DTB read accesses -system.cpu1.dtb.write_accesses 11839240 # DTB write accesses +system.cpu1.dtb.read_accesses 15535354 # DTB read accesses +system.cpu1.dtb.write_accesses 11839195 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27368468 # DTB hits +system.cpu1.dtb.hits 27368346 # DTB hits system.cpu1.dtb.misses 6203 # DTB misses -system.cpu1.dtb.accesses 27374671 # DTB accesses +system.cpu1.dtb.accesses 27374549 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -557,26 +557,26 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3040 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3040 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walkWaitTime::samples 3040 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3040 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 3041 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3041 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 3041 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3041 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3041 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1720 81.52% 81.52% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 390 18.48% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1721 81.53% 81.53% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 390 18.47% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2111 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3040 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3041 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3041 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5150 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 72259450 # ITB inst hits -system.cpu1.itb.inst_misses 3040 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2111 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2111 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5152 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 72259358 # ITB inst hits +system.cpu1.itb.inst_misses 3041 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -585,45 +585,45 @@ system.cpu1.itb.flush_tlb 2817 # Nu system.cpu1.itb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2022 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72262490 # ITB inst accesses -system.cpu1.itb.hits 72259450 # DTB hits -system.cpu1.itb.misses 3040 # DTB misses -system.cpu1.itb.accesses 72262490 # DTB accesses -system.cpu1.numCycles 88040872 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 72262399 # ITB inst accesses +system.cpu1.itb.hits 72259358 # DTB hits +system.cpu1.itb.misses 3041 # DTB misses +system.cpu1.itb.accesses 72262399 # DTB accesses +system.cpu1.numCycles 88040649 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 70146598 # Number of instructions committed -system.cpu1.committedOps 85830973 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75676981 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6212 # Number of float alu accesses -system.cpu1.num_func_calls 8181424 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9272106 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75676981 # number of integer instructions -system.cpu1.num_fp_insts 6212 # number of float instructions -system.cpu1.num_int_register_reads 140994581 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52737823 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4658 # number of times the floating registers were read +system.cpu1.committedInsts 70146546 # Number of instructions committed +system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6228 # Number of float alu accesses +system.cpu1.num_func_calls 8181374 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9272054 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75676825 # number of integer instructions +system.cpu1.num_fp_insts 6228 # number of float instructions +system.cpu1.num_int_register_reads 140994115 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52737742 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4674 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1556 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261999475 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30539263 # number of times the CC registers were written -system.cpu1.num_mem_refs 28027673 # number of memory refs -system.cpu1.num_load_insts 15693775 # Number of load instructions -system.cpu1.num_store_insts 12333898 # Number of store instructions -system.cpu1.num_idle_cycles 85385179.520823 # Number of idle cycles -system.cpu1.num_busy_cycles 2655692.479177 # Number of busy cycles +system.cpu1.num_cc_register_reads 261998832 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30539220 # number of times the CC registers were written +system.cpu1.num_mem_refs 28027555 # number of memory refs +system.cpu1.num_load_insts 15693703 # Number of load instructions +system.cpu1.num_store_insts 12333852 # Number of store instructions +system.cpu1.num_idle_cycles 85384966.713327 # Number of idle cycles +system.cpu1.num_busy_cycles 2655682.286673 # Number of busy cycles system.cpu1.not_idle_fraction 0.030164 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969836 # Percentage of idle cycles -system.cpu1.Branches 17799968 # Number of branches fetched +system.cpu1.Branches 17799875 # Number of branches fetched system.cpu1.op_class::No_OpClass 148 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59388214 67.89% 67.89% # Class of executed instruction -system.cpu1.op_class::IntMult 57231 0.07% 67.96% # Class of executed instruction +system.cpu1.op_class::IntAlu 59388111 67.89% 67.89% # Class of executed instruction +system.cpu1.op_class::IntMult 57232 0.07% 67.96% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.96% # Class of executed instruction @@ -647,23 +647,23 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.96% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4163 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4166 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::MemRead 15693775 17.94% 85.90% # Class of executed instruction -system.cpu1.op_class::MemWrite 12333898 14.10% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 15693703 17.94% 85.90% # Class of executed instruction +system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87477429 # Class of executed instruction +system.cpu1.op_class::total 87477212 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 30171 # Transaction distribution -system.iobus.trans_dist::ReadResp 30171 # Transaction distribution -system.iobus.trans_dist::WriteReq 59016 # Transaction distribution -system.iobus.trans_dist::WriteResp 22792 # Transaction distribution +system.iobus.trans_dist::ReadReq 30164 # Transaction distribution +system.iobus.trans_dist::ReadResp 30164 # Transaction distribution +system.iobus.trans_dist::WriteReq 59002 # Transaction distribution +system.iobus.trans_dist::WriteResp 22778 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -684,11 +684,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -709,17 +709,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -762,20 +762,20 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 110021 # number of replacements -system.l2c.tags.tagsinuse 65155.309065 # Cycle average of tags in use -system.l2c.tags.total_refs 2731330 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175302 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 15.580712 # Average number of references to valid blocks. +system.l2c.tags.replacements 110020 # number of replacements +system.l2c.tags.tagsinuse 65155.309107 # Cycle average of tags in use +system.l2c.tags.total_refs 2731325 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 175301 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 15.580772 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48893.434420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48893.438134 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5044.359026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4729.332054 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5044.354241 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4729.333214 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 4020.194257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2464.086185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2464.086137 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -795,143 +795,143 @@ system.l2c.tags.age_task_id_blocks_1024::3 10700 # system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26231923 # Number of tag accesses -system.l2c.tags.data_accesses 26231923 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4699 # number of ReadReq hits +system.l2c.tags.tag_accesses 26231874 # Number of tag accesses +system.l2c.tags.data_accesses 26231874 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4700 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 833747 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 246348 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5000 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 833711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 246358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 847615 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 259132 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2201281 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682284 # number of Writeback hits -system.l2c.Writeback_hits::total 682284 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 847646 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 259121 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2201277 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 682283 # number of Writeback hits +system.l2c.Writeback_hits::total 682283 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72504 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78554 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 72515 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78543 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 151058 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4699 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.dtb.walker 4700 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 2287 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833747 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 318852 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5000 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833711 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 318873 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5001 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 2453 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847615 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337686 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352339 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4699 # number of overall hits +system.l2c.demand_hits::cpu1.inst 847646 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337664 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352335 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4700 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 2287 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833747 # number of overall hits -system.l2c.overall_hits::cpu0.data 318852 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5000 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833711 # number of overall hits +system.l2c.overall_hits::cpu0.data 318873 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5001 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 2453 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847615 # number of overall hits -system.l2c.overall_hits::cpu1.data 337686 # number of overall hits -system.l2c.overall_hits::total 2352339 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847646 # number of overall hits +system.l2c.overall_hits::cpu1.data 337664 # number of overall hits +system.l2c.overall_hits::total 2352335 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10820 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 10819 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 9770 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 7538 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 5759 # number of ReadReq misses -system.l2c.ReadReq_misses::total 33895 # number of ReadReq misses +system.l2c.ReadReq_misses::total 33894 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63963 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83901 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 63964 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83900 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10820 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73733 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10819 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73734 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 7538 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89660 # number of demand (read+write) misses -system.l2c.demand_misses::total 181759 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89659 # number of demand (read+write) misses +system.l2c.demand_misses::total 181758 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10820 # number of overall misses -system.l2c.overall_misses::cpu0.data 73733 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10819 # number of overall misses +system.l2c.overall_misses::cpu0.data 73734 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu1.inst 7538 # number of overall misses -system.l2c.overall_misses::cpu1.data 89660 # number of overall misses -system.l2c.overall_misses::total 181759 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4704 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.data 89659 # number of overall misses +system.l2c.overall_misses::total 181758 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4705 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 2288 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 844567 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 256118 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5002 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 844530 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 256128 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5003 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 855153 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 264891 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2235176 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682284 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682284 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 855184 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 264880 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2235171 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 682283 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 682283 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136467 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162455 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 136479 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162443 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4704 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 4705 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 2288 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844567 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392585 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5002 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844530 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392607 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5003 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 2453 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855153 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427346 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2534098 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4704 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855184 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427323 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2534093 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4705 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 2288 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844567 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392585 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5002 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844530 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392607 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5003 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 2453 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855153 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427346 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2534098 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855184 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427323 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2534093 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.012811 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038146 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038145 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008815 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021741 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008814 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.021742 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.015164 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989699 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989960 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.468707 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.516457 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.468673 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.516489 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.012811 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187806 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008815 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209807 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209816 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.071725 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.012811 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187806 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008815 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209807 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209816 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.071725 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -941,14 +941,14 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101892 # number of writebacks -system.l2c.writebacks::total 101892 # number of writebacks +system.l2c.writebacks::writebacks 101891 # number of writebacks +system.l2c.writebacks::total 101891 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74229 # Transaction distribution -system.membus.trans_dist::ReadResp 74229 # Transaction distribution -system.membus.trans_dist::WriteReq 27560 # Transaction distribution -system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 138082 # Transaction distribution +system.membus.trans_dist::ReadReq 74221 # Transaction distribution +system.membus.trans_dist::ReadResp 74221 # Transaction distribution +system.membus.trans_dist::WriteReq 27546 # Transaction distribution +system.membus.trans_dist::WriteResp 27546 # Transaction distribution +system.membus.trans_dist::Writeback 138081 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -956,34 +956,34 @@ system.membus.trans_dist::SCUpgradeReq 2 # Tr system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 606178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 606133 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 715296 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 715251 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095676 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18258691 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095548 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18258521 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22908547 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22908377 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 359035 # Request fanout histogram +system.membus.snoop_fanout::samples 359033 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 359035 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 359033 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 359035 # Request fanout histogram +system.membus.snoop_fanout::total 359033 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1015,41 +1015,39 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2291995 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291995 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682284 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2291984 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 682283 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417520 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20800 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41508 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5924754 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96324555 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83016 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205268491 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417508 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444881 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5924703 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96324385 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205267949 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36631 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3272329 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011143 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3272324 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011143 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.104971 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3235865 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3235860 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 36464 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3272329 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3272324 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 83b8a4ab7..b412f009d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.177080 # Number of seconds simulated -sim_ticks 47177080006500 # Number of ticks simulated -final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.216814 # Number of seconds simulated +sim_ticks 47216814145000 # Number of ticks simulated +final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1049876 # Simulator instruction rate (inst/s) -host_op_rate 1235062 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50706899360 # Simulator tick rate (ticks/s) -host_mem_usage 670076 # Number of bytes of host memory used -host_seconds 930.39 # Real time elapsed on the host -sim_insts 976792036 # Number of instructions simulated -sim_ops 1149086878 # Number of ops (including micro ops) simulated +host_inst_rate 1225013 # Simulator instruction rate (inst/s) +host_op_rate 1441119 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59296512316 # Simulator tick rate (ticks/s) +host_mem_usage 723320 # Number of bytes of host memory used +host_seconds 796.28 # Real time elapsed on the host +sim_insts 975457230 # Number of instructions simulated +sim_ops 1147538415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 149696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 124032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3867700 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35125336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 224640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 222848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2692808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 38798848 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 404992 # Number of bytes read from this memory -system.physmem.bytes_read::total 81610900 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3867700 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2692808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 100759808 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 154048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3911220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35234584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 222912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 221184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2638152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 38475968 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 412928 # Number of bytes read from this memory +system.physmem.bytes_read::total 81399700 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3911220 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2638152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6549372 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 100563072 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 100780624 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2339 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1938 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 100840 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 548855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3510 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3482 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 42182 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 606250 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6328 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315724 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1574372 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 100583888 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2407 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 101520 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 550562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3483 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 601205 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6452 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1312424 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1571298 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1576975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 744542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 57079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 822409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1729885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 57079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 139061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2135779 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1573901 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 746230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 55873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 814879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1723956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 55873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 138708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2129815 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2136220 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2135779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 744984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 57079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 822409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3866105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2130256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2129815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 746670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 55873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 814879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3854211 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -134,45 +134,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 123914 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 123914 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 123914 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 123914 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 125229 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95376 89.74% 89.74% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10905 10.26% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 106281 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123914 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106281 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 230195 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91355479 # DTB read hits -system.cpu0.dtb.read_misses 87819 # DTB read misses -system.cpu0.dtb.write_hits 84601943 # DTB write hits -system.cpu0.dtb.write_misses 36095 # DTB write misses +system.cpu0.dtb.read_hits 92662773 # DTB read hits +system.cpu0.dtb.read_misses 88786 # DTB read misses +system.cpu0.dtb.write_hits 85694958 # DTB write hits +system.cpu0.dtb.write_misses 36443 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36260 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5461 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10344 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91443298 # DTB read accesses -system.cpu0.dtb.write_accesses 84638038 # DTB write accesses +system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 92751559 # DTB read accesses +system.cpu0.dtb.write_accesses 85731401 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 175957422 # DTB hits -system.cpu0.dtb.misses 123914 # DTB misses -system.cpu0.dtb.accesses 176081336 # DTB accesses +system.cpu0.dtb.hits 178357731 # DTB hits +system.cpu0.dtb.misses 125229 # DTB misses +system.cpu0.dtb.accesses 178482960 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -202,187 +202,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 60226 # Table walker walks requested -system.cpu0.itb.walker.walksLong 60226 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 60226 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 60226 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 61377 # Table walker walks requested +system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54190 98.81% 98.81% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 654 1.19% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 54844 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60226 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54844 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54844 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 115070 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 491372488 # ITB inst hits -system.cpu0.itb.inst_misses 60226 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 497696393 # ITB inst hits +system.cpu0.itb.inst_misses 61377 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25015 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 491432714 # ITB inst accesses -system.cpu0.itb.hits 491372488 # DTB hits -system.cpu0.itb.misses 60226 # DTB misses -system.cpu0.itb.accesses 491432714 # DTB accesses -system.cpu0.numCycles 94354173207 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses +system.cpu0.itb.hits 497696393 # DTB hits +system.cpu0.itb.misses 61377 # DTB misses +system.cpu0.itb.accesses 497757770 # DTB accesses +system.cpu0.numCycles 94433641544 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 491139120 # Number of instructions committed -system.cpu0.committedOps 577575160 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 529301791 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 523058 # Number of float alu accesses -system.cpu0.num_func_calls 28573576 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 75495865 # number of instructions that are conditional controls -system.cpu0.num_int_insts 529301791 # number of integer instructions -system.cpu0.num_fp_insts 523058 # number of float instructions -system.cpu0.num_int_register_reads 775565033 # number of times the integer registers were read -system.cpu0.num_int_register_writes 419986522 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 843711 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 444676 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132153354 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 131825344 # number of times the CC registers were written -system.cpu0.num_mem_refs 176058068 # number of memory refs -system.cpu0.num_load_insts 91428761 # Number of load instructions -system.cpu0.num_store_insts 84629307 # Number of store instructions -system.cpu0.num_idle_cycles 93776262262.183929 # Number of idle cycles -system.cpu0.num_busy_cycles 577910944.816068 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006125 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993875 # Percentage of idle cycles -system.cpu0.Branches 109891880 # Number of branches fetched +system.cpu0.committedInsts 497466384 # Number of instructions committed +system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses +system.cpu0.num_func_calls 28869117 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls +system.cpu0.num_int_insts 536103359 # number of integer instructions +system.cpu0.num_fp_insts 526132 # number of float instructions +system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read +system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written +system.cpu0.num_mem_refs 178459396 # number of memory refs +system.cpu0.num_load_insts 92737001 # Number of load instructions +system.cpu0.num_store_insts 85722395 # Number of store instructions +system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles +system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles +system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles +system.cpu0.Branches 111287587 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 400497126 69.30% 69.30% # Class of executed instruction -system.cpu0.op_class::IntMult 1218559 0.21% 69.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 59561 0.01% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 73140 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::MemRead 91428761 15.82% 85.36% # Class of executed instruction -system.cpu0.op_class::MemWrite 84629307 14.64% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction +system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction +system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction +system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 577906497 # Class of executed instruction +system.cpu0.op_class::total 585300003 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13193 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 6189405 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.263112 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169698310 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6189917 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.415280 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 6272759 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 172015744 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6273271 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.420423 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.263112 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988795 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988795 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 358274198 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 358274198 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 84971856 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 84971856 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79868150 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 79868150 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214674 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 214674 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 260533 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 260533 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2068908 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2068908 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2028668 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2028668 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164840006 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164840006 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165054680 # number of overall hits -system.cpu0.dcache.overall_hits::total 165054680 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3260277 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3260277 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1458399 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1458399 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 767112 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 767112 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 819206 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 819206 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 116959 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 116959 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156094 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 156094 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4718676 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4718676 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5485788 # number of overall misses -system.cpu0.dcache.overall_misses::total 5485788 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88232133 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 88232133 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81326549 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81326549 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 981786 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 981786 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079739 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079739 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2185867 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2185867 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2184762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2184762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169558682 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 169558682 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170540468 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 170540468 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036951 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036951 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017933 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017933 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781343 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781343 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.758707 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.758707 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053507 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053507 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071447 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071447 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027829 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027829 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032167 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032167 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 363162158 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 363162158 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86214905 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86214905 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80919887 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80919887 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215655 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 215655 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 262024 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 262024 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036774 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2036774 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 167134792 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 167134792 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 167350447 # number of overall hits +system.cpu0.dcache.overall_hits::total 167350447 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3309378 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3309378 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1475526 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1475526 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772138 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 772138 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 831696 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 831696 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158369 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 158369 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4784904 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4784904 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5557042 # number of overall misses +system.cpu0.dcache.overall_misses::total 5557042 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524283 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89524283 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395413 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82395413 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093720 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093720 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 171919696 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 171919696 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 172907489 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 172907489 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017908 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017908 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072145 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072145 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027832 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027832 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,50 +391,50 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4407988 # number of writebacks -system.cpu0.dcache.writebacks::total 4407988 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 4469723 # number of writebacks +system.cpu0.dcache.writebacks::total 4469723 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5467768 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 485959047 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5468280 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.868721 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 5539081 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 988322949 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 988322949 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 485959047 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 485959047 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 485959047 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 485959047 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 485959047 # number of overall hits -system.cpu0.icache.overall_hits::total 485959047 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5468285 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5468285 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5468285 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5468285 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5468285 # number of overall misses -system.cpu0.icache.overall_misses::total 5468285 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 491427332 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 491427332 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 491427332 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 491427332 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 491427332 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 491427332 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011127 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011127 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011127 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011127 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011127 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011127 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits +system.cpu0.icache.overall_hits::total 492212891 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses +system.cpu0.icache.overall_misses::total 5539598 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,132 +450,132 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2648971 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2665005 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.283598 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2710840 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16208.843540 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 11548798 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2726836 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.235237 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5428.449185 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.127041 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.911966 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4608.843039 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 6080.573004 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.331326 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003060 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003168 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.281301 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.371129 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989984 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15969 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 5735.641953 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.550576 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 55.046098 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4528.763909 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5835.841004 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.350076 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003268 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003360 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276414 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.356191 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989309 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15944 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 50 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1130 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4626 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5485 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4547 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.974670 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 274915962 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 274915962 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 266204 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 139155 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4917807 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2910870 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 8234036 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4407988 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4407988 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 219663 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 219663 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3562 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 3562 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 630387 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 630387 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 266204 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 139155 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4917807 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3541257 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8864423 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 266204 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 139155 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4917807 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3541257 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8864423 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10959 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8288 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 550478 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1233478 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1803203 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 599179 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 599179 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 125865 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 125865 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156094 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 156094 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 698949 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 698949 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10959 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8288 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 550478 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1932427 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2502152 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10959 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8288 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 550478 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1932427 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2502152 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 277163 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 147443 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5468285 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4144348 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 10037239 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4407988 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4407988 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 818842 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 818842 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 129427 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 129427 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156094 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 156094 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1329336 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1329336 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 277163 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 147443 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5468285 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5473684 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11366575 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 277163 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 147443 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5468285 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5473684 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11366575 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056212 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.100667 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.297629 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.179651 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.731739 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.731739 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.972479 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.972479 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1162 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4591 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5299 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4659 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973145 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 278654950 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 278654950 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 269350 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 141753 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4971397 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2944075 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 8326575 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 4469723 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 4469723 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 222737 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 222737 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3521 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 3521 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634814 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 634814 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 269350 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 141753 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4971397 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3578889 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8961389 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 269350 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 141753 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4971397 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3578889 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8961389 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11316 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8593 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 568201 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 1257257 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1845367 # number of ReadReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608598 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 608598 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128143 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 128143 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158369 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 158369 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709409 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 709409 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11316 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8593 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 568201 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1966666 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2554776 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11316 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8593 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 568201 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1966666 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2554776 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 280666 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 150346 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539598 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201332 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 10171942 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4469723 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4469723 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831335 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831335 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131664 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 131664 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158369 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 158369 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344223 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1344223 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 280666 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 150346 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5545555 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11516165 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 280666 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 150346 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5545555 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11516165 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057155 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102571 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299252 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.181417 # miss rate for ReadReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.732073 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.732073 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973258 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973258 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525788 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.525788 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056212 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.100667 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.353040 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.220132 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056212 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.100667 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.353040 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.220132 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527747 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527747 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057155 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102571 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354638 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.221843 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057155 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102571 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354638 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.221843 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,47 +584,45 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1542533 # number of writebacks -system.cpu0.l2cache.writebacks::total 1542533 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1573452 # number of writebacks +system.cpu0.l2cache.writebacks::total 1573452 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 10228504 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10228504 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4407988 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 818842 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 818842 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 129427 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156094 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 285521 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1329336 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1329336 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11022820 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17694214 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 359792 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 720614 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 29797440 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 350142740 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 685026670 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2882456 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1039491034 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 3383860 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20196192 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.158528 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.365236 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 10363949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10363949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32448 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32448 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4469723 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 131664 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158369 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 290033 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1344223 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1344223 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165446 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17933523 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 30193699 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694376897 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1053462589 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 3346385 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 20385280 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.155096 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.361996 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 16994523 84.15% 84.15% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 3201669 15.85% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 17223609 84.49% 84.49% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 3161671 15.51% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 20385280 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -654,45 +652,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 144852 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 144852 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 144852 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 144852 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 144041 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 112422 89.02% 89.02% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 13865 10.98% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 126287 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144852 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126287 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 271139 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91720002 # DTB read hits -system.cpu1.dtb.read_misses 112244 # DTB read misses -system.cpu1.dtb.write_hits 82499013 # DTB write hits -system.cpu1.dtb.write_misses 32608 # DTB write misses +system.cpu1.dtb.read_hits 90153061 # DTB read hits +system.cpu1.dtb.read_misses 111753 # DTB read misses +system.cpu1.dtb.write_hits 81132787 # DTB write hits +system.cpu1.dtb.write_misses 32288 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 45118 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4542 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11534 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91832246 # DTB read accesses -system.cpu1.dtb.write_accesses 82531621 # DTB write accesses +system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90264814 # DTB read accesses +system.cpu1.dtb.write_accesses 81165075 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 174219015 # DTB hits -system.cpu1.dtb.misses 144852 # DTB misses -system.cpu1.dtb.accesses 174363867 # DTB accesses +system.cpu1.dtb.hits 171285848 # DTB hits +system.cpu1.dtb.misses 144041 # DTB misses +system.cpu1.dtb.accesses 171429889 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -722,186 +720,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 61939 # Table walker walks requested -system.cpu1.itb.walker.walksLong 61939 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 61939 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 61939 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 60885 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54929 99.06% 99.06% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 521 0.94% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55450 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61939 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55450 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55450 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 117389 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 485906850 # ITB inst hits -system.cpu1.itb.inst_misses 61939 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 478248118 # ITB inst hits +system.cpu1.itb.inst_misses 60885 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31863 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 485968789 # ITB inst accesses -system.cpu1.itb.hits 485906850 # DTB hits -system.cpu1.itb.misses 61939 # DTB misses -system.cpu1.itb.accesses 485968789 # DTB accesses -system.cpu1.numCycles 94354166192 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses +system.cpu1.itb.hits 478248118 # DTB hits +system.cpu1.itb.misses 60885 # DTB misses +system.cpu1.itb.accesses 478309003 # DTB accesses +system.cpu1.numCycles 94433634550 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 485652916 # Number of instructions committed -system.cpu1.committedOps 571511718 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 524558211 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 375128 # Number of float alu accesses -system.cpu1.num_func_calls 28666071 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 74347572 # number of instructions that are conditional controls -system.cpu1.num_int_insts 524558211 # number of integer instructions -system.cpu1.num_fp_insts 375128 # number of float instructions -system.cpu1.num_int_register_reads 774388464 # number of times the integer registers were read -system.cpu1.num_int_register_writes 417530639 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 610571 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 303256 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 128278137 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 127991607 # number of times the CC registers were written -system.cpu1.num_mem_refs 174340371 # number of memory refs -system.cpu1.num_load_insts 91819242 # Number of load instructions -system.cpu1.num_store_insts 82521129 # Number of store instructions -system.cpu1.num_idle_cycles 93782340058.888657 # Number of idle cycles -system.cpu1.num_busy_cycles 571826133.111340 # Number of busy cycles -system.cpu1.not_idle_fraction 0.006060 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.993940 # Percentage of idle cycles -system.cpu1.Branches 108195111 # Number of branches fetched +system.cpu1.committedInsts 477990846 # Number of instructions committed +system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses +system.cpu1.num_func_calls 28237407 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls +system.cpu1.num_int_insts 516282159 # number of integer instructions +system.cpu1.num_fp_insts 374678 # number of float instructions +system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read +system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written +system.cpu1.num_mem_refs 171406825 # number of memory refs +system.cpu1.num_load_insts 90251973 # Number of load instructions +system.cpu1.num_store_insts 81154852 # Number of store instructions +system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles +system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles +system.cpu1.Branches 106497601 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 396230726 69.29% 69.29% # Class of executed instruction -system.cpu1.op_class::IntMult 1151823 0.20% 69.49% # Class of executed instruction -system.cpu1.op_class::IntDiv 61886 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 36426 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::MemRead 91819242 16.06% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 82521129 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction +system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction +system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 571821232 # Class of executed instruction +system.cpu1.op_class::total 562879339 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6178 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 6025220 # number of replacements -system.cpu1.dcache.tags.tagsinuse 443.938244 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 168203685 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 6025731 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.914237 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 5945049 # number of replacements +system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 443.938244 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867067 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.867067 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 354758936 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 354758936 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 85201700 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 85201700 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 78314445 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 78314445 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188411 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 188411 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 65692 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 65692 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2073864 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2073864 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2064069 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2064069 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 163516145 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 163516145 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 163704556 # number of overall hits -system.cpu1.dcache.overall_hits::total 163704556 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3403274 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3403274 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1467363 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1467363 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 796168 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 796168 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 438523 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 438523 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 149383 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 149383 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 157982 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 157982 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4870637 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4870637 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5666805 # number of overall misses -system.cpu1.dcache.overall_misses::total 5666805 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 88604974 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 88604974 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 79781808 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 79781808 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 984579 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 984579 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 504215 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 504215 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2223247 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2223247 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2222051 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2222051 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 168386782 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 168386782 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 169371361 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 169371361 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038410 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038410 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018392 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018392 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808638 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808638 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.869714 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.869714 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067191 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067191 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071097 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071097 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028925 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.028925 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033458 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033458 # miss rate for overall accesses +system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 76990336 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 76990336 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63447 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 63447 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048907 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2048907 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 160687900 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 160687900 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 160875754 # number of overall hits +system.cpu1.dcache.overall_hits::total 160875754 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1453140 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1453140 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427052 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 427052 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158842 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 158842 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4811362 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4811362 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5603713 # number of overall misses +system.cpu1.dcache.overall_misses::total 5603713 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 490499 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 490499 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018525 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870648 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870648 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033660 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -910,49 +909,49 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 4091318 # number of writebacks -system.cpu1.dcache.writebacks::total 4091318 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 4030826 # number of writebacks +system.cpu1.dcache.writebacks::total 4030826 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4818195 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.412963 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 481143593 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4818707 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.849107 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 4741297 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.412963 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969557 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969557 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 976743307 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 976743307 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 481143593 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 481143593 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 481143593 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 481143593 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 481143593 # number of overall hits -system.cpu1.icache.overall_hits::total 481143593 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4818707 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4818707 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4818707 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4818707 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4818707 # number of overall misses -system.cpu1.icache.overall_misses::total 4818707 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 485962300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 485962300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 485962300 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 485962300 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 485962300 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 485962300 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits +system.cpu1.icache.overall_hits::total 473560604 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses +system.cpu1.icache.overall_misses::total 4741809 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -968,133 +967,132 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2333825 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2349876 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.683889 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9726491548000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5253.379361 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.604678 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.064726 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2656.476360 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5431.499219 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.320641 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004582 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.162138 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.331512 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.823000 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 103 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15948 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1580 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5821 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4453 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4016 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006287 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973389 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 257480243 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 257480243 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 323221 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141798 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4279723 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 3095607 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7840349 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 4091318 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 4091318 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 167179 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 167179 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3859 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 3859 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 621347 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 621347 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 323221 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1583 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5963 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4534 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3771 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 254019378 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 254019378 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 325118 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141158 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4217165 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 3057891 # 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number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 4030826 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137456 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 137456 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158842 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 158842 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337607 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150938 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10843637 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337607 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150938 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10843637 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064795 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110642 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288431 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.187496 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.621957 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.621957 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971882 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971882 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532845 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532845 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064657 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.111852 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345479 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.229701 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064657 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.111852 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345479 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.229701 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533250 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533250 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064795 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110642 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345823 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.229454 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064795 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110642 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345823 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.229454 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1103,53 +1101,51 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1212706 # number of writebacks -system.cpu1.l2cache.writebacks::total 1212706 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 1183487 # number of writebacks +system.cpu1.l2cache.writebacks::total 1183487 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 9779239 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9779239 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6380 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6380 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4091318 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 438296 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 438296 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 137523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157982 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 295505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1330067 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1330067 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9637674 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16942172 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370292 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 840154 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27790292 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 308397768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 653382681 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1481168 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3360616 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 966622233 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 3659793 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 19426876 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.180108 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.384277 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4030826 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 137456 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158842 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 296298 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16729164 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27412486 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644579516 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 952853588 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 3730448 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 19274314 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.184989 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.388288 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15927941 81.99% 81.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 3498935 18.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 15708784 81.50% 81.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 3565530 18.50% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19426876 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40346 # Transaction distribution -system.iobus.trans_dist::ReadResp 40346 # Transaction distribution -system.iobus.trans_dist::WriteReq 136741 # Transaction distribution -system.iobus.trans_dist::WriteResp 30013 # Transaction distribution +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 19274314 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40295 # Transaction distribution +system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.iobus.trans_dist::WriteReq 136634 # Transaction distribution +system.iobus.trans_dist::WriteResp 29906 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1164,13 +1160,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122884 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354174 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47970 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1185,54 +1181,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155991 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496933 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115586 # number of replacements -system.iocache.tags.tagsinuse 11.286927 # Cycle average of tags in use +system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115585 # number of replacements +system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115602 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.855232 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.431695 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240952 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.464481 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705433 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040802 # Number of tag accesses -system.iocache.tags.data_accesses 1040802 # Number of data accesses +system.iocache.tags.tag_accesses 1040793 # Number of tag accesses +system.iocache.tags.data_accesses 1040793 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses -system.iocache.demand_misses::total 8917 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses +system.iocache.demand_misses::total 8916 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8877 # number of overall misses -system.iocache.overall_misses::total 8917 # number of overall misses +system.iocache.overall_misses::realview.ide 8876 # number of overall misses +system.iocache.overall_misses::total 8916 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1257,205 +1253,205 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1764050 # number of replacements -system.l2c.tags.tagsinuse 62893.103184 # Cycle average of tags in use -system.l2c.tags.total_refs 3693923 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1823047 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.026236 # Average number of references to valid blocks. +system.l2c.tags.replacements 1759966 # number of replacements +system.l2c.tags.tagsinuse 62842.185631 # Cycle average of tags in use +system.l2c.tags.total_refs 3707512 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1818705 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.038545 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35252.715261 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 32.297168 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 36.889266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3199.431904 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6870.253722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 308.072507 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 447.332489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2890.642136 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 13855.468731 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.537914 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000493 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000563 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.048819 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.104832 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004701 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006826 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.044108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.211418 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.959673 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 209 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 58788 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 35219.340736 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 46.907098 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 57.886687 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3338.956610 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6965.181537 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.496433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 430.211698 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2959.236338 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13514.968494 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.537404 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000716 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000883 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050948 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.106280 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006565 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.045154 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.206222 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.958896 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 231 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 58508 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3602 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 49009 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003189 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.897034 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 66315846 # Number of tag accesses -system.l2c.tags.data_accesses 66315846 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5920 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4325 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 492739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 723130 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3764 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 496903 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 707011 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2439522 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2755239 # number of Writeback hits -system.l2c.Writeback_hits::total 2755239 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 115462 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 102925 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 218387 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 13978 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 10743 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24721 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1494 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1282 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2776 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 196550 # 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number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 608055 # number of demand (read+write) misses +system.l2c.demand_misses::total 1280735 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2407 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2011 # number of overall misses +system.l2c.overall_misses::cpu0.inst 58419 # number of overall misses +system.l2c.overall_misses::cpu0.data 561677 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3483 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3456 # number of overall misses +system.l2c.overall_misses::cpu1.inst 41227 # number of overall misses +system.l2c.overall_misses::cpu1.data 608055 # number of overall misses +system.l2c.overall_misses::total 1280735 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8741 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6688 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 568201 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 928520 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 9052 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7066 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 524644 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 881763 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2934675 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2756939 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2756939 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 600751 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 258823 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 859574 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 71845 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 64785 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 136630 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9288 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8727 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18015 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 580231 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 589564 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1169795 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8741 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6688 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 568201 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1508751 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9052 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7066 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 524644 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1471327 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4104470 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8741 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6688 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 568201 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1508751 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9052 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7066 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 524644 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1471327 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4104470 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.300688 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.102814 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.198309 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.489103 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.078581 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.215189 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.165225 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.797690 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.621452 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.744623 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807544 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831257 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.831395 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.850579 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.840688 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.650677 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.709523 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.680335 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.300688 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.102814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.372279 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.489103 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.078581 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.413270 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.312034 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.300688 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.102814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.372279 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.489103 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.078581 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.413270 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.312034 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1464,49 +1460,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1467678 # number of writebacks -system.l2c.writebacks::total 1467678 # number of writebacks +system.l2c.writebacks::writebacks 1464604 # number of writebacks +system.l2c.writebacks::total 1464604 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 577534 # Transaction distribution -system.membus.trans_dist::ReadResp 577534 # Transaction distribution -system.membus.trans_dist::WriteReq 38903 # Transaction distribution -system.membus.trans_dist::WriteResp 38903 # Transaction distribution -system.membus.trans_dist::Writeback 1574372 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 739425 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 739425 # Transaction distribution -system.membus.trans_dist::UpgradeReq 325897 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 311300 # Transaction distribution -system.membus.trans_dist::UpgradeResp 149445 # Transaction distribution -system.membus.trans_dist::ReadExReq 961374 # Transaction distribution -system.membus.trans_dist::ReadExResp 780321 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122884 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 575939 # Transaction distribution +system.membus.trans_dist::ReadResp 575939 # Transaction distribution +system.membus.trans_dist::WriteReq 38831 # Transaction distribution +system.membus.trans_dist::WriteResp 38831 # Transaction distribution +system.membus.trans_dist::Writeback 1571298 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 742240 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 742240 # Transaction distribution +system.membus.trans_dist::UpgradeReq 327418 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 314341 # Transaction distribution +system.membus.trans_dist::UpgradeResp 148936 # Transaction distribution +system.membus.trans_dist::ReadExReq 965776 # Transaction distribution +system.membus.trans_dist::ReadExResp 778482 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27406 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6326067 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6476449 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337984 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337984 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6814433 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155991 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6332069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6482289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6820271 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54812 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215692580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 215903587 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14229504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 230133091 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215456868 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 215667865 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 229897305 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4407750 # Request fanout histogram +system.membus.snoop_fanout::samples 4414869 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4407750 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4414869 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4407750 # Request fanout histogram +system.membus.snoop_fanout::total 4414869 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1549,35 +1545,35 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 3699896 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3699896 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38903 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38903 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2755239 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 855709 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 855709 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 328922 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 314076 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 642998 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1352863 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1352863 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8525495 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7410482 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15935977 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295216066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 254408545 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 549624611 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 117315 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9340198 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012381 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110581 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 3713925 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3713925 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38831 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38831 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2756939 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 859574 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 859574 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 330257 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 317211 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 647468 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1357089 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1357089 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8689428 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7301285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15990713 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301218837 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249930820 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 551149657 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 117306 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9368496 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012344 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110415 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9224553 98.76% 98.76% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115645 1.24% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9252852 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115644 1.23% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9340198 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 9368496 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 70b8700c6..b381100ef 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111151 # Number of seconds simulated -sim_ticks 51111150553500 # Number of ticks simulated -final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111153 # Number of seconds simulated +sim_ticks 51111152682000 # Number of ticks simulated +final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1336104 # Simulator instruction rate (inst/s) -host_op_rate 1570142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69344550867 # Simulator tick rate (ticks/s) -host_mem_usage 712616 # Number of bytes of host memory used -host_seconds 737.06 # Real time elapsed on the host -sim_insts 984789519 # Number of instructions simulated -sim_ops 1157289961 # Number of ops (including micro ops) simulated +host_inst_rate 1276359 # Simulator instruction rate (inst/s) +host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66258489115 # Simulator tick rate (ticks/s) +host_mem_usage 712024 # Number of bytes of host memory used +host_seconds 771.39 # Real time elapsed on the host +sim_insts 984570519 # Number of instructions simulated +sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 411136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 373504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5556020 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 75320200 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory -system.physmem.bytes_read::total 82098556 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5556020 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5556020 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103277568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory +system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298148 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 127220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1176891 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1323210 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613712 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616285 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 8044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 108705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1473655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1606275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020647 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1474058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3627324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -103,45 +103,45 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 265618 # Table walker walks requested -system.cpu.dtb.walker.walksLong 265618 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 265618 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 265618 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 265715 # Table walker walks requested +system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 204344 89.54% 89.54% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 23878 10.46% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 228222 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265618 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228222 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 493840 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 184057973 # DTB read hits -system.cpu.dtb.read_misses 194269 # DTB read misses -system.cpu.dtb.write_hits 168276300 # DTB write hits -system.cpu.dtb.write_misses 71349 # DTB write misses +system.cpu.dtb.read_hits 184014035 # DTB read hits +system.cpu.dtb.read_misses 194198 # DTB read misses +system.cpu.dtb.write_hits 168232768 # DTB write hits +system.cpu.dtb.write_misses 71517 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 81439 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9105 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184252242 # DTB read accesses -system.cpu.dtb.write_accesses 168347649 # DTB write accesses +system.cpu.dtb.read_accesses 184208233 # DTB read accesses +system.cpu.dtb.write_accesses 168304285 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 352334273 # DTB hits -system.cpu.dtb.misses 265618 # DTB misses -system.cpu.dtb.accesses 352599891 # DTB accesses +system.cpu.dtb.hits 352246803 # DTB hits +system.cpu.dtb.misses 265715 # DTB misses +system.cpu.dtb.accesses 352512518 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -171,26 +171,26 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 126829 # Table walker walks requested -system.cpu.itb.walker.walksLong 126829 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126829 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126829 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 126837 # Table walker walks requested +system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113566 99.02% 99.02% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1125 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114691 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126829 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114691 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114691 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241520 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 985266544 # ITB inst hits -system.cpu.itb.inst_misses 126829 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 985047321 # ITB inst hits +system.cpu.itb.inst_misses 126837 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -199,46 +199,46 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57079 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 985393373 # ITB inst accesses -system.cpu.itb.hits 985266544 # DTB hits -system.cpu.itb.misses 126829 # DTB misses -system.cpu.itb.accesses 985393373 # DTB accesses -system.cpu.numCycles 102222317883 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 985174158 # ITB inst accesses +system.cpu.itb.hits 985047321 # DTB hits +system.cpu.itb.misses 126837 # DTB misses +system.cpu.itb.accesses 985174158 # DTB accesses +system.cpu.numCycles 102222322140 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 984789519 # Number of instructions committed -system.cpu.committedOps 1157289961 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1060698532 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 880773 # Number of float alu accesses -system.cpu.num_func_calls 57075493 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151966445 # number of instructions that are conditional controls -system.cpu.num_int_insts 1060698532 # number of integer instructions -system.cpu.num_fp_insts 880773 # number of float instructions -system.cpu.num_int_register_reads 1564314393 # number of times the integer registers were read -system.cpu.num_int_register_writes 842633326 # number of times the integer registers were written +system.cpu.committedInsts 984570519 # Number of instructions committed +system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses +system.cpu.num_func_calls 57056367 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls +system.cpu.num_int_insts 1060455466 # number of integer instructions +system.cpu.num_fp_insts 880805 # number of float instructions +system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read +system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read -system.cpu.num_fp_register_writes 747792 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264443211 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263865511 # number of times the CC registers were written -system.cpu.num_mem_refs 352552781 # number of memory refs -system.cpu.num_load_insts 184224242 # Number of load instructions -system.cpu.num_store_insts 168328539 # Number of store instructions -system.cpu.num_idle_cycles 101064381138.333679 # Number of idle cycles -system.cpu.num_busy_cycles 1157936744.666323 # Number of busy cycles -system.cpu.not_idle_fraction 0.011328 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.988672 # Percentage of idle cycles -system.cpu.Branches 220135160 # Number of branches fetched +system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written +system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read +system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written +system.cpu.num_mem_refs 352465606 # number of memory refs +system.cpu.num_load_insts 184180431 # Number of load instructions +system.cpu.num_store_insts 168285175 # Number of store instructions +system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles +system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles +system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.988675 # Percentage of idle cycles +system.cpu.Branches 220088562 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 802806903 69.33% 69.33% # Class of executed instruction -system.cpu.op_class::IntMult 2355402 0.20% 69.53% # Class of executed instruction -system.cpu.op_class::IntDiv 101851 0.01% 69.54% # Class of executed instruction +system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction +system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction +system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction @@ -265,93 +265,93 @@ system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::MemRead 184224242 15.91% 85.46% # Class of executed instruction -system.cpu.op_class::MemWrite 168328539 14.54% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction +system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1157924802 # Class of executed instruction +system.cpu.op_class::total 1157666593 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 11615783 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 340859576 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11616295 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.343227 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 11612141 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999718 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1421519854 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1421519854 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 171606610 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171606610 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159566138 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159566138 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424146 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424146 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337798 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 337798 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310377 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4310377 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4563246 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4563246 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 331172748 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 331172748 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 331596894 # number of overall hits -system.cpu.dcache.overall_hits::total 331596894 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6013361 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6013361 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2569466 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2569466 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1584813 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1584813 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245259 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1245259 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 254671 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 254671 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits +system.cpu.dcache.overall_hits::total 331514149 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8582827 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8582827 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10167640 # number of overall misses -system.cpu.dcache.overall_misses::total 10167640 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177619971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177619971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 162135604 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 162135604 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008959 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2008959 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583057 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1583057 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4565048 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4565048 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4563247 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4563247 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 339755575 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 339755575 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 341764534 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 341764534 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033855 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015848 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015848 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788873 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788873 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786617 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786617 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses +system.cpu.dcache.overall_misses::total 10164734 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.029750 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.029750 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -360,49 +360,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8923646 # number of writebacks -system.cpu.dcache.writebacks::total 8923646 # number of writebacks +system.cpu.dcache.writebacks::writebacks 8921315 # number of writebacks +system.cpu.dcache.writebacks::total 8921315 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 14287218 # number of replacements +system.cpu.icache.tags.replacements 14295641 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 971093500 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14287730 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.966955 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 999668970 # Number of tag accesses -system.cpu.icache.tags.data_accesses 999668970 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 971093500 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 971093500 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 971093500 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 971093500 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 971093500 # number of overall hits -system.cpu.icache.overall_hits::total 971093500 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14287735 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14287735 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14287735 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14287735 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14287735 # number of overall misses -system.cpu.icache.overall_misses::total 14287735 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 985381235 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 985381235 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 985381235 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 985381235 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 985381235 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 985381235 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014500 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014500 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014500 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014500 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014500 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014500 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses +system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits +system.cpu.icache.overall_hits::total 970865862 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14296158 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14296158 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14296158 # number of overall misses +system.cpu.icache.overall_misses::total 14296158 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 985162020 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,130 +412,129 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1726949 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65261.456081 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29978708 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1789688 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 16.750801 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1722692 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65341.862502 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 29983424 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1785989 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 16.788135 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37844.065183 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 274.121350 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 368.710071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6273.950851 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20500.608627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.577455 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004183 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005626 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095733 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.312814 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995811 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 248 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62491 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 597 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2750 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4968 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54019 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953537 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 290358067 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 290358067 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 511193 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 258912 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 14203603 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7508372 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 22482080 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 8923646 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 8923646 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 697316 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 697316 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 11232 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 11232 # 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number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10371051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25441151 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 517617 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 264748 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14287735 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10371051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25441151 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012411 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022044 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005888 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043866 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019221 # miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442459 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.331031 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.331031 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012411 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022044 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005888 # 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miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005892 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.112900 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049809 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005892 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,53 +543,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # 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Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 51260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 51261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2518206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2518206 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28661720 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32393426 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 63356998 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 914587540 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314747172 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6174720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2238542120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 116335 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 36145396 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003196 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.056442 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 116338 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 36029878 99.68% 99.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 36145396 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40296 # Transaction distribution -system.iobus.trans_dist::ReadResp 40296 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 29957 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40246 # Transaction distribution +system.iobus.trans_dist::ReadResp 40246 # Transaction distribution +system.iobus.trans_dist::WriteReq 136515 # Transaction distribution +system.iobus.trans_dist::WriteResp 29851 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -605,13 +602,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -626,54 +623,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115460 # number of replacements +system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115463 # number of replacements system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039659 # Number of tag accesses -system.iocache.tags.data_accesses 1039659 # Number of data accesses +system.iocache.tags.tag_accesses 1039686 # Number of tag accesses +system.iocache.tags.data_accesses 1039686 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses -system.iocache.demand_misses::total 8854 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses +system.iocache.demand_misses::total 8857 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8814 # number of overall misses -system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.overall_misses::realview.ide 8817 # number of overall misses +system.iocache.overall_misses::total 8857 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -698,46 +695,46 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 526448 # Transaction distribution -system.membus.trans_dist::ReadResp 526448 # Transaction distribution -system.membus.trans_dist::WriteReq 33712 # Transaction distribution -system.membus.trans_dist::WriteResp 33712 # Transaction distribution -system.membus.trans_dist::Writeback 1613712 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 654602 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 654602 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40596 # Transaction distribution +system.membus.trans_dist::ReadReq 526062 # Transaction distribution +system.membus.trans_dist::ReadResp 526062 # Transaction distribution +system.membus.trans_dist::WriteReq 33606 # Transaction distribution +system.membus.trans_dist::WriteResp 33606 # Transaction distribution +system.membus.trans_dist::Writeback 1610046 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40597 # Transaction distribution -system.membus.trans_dist::ReadExReq 833043 # Transaction distribution -system.membus.trans_dist::ReadExResp 833043 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution +system.membus.trans_dist::ReadExReq 825948 # Transaction distribution +system.membus.trans_dist::ReadExResp 825948 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5323339 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5452849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5790516 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213244448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213413816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 227631160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3591670 # Request fanout histogram +system.membus.snoop_fanout::samples 3583537 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3591670 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3591670 # Request fanout histogram +system.membus.snoop_fanout::total 3583537 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index cd0cb8f17..fb0fbc4a7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.410782 # Number of seconds simulated -sim_ticks 47410781652000 # Number of ticks simulated -final_tick 47410781652000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.367818 # Number of seconds simulated +sim_ticks 47367817574000 # Number of ticks simulated +final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 787433 # Simulator instruction rate (inst/s) -host_op_rate 926573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41969003911 # Simulator tick rate (ticks/s) -host_mem_usage 699232 # Number of bytes of host memory used -host_seconds 1129.66 # Real time elapsed on the host -sim_insts 889532971 # Number of instructions simulated -sim_ops 1046714541 # Number of ops (including micro ops) simulated +host_inst_rate 678056 # Simulator instruction rate (inst/s) +host_op_rate 798173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38043399524 # Simulator tick rate (ticks/s) +host_mem_usage 751768 # Number of bytes of host memory used +host_seconds 1245.10 # Real time elapsed on the host +sim_insts 844246943 # Number of instructions simulated +sim_ops 993804803 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 154432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 156800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3551860 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14084888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 14587840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 66560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 59904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2809592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 8562400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 11943680 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory -system.physmem.bytes_read::total 56406948 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3551860 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2809592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6361452 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74353408 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 36928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 40576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2794548 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9993048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9568064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 72256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 86016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2509048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8105888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 7582272 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437184 # Number of bytes read from this memory +system.physmem.bytes_read::total 41225828 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2794548 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2509048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5303596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 61292480 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74374224 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2413 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 95905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 220098 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 227935 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 43988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 133802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 186620 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory -system.physmem.num_reads::total 921890 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1161772 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 61313296 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 84072 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 156163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 149501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1344 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39292 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 126669 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 118473 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6831 # Number of read requests responded to by this memory +system.physmem.num_reads::total 684685 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 957695 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1164375 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 74917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 297082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 307690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 180600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 251919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1189749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 74917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 134177 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1568281 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 960298 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 58997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 210967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 201995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 171126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 160072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 870334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 58997 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 111966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1293969 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1568720 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1568281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 74917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 297521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 307690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 180600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 251919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2758469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 921890 # Number of read requests accepted -system.physmem.writeReqs 1829645 # Number of write requests accepted -system.physmem.readBursts 921890 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1829645 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 58978368 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue -system.physmem.bytesWritten 116660480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56406948 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 116951504 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6803 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 114603 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 54393 # Per bank write bursts -system.physmem.perBankRdBursts::1 56084 # Per bank write bursts -system.physmem.perBankRdBursts::2 54659 # Per bank write bursts -system.physmem.perBankRdBursts::3 58883 # Per bank write bursts -system.physmem.perBankRdBursts::4 54974 # Per bank write bursts -system.physmem.perBankRdBursts::5 58047 # Per bank write bursts -system.physmem.perBankRdBursts::6 51881 # Per bank write bursts -system.physmem.perBankRdBursts::7 58759 # Per bank write bursts -system.physmem.perBankRdBursts::8 52533 # Per bank write bursts -system.physmem.perBankRdBursts::9 95950 # Per bank write bursts -system.physmem.perBankRdBursts::10 53815 # Per bank write bursts -system.physmem.perBankRdBursts::11 56993 # Per bank write bursts -system.physmem.perBankRdBursts::12 52328 # Per bank write bursts -system.physmem.perBankRdBursts::13 55917 # Per bank write bursts -system.physmem.perBankRdBursts::14 52932 # Per bank write bursts -system.physmem.perBankRdBursts::15 53389 # Per bank write bursts -system.physmem.perBankWrBursts::0 113787 # Per bank write bursts -system.physmem.perBankWrBursts::1 117144 # Per bank write bursts -system.physmem.perBankWrBursts::2 115098 # Per bank write bursts -system.physmem.perBankWrBursts::3 118536 # Per bank write bursts -system.physmem.perBankWrBursts::4 116769 # Per bank write bursts -system.physmem.perBankWrBursts::5 120895 # Per bank write bursts -system.physmem.perBankWrBursts::6 109520 # Per bank write bursts -system.physmem.perBankWrBursts::7 112924 # Per bank write bursts -system.physmem.perBankWrBursts::8 111914 # Per bank write bursts -system.physmem.perBankWrBursts::9 117541 # Per bank write bursts -system.physmem.perBankWrBursts::10 111832 # Per bank write bursts -system.physmem.perBankWrBursts::11 116807 # Per bank write bursts -system.physmem.perBankWrBursts::12 108182 # Per bank write bursts -system.physmem.perBankWrBursts::13 109739 # Per bank write bursts -system.physmem.perBankWrBursts::14 110202 # Per bank write bursts -system.physmem.perBankWrBursts::15 111930 # Per bank write bursts +system.physmem.bw_write::total 1294408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1293969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 58997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 211406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 201995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 171127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 160072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2164742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 684685 # Number of read requests accepted +system.physmem.writeReqs 1596629 # Number of write requests accepted +system.physmem.readBursts 684685 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1596629 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 43802304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17536 # Total number of bytes read from write queue +system.physmem.bytesWritten 99044160 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 41225828 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 274 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49035 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 111704 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 42136 # Per bank write bursts +system.physmem.perBankRdBursts::1 44080 # Per bank write bursts +system.physmem.perBankRdBursts::2 34958 # Per bank write bursts +system.physmem.perBankRdBursts::3 41288 # Per bank write bursts +system.physmem.perBankRdBursts::4 39326 # Per bank write bursts +system.physmem.perBankRdBursts::5 49165 # Per bank write bursts +system.physmem.perBankRdBursts::6 40428 # Per bank write bursts +system.physmem.perBankRdBursts::7 47118 # Per bank write bursts +system.physmem.perBankRdBursts::8 36254 # Per bank write bursts +system.physmem.perBankRdBursts::9 81044 # Per bank write bursts +system.physmem.perBankRdBursts::10 36070 # Per bank write bursts +system.physmem.perBankRdBursts::11 40557 # Per bank write bursts +system.physmem.perBankRdBursts::12 34453 # Per bank write bursts +system.physmem.perBankRdBursts::13 38158 # Per bank write bursts +system.physmem.perBankRdBursts::14 37145 # Per bank write bursts +system.physmem.perBankRdBursts::15 42231 # Per bank write bursts +system.physmem.perBankWrBursts::0 97165 # Per bank write bursts +system.physmem.perBankWrBursts::1 99476 # Per bank write bursts +system.physmem.perBankWrBursts::2 95543 # Per bank write bursts +system.physmem.perBankWrBursts::3 98326 # Per bank write bursts +system.physmem.perBankWrBursts::4 92692 # Per bank write bursts +system.physmem.perBankWrBursts::5 102230 # Per bank write bursts +system.physmem.perBankWrBursts::6 96747 # Per bank write bursts +system.physmem.perBankWrBursts::7 98806 # Per bank write bursts +system.physmem.perBankWrBursts::8 93672 # Per bank write bursts +system.physmem.perBankWrBursts::9 100275 # Per bank write bursts +system.physmem.perBankWrBursts::10 92352 # Per bank write bursts +system.physmem.perBankWrBursts::11 96579 # Per bank write bursts +system.physmem.perBankWrBursts::12 94667 # Per bank write bursts +system.physmem.perBankWrBursts::13 97213 # Per bank write bursts +system.physmem.perBankWrBursts::14 92658 # Per bank write bursts +system.physmem.perBankWrBursts::15 99164 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 47410778671000 # Total gap between requests +system.physmem.numWrRetry 352 # Number of times write queue was full causing retry +system.physmem.totGap 47367814519500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 878653 # Read request sizes (log2) +system.physmem.readPktSize::6 641448 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1827042 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 652905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 75815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 40303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 22543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 19321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1594026 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 510577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 16379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 14128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 9819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,181 +188,170 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 54841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 74169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 96317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 106970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 112981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 116642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 107891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 106380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 108843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 109894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 105867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 106408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 98436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 96529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 94372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 91211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1000117 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.617981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 106.594305 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 248.236984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 645970 64.59% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 191036 19.10% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 45051 4.50% 88.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21747 2.17% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15328 1.53% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10644 1.06% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8285 0.83% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7295 0.73% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 54761 5.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1000117 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 87721 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.505238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 108.849756 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 87718 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 50983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 63815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 77905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 83850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 82535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 80562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 80737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 81986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 81840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 82529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 87953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 82789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 95240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 86941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 82400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 79288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1324 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 813055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12096 1.49% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6222 0.77% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 87721 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 87721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.779745 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.605058 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.125024 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 56948 64.92% 64.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 16031 18.27% 83.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 6972 7.95% 91.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 3738 4.26% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1084 1.24% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 357 0.41% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 239 0.27% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 271 0.31% 97.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 649 0.74% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 108 0.12% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 85 0.10% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 76 0.09% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 135 0.15% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 76 0.09% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 51 0.06% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 73 0.08% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 134 0.15% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 41 0.05% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 31 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 49 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 179 0.20% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 16 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 31 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 43 0.05% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 12 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 20 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 30 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 97 0.11% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 18 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 14 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 10 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 11 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 14 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 12 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 87721 # Writes before turning the bus around for reads -system.physmem.totQLat 32913462781 # Total ticks spent queuing -system.physmem.totMemAccLat 50192281531 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4607685000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35715.83 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 73772 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 73772 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.369218 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 71961 97.55% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 712 0.97% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 29 0.04% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 36 0.05% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 132 0.18% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 174 0.24% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 342 0.46% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 135 0.18% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 19 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 64 0.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 33 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 4 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 7 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 10 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 9 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 15 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads +system.physmem.totQLat 20326500723 # Total ticks spent queuing +system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54465.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.46 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.47 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing -system.physmem.readRowHits 687654 # Number of row buffer hits during reads -system.physmem.writeRowHits 1056585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.96 # Row buffer hit rate for writes -system.physmem.avgGap 17230665.31 # Average gap between requests -system.physmem.pageHitRate 63.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3832851960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2091337875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3491865000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5991881040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1200455054145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27393437346750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31705942010610 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.749637 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45570820980751 # Time in different power states -system.physmem_0.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing +system.physmem.readRowHits 509481 # Number of row buffer hits during reads +system.physmem.writeRowHits 909439 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes +system.physmem.avgGap 20763390.98 # Average gap between requests +system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.635370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 256810103749 # Time in different power states +system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3728032560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2034144750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3696084600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5819992560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1191404828700 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27401376141000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31704700898010 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.723459 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45584059811251 # Time in different power states -system.physmem_1.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.605711 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 243570222499 # Time in different power states +system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -393,9 +382,9 @@ system.realview.nvmem.bw_total::total 4 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1670 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1673 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -426,66 +415,67 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 107972 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 107972 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9276 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83163 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walks 95467 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 107963 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 107963 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 107963 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 92448 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 17595.764614 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15306.328665 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15454.252367 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 91009 98.44% 98.44% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1235 1.34% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 66 0.07% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 55 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 65 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 92448 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -2398441544 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.163884 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.370170 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -2005375084 83.61% 83.61% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -393066460 16.39% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -2398441544 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 83163 89.97% 89.97% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9276 10.03% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 92439 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 107972 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92439 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 200411 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83792624 # DTB read hits -system.cpu0.dtb.read_misses 78614 # DTB read misses -system.cpu0.dtb.write_hits 76883618 # DTB write hits -system.cpu0.dtb.write_misses 29358 # DTB write misses +system.cpu0.dtb.read_hits 81219280 # DTB read hits +system.cpu0.dtb.read_misses 71070 # DTB read misses +system.cpu0.dtb.write_hits 73504932 # DTB write hits +system.cpu0.dtb.write_misses 24397 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38297 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4651 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10679 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83871238 # DTB read accesses -system.cpu0.dtb.write_accesses 76912976 # DTB write accesses +system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81290350 # DTB read accesses +system.cpu0.dtb.write_accesses 73529329 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 160676242 # DTB hits -system.cpu0.dtb.misses 107972 # DTB misses -system.cpu0.dtb.accesses 160784214 # DTB accesses +system.cpu0.dtb.hits 154724212 # DTB hits +system.cpu0.dtb.misses 95467 # DTB misses +system.cpu0.dtb.accesses 154819679 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -515,236 +505,239 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 64255 # Table walker walks requested -system.cpu0.itb.walker.walksLong 64255 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 637 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58227 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 64255 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 64255 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 64255 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 58864 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 20635.902164 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17664.674655 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19771.927470 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 57276 97.30% 97.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1371 2.33% 99.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.15% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 53 0.09% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 58864 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -673300296 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -673300296 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -673300296 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58227 98.92% 98.92% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 637 1.08% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 58864 # Table walker page sizes translated +system.cpu0.itb.walker.walks 56383 # Table walker walks requested +system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64255 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58864 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58864 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 123119 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 448595101 # ITB inst hits -system.cpu0.itb.inst_misses 64255 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 434853798 # ITB inst hits +system.cpu0.itb.inst_misses 56383 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26739 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 448659356 # ITB inst accesses -system.cpu0.itb.hits 448595101 # DTB hits -system.cpu0.itb.misses 64255 # DTB misses -system.cpu0.itb.accesses 448659356 # DTB accesses -system.cpu0.numCycles 94821563304 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses +system.cpu0.itb.hits 434853798 # DTB hits +system.cpu0.itb.misses 56383 # DTB misses +system.cpu0.itb.accesses 434910181 # DTB accesses +system.cpu0.numCycles 94735635148 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 448345930 # Number of instructions committed -system.cpu0.committedOps 527651436 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 484594714 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 558267 # Number of float alu accesses -system.cpu0.num_func_calls 26890258 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68074268 # number of instructions that are conditional controls -system.cpu0.num_int_insts 484594714 # number of integer instructions -system.cpu0.num_fp_insts 558267 # number of float instructions -system.cpu0.num_int_register_reads 706750752 # number of times the integer registers were read -system.cpu0.num_int_register_writes 384547382 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 893879 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 490056 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 117567828 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 117277075 # number of times the CC registers were written -system.cpu0.num_mem_refs 160668093 # number of memory refs -system.cpu0.num_load_insts 83788812 # Number of load instructions -system.cpu0.num_store_insts 76879281 # Number of store instructions -system.cpu0.num_idle_cycles 93729284290.716034 # Number of idle cycles -system.cpu0.num_busy_cycles 1092279013.283977 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011519 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988481 # Percentage of idle cycles -system.cpu0.Branches 100174256 # Number of branches fetched +system.cpu0.committedInsts 434594659 # Number of instructions committed +system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses +system.cpu0.num_func_calls 25685063 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls +system.cpu0.num_int_insts 468245604 # number of integer instructions +system.cpu0.num_fp_insts 368958 # number of float instructions +system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read +system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written +system.cpu0.num_mem_refs 154715442 # number of memory refs +system.cpu0.num_load_insts 81215665 # Number of load instructions +system.cpu0.num_store_insts 73499777 # Number of store instructions +system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles +system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles +system.cpu0.Branches 96525602 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 365953478 69.32% 69.32% # Class of executed instruction -system.cpu0.op_class::IntMult 1186010 0.22% 69.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 57830 0.01% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 78277 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::MemRead 83788812 15.87% 85.44% # Class of executed instruction -system.cpu0.op_class::MemWrite 76879281 14.56% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction +system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction +system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction +system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 527943731 # Class of executed instruction +system.cpu0.op_class::total 510121531 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5474 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 5753925 # number of replacements -system.cpu0.dcache.tags.tagsinuse 509.684776 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 154679022 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5754435 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.879967 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3644714000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 509.684776 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.995478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.995478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 327127592 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 327127592 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77833401 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77833401 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72535559 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72535559 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180949 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 180949 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 117408 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 117408 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813577 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1813577 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1784599 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1784599 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 150368960 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 150368960 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150549909 # number of overall hits -system.cpu0.dcache.overall_hits::total 150549909 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3079415 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3079415 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1439122 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1439122 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 698265 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 698265 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 782756 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 782756 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172905 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 172905 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200615 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 200615 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4518537 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4518537 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5216802 # number of overall misses -system.cpu0.dcache.overall_misses::total 5216802 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45365631768 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 45365631768 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25986134990 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 25986134990 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 26026367891 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 26026367891 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2610218258 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2610218258 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4265500897 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4265500897 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2243000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2243000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 71351766758 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 71351766758 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 71351766758 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 71351766758 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80912816 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80912816 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73974681 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73974681 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 879214 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 879214 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 900164 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 900164 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1986482 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1986482 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1985214 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1985214 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154887497 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 154887497 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 155766711 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 155766711 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038058 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.038058 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019454 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.019454 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.794192 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.794192 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.869570 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.869570 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101055 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101055 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029173 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029173 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.033491 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.033491 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14731.899328 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.899328 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18056.936792 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18056.936792 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 33249.656203 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 33249.656203 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15096.256661 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15096.256661 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21262.123455 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21262.123455 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5284481 # number of replacements +system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69444390 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 145184458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 145361912 # number of overall hits +system.cpu0.dcache.overall_hits::total 145361912 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2820396 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2820396 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1320543 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1320543 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635767 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 746024 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 746024 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156072 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 182947 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 182947 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4140939 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4776706 # number of overall misses +system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39561901741 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39561901741 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24338572363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24338572363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30943018074 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30943018074 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2147538753 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2147538753 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3961701456 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3961701456 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1248500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1248500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 63900474104 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 63900474104 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 63900474104 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 63900474104 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78560464 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78560464 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 70764933 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 70764933 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 813221 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 813221 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 889124 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 889124 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1818372 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1818372 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1817042 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1817042 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 149325397 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149325397 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150138618 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.035901 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018661 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781789 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839055 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100684 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027731 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15790.900187 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15790.900187 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13677.300146 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13677.300146 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15431.397107 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15431.397107 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13377.518755 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13377.518755 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,92 +746,92 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3895213 # number of writebacks -system.cpu0.dcache.writebacks::total 3895213 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 35120 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 35120 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21470 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21470 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46933 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46933 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 56590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 56590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 56590 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 56590 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3044295 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3044295 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1417652 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1417652 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 692633 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 692633 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 782756 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 782756 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125972 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125972 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200615 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 200615 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4461947 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4461947 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5154580 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5154580 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37795344499 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37795344499 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22579422262 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22579422262 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14234213672 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14234213672 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24458156109 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24458156109 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564829744 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564829744 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3853276103 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3853276103 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2137000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2137000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60374766761 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 60374766761 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74608980433 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 74608980433 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2287793998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2287793998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2244465248 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2244465248 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4532259246 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4532259246 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037624 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037624 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019164 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019164 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.787787 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.787787 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.869570 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.869570 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063415 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063415 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101055 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101055 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028808 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028808 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033092 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033092 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12415.138644 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12415.138644 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15927.337782 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15927.337782 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20550.874232 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20550.874232 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31246.207131 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 31246.207131 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12422.044137 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.044137 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19207.318012 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19207.318012 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3634622 # number of writebacks +system.cpu0.dcache.writebacks::total 3634622 # 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number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1299186 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1299186 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 630147 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 630147 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 746024 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 746024 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117927 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117927 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 182947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 182947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4090970 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4090970 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4721117 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4721117 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34314944268 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34314944268 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 21777665637 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21777665637 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12432309289 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12432309289 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29820271426 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29820271426 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1422971246 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1422971246 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3676791544 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3676791544 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1208000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1208000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 56092609905 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 56092609905 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68524919194 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 68524919194 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4525228998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4525228998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4129291250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4129291250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8654520248 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8654520248 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035537 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035537 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774878 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774878 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839055 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839055 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064853 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064853 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100684 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100684 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027396 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027396 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031445 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031445 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12291.403729 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12291.403729 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16762.546423 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16762.546423 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19729.220783 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19729.220783 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39972.268219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39972.268219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12066.543251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12066.543251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20097.577681 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20097.577681 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13531.036286 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13531.036286 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14474.308369 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14474.308369 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13711.322719 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13711.322719 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14514.556448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14514.556448 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -846,58 +839,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5166576 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.910022 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 443428013 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5167088 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.817778 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30209622750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.910022 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999824 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999824 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 4499955 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.899412 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 430353331 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4500467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 95.624150 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 33435593250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899412 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999804 # 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number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 53694723563 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 53694723563 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 53694723563 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 53694723563 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 448595101 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 448595101 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 448595101 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 448595101 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 448595101 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 448595101 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011518 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011518 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011518 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011518 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011518 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011518 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10391.679717 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10391.679717 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10391.679717 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10391.679717 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 874208063 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 874208063 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 430353331 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 430353331 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 430353331 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 430353331 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 430353331 # number of overall hits +system.cpu0.icache.overall_hits::total 430353331 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4500467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4500467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4500467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4500467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4500467 # 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number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 434853798 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 434853798 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010349 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010349 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010349 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010349 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010349 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010349 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10614.134928 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10614.134928 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10614.134928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10614.134928 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -906,241 +899,240 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5167088 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5167088 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5167088 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5167088 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5167088 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5167088 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45925261947 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 45925261947 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45925261947 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 45925261947 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45925261947 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 45925261947 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011518 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011518 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011518 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8888.035572 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4500467 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4500467 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4500467 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4500467 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4500467 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4500467 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 43254050535 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 43254050535 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 43254050535 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 43254050535 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 43254050535 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 43254050535 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3811870500 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 592 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 515 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 17 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 811 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4617 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5283 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3880 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.085083 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.894775 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 232158629 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 232158629 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 184213 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122134 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 3989528 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2659243 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 6955118 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3634621 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3634621 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 174040 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 174040 # 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mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205407 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205407 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205169 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205169 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172480 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231978 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26026.451805 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25072.510487 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49425.192319 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 34326.997887 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34326.997887 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16986.530742 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16986.530742 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13741.236699 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13741.236699 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 214125 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 214125 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36924.550389 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36924.550389 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26740.395420 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33232.542850 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239706 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24493.654964 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23901.499212 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 36215.315810 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42441.441675 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42441.441675 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20873.741897 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20873.741897 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15129.520789 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15129.520789 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 335166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 335166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38586.013882 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38586.013882 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25928.818372 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28813.655266 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1292,58 +1284,56 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 11541292 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9690709 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15329 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15329 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3895213 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1069383 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166255 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 781481 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 444610 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368177 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 498972 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1328849 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1215209 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10420426 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16690518 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 351532 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 549297 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 28011773 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 330866132 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 630631769 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1276280 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1881728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 964655909 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4194903 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 19756578 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.197801 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.398341 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 15848715 80.22% 80.22% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 3907863 19.78% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 19756578 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 12645685295 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 194485993 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7813325558 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8298663367 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 192341003 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 314436506 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1374,74 +1364,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 99527 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 99527 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9603 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 74573 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walks 92509 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 99518 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.271308 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 67.169326 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 99516 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 99518 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 84185 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 16581.674289 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 15037.130908 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 10932.627488 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 81471 96.78% 96.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2185 2.60% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 285 0.34% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 159 0.19% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 18 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 84185 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1589468256 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.778279 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.415405 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -352419148 22.17% 22.17% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -1237049108 77.83% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1589468256 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 74574 88.59% 88.59% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9603 11.41% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 84177 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99527 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84177 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 183704 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 83767099 # DTB read hits -system.cpu1.dtb.read_misses 74857 # DTB read misses -system.cpu1.dtb.write_hits 75685520 # DTB write hits -system.cpu1.dtb.write_misses 24670 # DTB write misses +system.cpu1.dtb.read_hits 78277454 # DTB read hits +system.cpu1.dtb.read_misses 68245 # DTB read misses +system.cpu1.dtb.write_hits 71517077 # DTB write hits +system.cpu1.dtb.write_misses 24264 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36584 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4104 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9015 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 83841956 # DTB read accesses -system.cpu1.dtb.write_accesses 75710190 # DTB write accesses +system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 78345699 # DTB read accesses +system.cpu1.dtb.write_accesses 71541341 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 159452619 # DTB hits -system.cpu1.dtb.misses 99527 # DTB misses -system.cpu1.dtb.accesses 159552146 # DTB accesses +system.cpu1.dtb.hits 149794531 # DTB hits +system.cpu1.dtb.misses 92509 # DTB misses +system.cpu1.dtb.accesses 149887040 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1471,239 +1454,242 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 55326 # Table walker walks requested -system.cpu1.itb.walker.walksLong 55326 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 571 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 55326 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 55326 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 55326 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 49782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 18533.691816 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 16693.913266 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 13345.941074 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47101 94.61% 94.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 2168 4.35% 98.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 178 0.36% 99.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 248 0.50% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 24 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 18 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 49782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1199136648 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1199136648 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1199136648 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 49211 98.85% 98.85% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 571 1.15% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 49782 # Table walker page sizes translated +system.cpu1.itb.walker.walks 60524 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 55326 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49782 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49782 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 105108 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 441493680 # ITB inst hits -system.cpu1.itb.inst_misses 55326 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 409921957 # ITB inst hits +system.cpu1.itb.inst_misses 60524 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25739 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 441549006 # ITB inst accesses -system.cpu1.itb.hits 441493680 # DTB hits -system.cpu1.itb.misses 55326 # DTB misses -system.cpu1.itb.accesses 441549006 # DTB accesses -system.cpu1.numCycles 94821563303 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses +system.cpu1.itb.hits 409921957 # DTB hits +system.cpu1.itb.misses 60524 # DTB misses +system.cpu1.itb.accesses 409982481 # DTB accesses +system.cpu1.numCycles 94735635148 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 441187041 # Number of instructions committed -system.cpu1.committedOps 519063105 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 477531543 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 364386 # Number of float alu accesses -system.cpu1.num_func_calls 26570520 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 66815511 # number of instructions that are conditional controls -system.cpu1.num_int_insts 477531543 # number of integer instructions -system.cpu1.num_fp_insts 364386 # number of float instructions -system.cpu1.num_int_register_reads 690361032 # number of times the integer registers were read -system.cpu1.num_int_register_writes 378560518 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 602629 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 273816 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 113424708 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113111436 # number of times the CC registers were written -system.cpu1.num_mem_refs 159443034 # number of memory refs -system.cpu1.num_load_insts 83763663 # Number of load instructions -system.cpu1.num_store_insts 75679371 # Number of store instructions -system.cpu1.num_idle_cycles 93795188251.508850 # Number of idle cycles -system.cpu1.num_busy_cycles 1026375051.491154 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010824 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989176 # Percentage of idle cycles -system.cpu1.Branches 98214896 # Number of branches fetched +system.cpu1.committedInsts 409652284 # Number of instructions committed +system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses +system.cpu1.num_func_calls 25682090 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls +system.cpu1.num_int_insts 446181756 # number of integer instructions +system.cpu1.num_fp_insts 565626 # number of float instructions +system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read +system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written +system.cpu1.num_mem_refs 149782083 # number of memory refs +system.cpu1.num_load_insts 78271508 # Number of load instructions +system.cpu1.num_store_insts 71510575 # Number of store instructions +system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles +system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles +system.cpu1.Branches 91673037 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 358777055 69.08% 69.08% # Class of executed instruction -system.cpu1.op_class::IntMult 1052972 0.20% 69.28% # Class of executed instruction -system.cpu1.op_class::IntDiv 61499 0.01% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 35293 0.01% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::MemRead 83763663 16.13% 85.43% # Class of executed instruction -system.cpu1.op_class::MemWrite 75679371 14.57% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction +system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction +system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction +system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 519369853 # Class of executed instruction +system.cpu1.op_class::total 484255317 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13999 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 4977655 # number of replacements -system.cpu1.dcache.tags.tagsinuse 421.597899 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 154271186 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4978165 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.989569 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8379002972500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.597899 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823433 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.823433 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 442 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 323862009 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 323862009 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 78232018 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 78232018 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 71864508 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 71864508 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191698 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 191698 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 211446 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 211446 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1712714 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1712714 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1673213 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1673213 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 150096526 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 150096526 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 150288224 # number of overall hits -system.cpu1.dcache.overall_hits::total 150288224 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2870044 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2870044 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1235849 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1235849 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 574884 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 574884 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 468795 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 468795 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 161452 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 161452 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199386 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 199386 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4105893 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4105893 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4680777 # number of overall misses -system.cpu1.dcache.overall_misses::total 4680777 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39400522531 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 39400522531 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20561069776 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 20561069776 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12119187041 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12119187041 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2308132257 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2308132257 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4261474455 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4261474455 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1966000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1966000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 59961592307 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 59961592307 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 59961592307 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 59961592307 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 81102062 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 81102062 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 73100357 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 73100357 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 766582 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 766582 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 680241 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 680241 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1874166 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1874166 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1872599 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1872599 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154202419 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154202419 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 154969001 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 154969001 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035388 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035388 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016906 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.016906 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.749932 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.749932 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.689160 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.689160 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086146 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086146 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106476 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106476 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026627 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026627 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030205 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.030205 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13728.194596 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13728.194596 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16637.202260 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16637.202260 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 25851.783916 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 25851.783916 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14296.089593 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14296.089593 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21372.987346 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21372.987346 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 4752540 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits +system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4421172 # number of overall misses +system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3770896575 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 57180589082 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 57180589082 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 75812564 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69041424 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 682821 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1770246 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1770246 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1769125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1769125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 144853988 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 144853988 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 145536809 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 145536809 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036506 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036506 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.730474 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # 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average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14603.788337 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14603.788337 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12810.179230 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 12810.179230 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1712,92 +1698,92 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8032885000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035243 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035243 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016902 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749932 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.749932 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.689160 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.689160 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063309 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063309 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106476 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106476 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026548 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026548 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030127 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11561.350275 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11561.350275 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14585.485290 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14585.485290 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18085.647294 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18085.647294 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 23844.142875 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 23844.142875 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12025.119602 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12025.119602 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19320.546804 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19320.546804 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks +system.cpu1.dcache.writebacks::total 3063492 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 352 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46682 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46682 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 11897 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 11897 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 11897 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2756082 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2756082 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1154410 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1154410 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 498783 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 498783 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 496292 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 496292 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111639 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111639 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 3910492 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 3910492 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4409275 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 32859790378 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 32859790378 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 17743172214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 17743172214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9770846491 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11134079098 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11134079098 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3498646925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498646925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 50602962592 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60373809083 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 60373809083 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1936116751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1936116751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2164016499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2164016499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4100133250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4100133250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036354 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036354 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016721 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016721 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.730474 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.730474 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.724271 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.724271 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063064 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063064 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099636 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099636 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026996 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026996 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030297 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030297 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11922.646125 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11922.646125 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15369.905158 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15369.905158 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19589.373517 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22434.532690 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12507.349564 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19848.451931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19848.451931 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12474.075096 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12474.075096 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13165.060396 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13165.060396 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12940.305873 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12940.305873 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13692.457169 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13692.457169 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1805,59 +1791,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4937125 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.391317 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 436556038 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4937637 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 88.413960 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8378975635000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.391317 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969514 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969514 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5523110 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.341944 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 404398330 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5523622 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 73.212528 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8382258847250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.341944 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969418 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969418 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 887925002 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 887925002 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 436556038 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 436556038 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 436556038 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 436556038 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 436556038 # number of overall hits -system.cpu1.icache.overall_hits::total 436556038 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4937642 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4937642 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4937642 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4937642 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4937642 # number of overall misses -system.cpu1.icache.overall_misses::total 4937642 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50835870381 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 50835870381 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 50835870381 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 50835870381 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 50835870381 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 50835870381 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 441493680 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 441493680 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 441493680 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 441493680 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 441493680 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 441493680 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011184 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011184 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011184 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011184 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011184 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011184 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10295.576387 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10295.576387 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10295.576387 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10295.576387 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 825367541 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 825367541 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 404398330 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 404398330 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 404398330 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 404398330 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 404398330 # number of overall hits +system.cpu1.icache.overall_hits::total 404398330 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5523627 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5523627 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5523627 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5523627 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5523627 # number of overall misses +system.cpu1.icache.overall_misses::total 5523627 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54612807078 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 54612807078 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 54612807078 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 54612807078 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 54612807078 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 54612807078 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 409921957 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 409921957 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 409921957 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 409921957 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 409921957 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 409921957 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013475 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013475 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013475 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013475 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013475 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013475 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9887.127983 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9887.127983 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9887.127983 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9887.127983 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1866,239 +1852,236 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4937642 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 4937642 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 4937642 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 4937642 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 4937642 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 4937642 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43414323627 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 43414323627 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43414323627 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 43414323627 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43414323627 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 43414323627 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8951000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8951000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8951000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8951000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011184 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011184 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011184 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8792.521537 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5523627 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5523627 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5523627 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5523627 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5523627 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5523627 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49075741422 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 49075741422 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49075741422 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 49075741422 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49075741422 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 49075741422 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9805750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9805750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9805750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9805750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013475 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013475 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013475 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8884.695042 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6896094 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6896721 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 539 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 5870481 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 5870524 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 853759 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 1907013 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13040.746764 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10338978 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1923015 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.376442 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9789299685500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5807.381964 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.245810 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 78.947620 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2946.895146 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3156.020749 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 990.255474 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.354454 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003738 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004819 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.179864 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.192628 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060440 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.795944 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1412 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 94 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1121 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 188 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1044 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1799 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 10295 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.086182 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005737 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 227501804 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 227501804 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 207163 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 127057 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4446186 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2697591 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7477997 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3230902 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3230902 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 181429 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 181429 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 59189 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 59189 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31769 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 31769 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 842543 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 842543 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 207163 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 127057 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4446186 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3540134 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8320540 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 207163 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 127057 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4446186 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3540134 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8320540 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 8925 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 6995 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 491456 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 854192 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1361568 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 285701 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 285701 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 127179 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 127179 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167611 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 167611 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 208488 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 208488 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 8925 # 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number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 25122385610 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 39875944424 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 189007871 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 189007871 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2544221753 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2544221753 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3390574541 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3390574541 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1824999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1824999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8358339864 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 8358339864 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 266500250 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 219567495 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 14267491069 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 33480725474 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 48234284288 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 266500250 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 219567495 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 14267491069 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 33480725474 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 48234284288 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 216088 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 134052 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4937642 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3551783 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 8839565 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3230902 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3230902 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 467130 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 467130 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 186368 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 186368 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199380 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 199380 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051031 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1051031 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 216088 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 134052 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4937642 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4602814 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 9890596 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 216088 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 134052 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4937642 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4602814 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 9890596 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.041303 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052181 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.099533 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.240497 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.154031 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.611609 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.611609 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.682408 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.682408 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.840661 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.840661 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 773012 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 1638473 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13410.207774 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10772955 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1654198 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.512494 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10040948806000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5186.730932 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.626422 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.861590 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3789.090493 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3453.027216 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 821.871120 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.316573 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 601 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6290 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5121 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.098633 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005005 # 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number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 146711 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 5082589 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3367812 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8793955 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9130 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7601 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 441038 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 776098 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1233867 # number of ReadReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 229595 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 229595 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120541 # 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average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30095.390338 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2246,66 +2229,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 11132088 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9059631 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 23142 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 23142 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3230902 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 957658 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1110389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 467130 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 407372 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365584 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 452132 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1208854 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1057926 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9875504 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14402767 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 299311 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 504421 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 25082003 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 316009528 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 537745480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1072416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1728704 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 856556128 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4579678 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 18388489 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.234421 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.423637 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 14077834 76.56% 76.56% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 4310655 23.44% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 18388489 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 10772824519 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 181931492 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7414134377 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7417250282 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 165377004 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 288475000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40416 # Transaction distribution -system.iobus.trans_dist::ReadResp 40416 # Transaction distribution -system.iobus.trans_dist::WriteReq 136984 # Transaction distribution -system.iobus.trans_dist::WriteResp 30064 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48038 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40336 # Transaction distribution +system.iobus.trans_dist::ReadResp 40336 # Transaction distribution +system.iobus.trans_dist::WriteReq 136623 # Transaction distribution +system.iobus.trans_dist::WriteResp 29895 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2315,18 +2295,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231644 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354800 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2336,18 +2316,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17645 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156137 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351344 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7351344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7509567 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36527000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2367,7 +2347,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22064000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2375,71 +2355,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1044902599 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607542087 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93015000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179432954 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148516061 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115804 # number of replacements -system.iocache.tags.tagsinuse 11.285754 # Cycle average of tags in use +system.iocache.tags.replacements 115606 # number of replacements +system.iocache.tags.tagsinuse 11.280528 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115820 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9175904776000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.836841 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.448912 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239803 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465557 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705360 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9179145722000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.421794 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.858734 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463862 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.241171 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705033 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042755 # Number of tag accesses -system.iocache.tags.data_accesses 1042755 # Number of data accesses +system.iocache.tags.tag_accesses 1040802 # Number of tag accesses +system.iocache.tags.data_accesses 1040802 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses -system.iocache.demand_misses::total 8942 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses +system.iocache.demand_misses::total 8917 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8902 # number of overall misses -system.iocache.overall_misses::total 8942 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1942659591 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1948366591 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28987663054 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28987663054 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1942659591 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1948723591 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1942659591 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1948723591 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8877 # number of overall misses +system.iocache.overall_misses::total 8917 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1629440754 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1634636254 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19888935272 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19888935272 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1629440754 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1635005254 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1629440754 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1635005254 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2453,55 +2433,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 218227.318692 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217962.478018 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271115.441957 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271115.441957 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217929.276560 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217929.276560 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 228501 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183557.593106 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183378.534216 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186351.615996 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186351.615996 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183358.220702 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183358.220702 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110662 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27689 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16220 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.252411 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.822565 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106887 # number of writebacks -system.iocache.writebacks::total 106887 # number of writebacks +system.iocache.writebacks::writebacks 106699 # number of writebacks +system.iocache.writebacks::total 106699 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1479616613 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1483399613 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427435940 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427435940 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1479616613 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1483600613 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1479616613 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1483600613 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166654804 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1169925304 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14339007344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14339007344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1166654804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1170138304 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1166654804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1170138304 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2515,560 +2495,561 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166211.706695 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165946.930641 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219111.821362 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219111.821362 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131424.445646 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 131245.827238 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134350.942058 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134350.942058 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1354462 # number of replacements -system.l2c.tags.tagsinuse 64231.297434 # Cycle average of tags in use -system.l2c.tags.total_refs 4107458 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1415378 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.902022 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9445810500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 19768.926665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 228.224478 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 327.605712 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4403.400979 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 13076.363837 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14280.609802 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 81.212634 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 119.963342 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2392.943065 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3574.441825 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5977.605096 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.301650 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003482 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004999 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.067191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.199529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217905 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001239 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001830 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.036513 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.054542 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.091211 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.980092 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11341 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 263 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49312 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 2022 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9219 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9958 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 38095 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.173050 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004013 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.752441 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 56299103 # 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 103357750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 2790521653 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 9390062347 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 56244035668 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3774730500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6744750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1609448501 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7996683251 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3450397000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1827911500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5278308500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7225127500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6744750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3437360001 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13274991751 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.149057 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172689 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.182588 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759197 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.477347 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.679626 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605334 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.632275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.617082 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.621773 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.611004 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.617104 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573401 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486396 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.534643 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.205409 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.205409 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77325.734556 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75217.333798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 91240.104337 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32418.974964 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31451.308706 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32227.094697 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17780.279250 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17794.118065 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.462483 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17815.791525 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17872.145516 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.981482 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74622.680148 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69151.437191 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72405.364770 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3083,58 +3064,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 841910 # Transaction distribution -system.membus.trans_dist::ReadResp 841910 # Transaction distribution -system.membus.trans_dist::WriteReq 38471 # Transaction distribution -system.membus.trans_dist::WriteResp 38471 # Transaction distribution -system.membus.trans_dist::Writeback 1161772 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 665270 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 665270 # Transaction distribution -system.membus.trans_dist::UpgradeReq 386597 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 321242 # Transaction distribution -system.membus.trans_dist::UpgradeResp 114625 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 138806 # Transaction distribution -system.membus.trans_dist::ReadExResp 121371 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123076 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 622157 # Transaction distribution +system.membus.trans_dist::ReadResp 622157 # Transaction distribution +system.membus.trans_dist::WriteReq 38973 # Transaction distribution +system.membus.trans_dist::WriteResp 38973 # Transaction distribution +system.membus.trans_dist::Writeback 957695 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 636331 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution +system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution +system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution +system.membus.trans_dist::ReadExReq 123220 # Transaction distribution +system.membus.trans_dist::ReadExResp 104410 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122628 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4847759 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4996369 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336372 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336372 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5332741 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159245812 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 159453037 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14112640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14112640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 173565677 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 613627 # Total snoops (count) -system.membus.snoop_fanout::samples 3433927 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 581158 # Total snoops (count) +system.membus.snoop_fanout::samples 2928688 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3433927 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3433927 # Request fanout histogram -system.membus.reqLayer0.occupancy 100976496 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2928688 # Request fanout histogram +system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22065500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 18062213474 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9212060141 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187637046 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3178,45 +3159,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4185645 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4178412 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38471 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38471 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2302237 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 921111 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 814190 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 436280 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 333774 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 770054 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 280654 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 280654 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7279651 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5709072 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 12988723 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243910125 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179631296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 423541421 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1593139 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8378399 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.013829 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.116780 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1518303 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 8262536 98.62% 98.62% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115863 1.38% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8378399 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 16938572035 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7678500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 11018810399 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 9692180196 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 11eb5dd0c..d577712e0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821157 # Number of seconds simulated -sim_ticks 51821157171000 # Number of ticks simulated -final_tick 51821157171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.824462 # Number of seconds simulated +sim_ticks 51824462100500 # Number of ticks simulated +final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 734878 # Simulator instruction rate (inst/s) -host_op_rate 863519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42416153440 # Simulator tick rate (ticks/s) -host_mem_usage 712380 # Number of bytes of host memory used -host_seconds 1221.73 # Real time elapsed on the host -sim_insts 897823750 # Number of instructions simulated -sim_ops 1054987960 # Number of ops (including micro ops) simulated +host_inst_rate 723017 # Simulator instruction rate (inst/s) +host_op_rate 849578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41937024652 # Simulator tick rate (ticks/s) +host_mem_usage 712044 # Number of bytes of host memory used +host_seconds 1235.77 # Real time elapsed on the host +sim_insts 893481288 # Number of instructions simulated +sim_ops 1049881338 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 267456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 270528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5250612 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 52674824 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 383808 # Number of bytes read from this memory -system.physmem.bytes_read::total 58847228 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5250612 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5250612 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79637568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory +system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 79658148 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4179 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 122448 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 823057 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 5997 # Number of read requests responded to by this memory -system.physmem.num_reads::total 959908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1244337 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory +system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1246910 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 101322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1016473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1135583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1536777 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1537174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1536777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1016870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2672757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 959908 # Number of read requests accepted -system.physmem.writeReqs 1865455 # Number of write requests accepted -system.physmem.readBursts 959908 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1865455 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61382336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 51776 # Total number of bytes read from write queue -system.physmem.bytesWritten 118954432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58847228 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 119245028 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 809 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6774 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 36275 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 56974 # Per bank write bursts -system.physmem.perBankRdBursts::1 60608 # Per bank write bursts -system.physmem.perBankRdBursts::2 56247 # Per bank write bursts -system.physmem.perBankRdBursts::3 58787 # Per bank write bursts -system.physmem.perBankRdBursts::4 55621 # Per bank write bursts -system.physmem.perBankRdBursts::5 61105 # Per bank write bursts -system.physmem.perBankRdBursts::6 53454 # Per bank write bursts -system.physmem.perBankRdBursts::7 55202 # Per bank write bursts -system.physmem.perBankRdBursts::8 54549 # Per bank write bursts -system.physmem.perBankRdBursts::9 101006 # Per bank write bursts -system.physmem.perBankRdBursts::10 57136 # Per bank write bursts -system.physmem.perBankRdBursts::11 59250 # Per bank write bursts -system.physmem.perBankRdBursts::12 54470 # Per bank write bursts -system.physmem.perBankRdBursts::13 61564 # Per bank write bursts -system.physmem.perBankRdBursts::14 57688 # Per bank write bursts -system.physmem.perBankRdBursts::15 55438 # Per bank write bursts -system.physmem.perBankWrBursts::0 113578 # Per bank write bursts -system.physmem.perBankWrBursts::1 118177 # Per bank write bursts -system.physmem.perBankWrBursts::2 119014 # Per bank write bursts -system.physmem.perBankWrBursts::3 122732 # Per bank write bursts -system.physmem.perBankWrBursts::4 115108 # Per bank write bursts -system.physmem.perBankWrBursts::5 118421 # Per bank write bursts -system.physmem.perBankWrBursts::6 110433 # Per bank write bursts -system.physmem.perBankWrBursts::7 110649 # Per bank write bursts -system.physmem.perBankWrBursts::8 111009 # Per bank write bursts -system.physmem.perBankWrBursts::9 115530 # Per bank write bursts -system.physmem.perBankWrBursts::10 116272 # Per bank write bursts -system.physmem.perBankWrBursts::11 116171 # Per bank write bursts -system.physmem.perBankWrBursts::12 116950 # Per bank write bursts -system.physmem.perBankWrBursts::13 121923 # Per bank write bursts -system.physmem.perBankWrBursts::14 117171 # Per bank write bursts -system.physmem.perBankWrBursts::15 115525 # Per bank write bursts +system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 923811 # Number of read requests accepted +system.physmem.writeReqs 1833124 # Number of write requests accepted +system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue +system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 57129 # Per bank write bursts +system.physmem.perBankRdBursts::1 60965 # Per bank write bursts +system.physmem.perBankRdBursts::2 52485 # Per bank write bursts +system.physmem.perBankRdBursts::3 50413 # Per bank write bursts +system.physmem.perBankRdBursts::4 54002 # Per bank write bursts +system.physmem.perBankRdBursts::5 59718 # Per bank write bursts +system.physmem.perBankRdBursts::6 51713 # Per bank write bursts +system.physmem.perBankRdBursts::7 51669 # Per bank write bursts +system.physmem.perBankRdBursts::8 50247 # Per bank write bursts +system.physmem.perBankRdBursts::9 101235 # Per bank write bursts +system.physmem.perBankRdBursts::10 59848 # Per bank write bursts +system.physmem.perBankRdBursts::11 58323 # Per bank write bursts +system.physmem.perBankRdBursts::12 55369 # Per bank write bursts +system.physmem.perBankRdBursts::13 55988 # Per bank write bursts +system.physmem.perBankRdBursts::14 51743 # Per bank write bursts +system.physmem.perBankRdBursts::15 52477 # Per bank write bursts +system.physmem.perBankWrBursts::0 110630 # Per bank write bursts +system.physmem.perBankWrBursts::1 112240 # Per bank write bursts +system.physmem.perBankWrBursts::2 108805 # Per bank write bursts +system.physmem.perBankWrBursts::3 108103 # Per bank write bursts +system.physmem.perBankWrBursts::4 111102 # Per bank write bursts +system.physmem.perBankWrBursts::5 113339 # Per bank write bursts +system.physmem.perBankWrBursts::6 105567 # Per bank write bursts +system.physmem.perBankWrBursts::7 107723 # Per bank write bursts +system.physmem.perBankWrBursts::8 108849 # Per bank write bursts +system.physmem.perBankWrBursts::9 115780 # Per bank write bursts +system.physmem.perBankWrBursts::10 115663 # Per bank write bursts +system.physmem.perBankWrBursts::11 113049 # Per bank write bursts +system.physmem.perBankWrBursts::12 112494 # Per bank write bursts +system.physmem.perBankWrBursts::13 116984 # Per bank write bursts +system.physmem.perBankWrBursts::14 111502 # Per bank write bursts +system.physmem.perBankWrBursts::15 110389 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51821154615000 # Total gap between requests +system.physmem.numWrRetry 145 # Number of times write queue was full causing retry +system.physmem.totGap 51824459475500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 916792 # Read request sizes (log2) +system.physmem.readPktSize::6 880695 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1862882 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 923488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 30071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1830551 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,181 +159,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 58678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 72148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 102041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 104846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 108153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 122813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 127000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 113028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 114051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 111714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 109570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 106267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 103051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 101586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 96822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 95736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 95578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 94283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 618930 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.368084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.608476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.498173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 256436 41.43% 41.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 152224 24.59% 66.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51996 8.40% 74.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28892 4.67% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20098 3.25% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13547 2.19% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10018 1.62% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9306 1.50% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 76413 12.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 618930 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 92468 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.372118 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 105.903641 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 92466 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 57524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 60978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 91825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 117209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 106855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 97040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 98714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 93369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 94185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 92986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 93402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 98737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 96397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 94916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 105152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 97025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 94048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 92817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 92468 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 92468 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.100608 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.118632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.444453 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 55053 59.54% 59.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 30512 33.00% 92.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2134 2.31% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1149 1.24% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 862 0.93% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 455 0.49% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 271 0.29% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 154 0.17% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 523 0.57% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 85 0.09% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 63 0.07% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 90 0.10% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 138 0.15% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 53 0.06% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 45 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 77 0.08% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 126 0.14% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 47 0.05% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 24 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 42 0.05% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 157 0.17% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 21 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 16 0.02% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 59 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 9 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 28 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 35 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 128 0.14% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 15 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 16 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 15 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 10 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 92468 # Writes before turning the bus around for reads -system.physmem.totQLat 12424177254 # Total ticks spent queuing -system.physmem.totMemAccLat 30407283504 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4795495000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12954.01 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads +system.physmem.totQLat 12043609520 # Total ticks spent queuing +system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31704.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.30 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.29 # Average write queue length when enqueuing -system.physmem.readRowHits 722238 # Number of row buffer hits during reads -system.physmem.writeRowHits 1476593 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes -system.physmem.avgGap 18341414.75 # Average gap between requests -system.physmem.pageHitRate 78.03 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2336584320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1274922000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3572345400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6014165760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1308692927565 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29944715868000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34651312636245 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.671195 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49815023694250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing +system.physmem.readRowHits 694872 # Number of row buffer hits during reads +system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes +system.physmem.avgGap 18797853.22 # Average gap between requests +system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.655841 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 275710901250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2342526480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1278164250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3908587800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6029970480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1310912306640 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29942769044250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34651946423100 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.683425 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49811721549250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.672178 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 279009798250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -387,73 +371,68 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 215397 # Table walker walks requested -system.cpu.dtb.walker.walksLong 215397 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16603 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 166513 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walks 211321 # Table walker walks requested +system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 215383 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.157858 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 54.935133 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 215381 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 215383 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 183130 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 21825.061432 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 17519.574906 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 14463.524428 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 181175 98.93% 98.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 4 0.00% 98.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1496 0.82% 99.75% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 183 0.10% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 74 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 58 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-229375 49 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::229376-262143 36 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 18 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::360448-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 183130 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 800972760 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 2.488036 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -1191876296 -148.80% -148.80% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 1992849056 248.80% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 800972760 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 166514 90.93% 90.93% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16603 9.07% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 183117 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 215397 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183117 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 398514 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168647599 # DTB read hits -system.cpu.dtb.read_misses 158984 # DTB read misses -system.cpu.dtb.write_hits 153347297 # DTB write hits -system.cpu.dtb.write_misses 56413 # DTB write misses +system.cpu.dtb.read_hits 167775531 # DTB read hits +system.cpu.dtb.read_misses 155743 # DTB read misses +system.cpu.dtb.write_hits 152648275 # DTB write hits +system.cpu.dtb.write_misses 55578 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 74349 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 8039 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 168806583 # DTB read accesses -system.cpu.dtb.write_accesses 153403710 # DTB write accesses +system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 167931274 # DTB read accesses +system.cpu.dtb.write_accesses 152703853 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 321994896 # DTB hits -system.cpu.dtb.misses 215397 # DTB misses -system.cpu.dtb.accesses 322210293 # DTB accesses +system.cpu.dtb.hits 320423806 # DTB hits +system.cpu.dtb.misses 211321 # DTB misses +system.cpu.dtb.accesses 320635127 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,91 +462,97 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 123370 # Table walker walks requested -system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1120 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 111048 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 112168 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 24898.509379 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 20785.013360 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 17155.421945 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 109848 97.93% 97.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2031 1.81% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 132 0.12% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 23 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 112168 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -1257598296 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -1257598296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -1257598296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 111048 99.00% 99.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1120 1.00% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 112168 # Table walker page sizes translated +system.cpu.itb.walker.walks 122916 # Table walker walks requested +system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112168 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 112168 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 235538 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 898375907 # ITB inst hits -system.cpu.itb.inst_misses 123370 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 894030670 # ITB inst hits +system.cpu.itb.inst_misses 122916 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52826 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 898499277 # ITB inst accesses -system.cpu.itb.hits 898375907 # DTB hits -system.cpu.itb.misses 123370 # DTB misses -system.cpu.itb.accesses 898499277 # DTB accesses -system.cpu.numCycles 103642314342 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 894153586 # ITB inst accesses +system.cpu.itb.hits 894030670 # DTB hits +system.cpu.itb.misses 122916 # DTB misses +system.cpu.itb.accesses 894153586 # DTB accesses +system.cpu.numCycles 103648924201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 897823750 # Number of instructions committed -system.cpu.committedOps 1054987960 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 968534129 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 900653 # Number of float alu accesses -system.cpu.num_func_calls 53156799 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 137185420 # number of instructions that are conditional controls -system.cpu.num_int_insts 968534129 # number of integer instructions -system.cpu.num_fp_insts 900653 # number of float instructions -system.cpu.num_int_register_reads 1413400107 # number of times the integer registers were read -system.cpu.num_int_register_writes 768429309 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1451290 # number of times the floating registers were read -system.cpu.num_fp_register_writes 764324 # number of times the floating registers were written -system.cpu.num_cc_register_reads 236274909 # number of times the CC registers were read -system.cpu.num_cc_register_writes 235673566 # number of times the CC registers were written -system.cpu.num_mem_refs 321978685 # number of memory refs -system.cpu.num_load_insts 168640749 # Number of load instructions -system.cpu.num_store_insts 153337936 # Number of store instructions -system.cpu.num_idle_cycles 100474351324.032059 # Number of idle cycles -system.cpu.num_busy_cycles 3167963017.967939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030566 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969434 # Percentage of idle cycles -system.cpu.Branches 200551202 # Number of branches fetched +system.cpu.committedInsts 893481288 # Number of instructions committed +system.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses +system.cpu.num_func_calls 52999943 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls +system.cpu.num_int_insts 963989017 # number of integer instructions +system.cpu.num_fp_insts 895873 # number of float instructions +system.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read +system.cpu.num_int_register_writes 764688301 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read +system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written +system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read +system.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written +system.cpu.num_mem_refs 320407593 # number of memory refs +system.cpu.num_load_insts 167768846 # Number of load instructions +system.cpu.num_store_insts 152638747 # Number of store instructions +system.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles +system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969376 # Percentage of idle cycles +system.cpu.Branches 199584978 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 731167173 69.27% 69.27% # Class of executed instruction -system.cpu.op_class::IntMult 2227672 0.21% 69.48% # Class of executed instruction -system.cpu.op_class::IntDiv 99245 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction @@ -590,126 +575,126 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Cl system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::MemRead 168640749 15.98% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 153337936 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1055583241 # Class of executed instruction +system.cpu.op_class::total 1050473844 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 10281150 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.969700 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 311526777 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10281662 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.299263 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.969700 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 10213653 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1297920552 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1297920552 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 157560037 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 157560037 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 145486469 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 145486469 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 397138 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 397138 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 335387 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 335387 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3699332 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3699332 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4002690 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4002690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 303046506 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 303046506 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 303443644 # number of overall hits -system.cpu.dcache.overall_hits::total 303443644 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5342305 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5342305 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2238545 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238545 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1309963 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1309963 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232790 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1232790 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 305057 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 305057 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 144836105 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 393576 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 334400 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 301594870 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 301988446 # number of overall hits +system.cpu.dcache.overall_hits::total 301988446 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5315823 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 7580850 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7580850 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8890813 # number of overall misses -system.cpu.dcache.overall_misses::total 8890813 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83595802503 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83595802503 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64185055523 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64185055523 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27578524507 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27578524507 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4441396750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4441396750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 147780858026 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 147780858026 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 147780858026 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 147780858026 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 162902342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 162902342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 147725014 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 147725014 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707101 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1707101 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1568177 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1568177 # 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number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2998156750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2998156750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137713909065 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 157866993339 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751194250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751194250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5618584250 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5618584250 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369778500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369778500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032700 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032700 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766206 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766206 # 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Number of tag accesses +system.cpu.icache.tags.data_accesses 907784360 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 880276980 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 880276980 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 880276980 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 880276980 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 880276980 # number of overall hits +system.cpu.icache.overall_hits::total 880276980 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13753690 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13753690 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13753690 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13753690 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13753690 # number of overall misses +system.cpu.icache.overall_misses::total 13753690 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13416.039782 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -868,208 +853,209 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13792179 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13792179 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13792179 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2831639000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2831639000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 2831639000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015352 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015352 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015352 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.198871 # 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number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 163860958817 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 163860958817 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 163860958817 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3211087000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3211087000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3211087000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 3211087000 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1330655 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65236.148872 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 27755474 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1393687 # 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Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 7588597000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 308.197317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.773838 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6468.758735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19751.242576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.585064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004703 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006420 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098705 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.301380 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996273 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 297 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62733 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2458 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5452 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54401 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004532 # 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number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4157 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4054 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 79532 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 275030 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 362773 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 509738 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 509738 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 35651 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 35651 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 534468 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7864867500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5180093000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5180093000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2585776000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10459184500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13044960500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.040274 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017101 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413482 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413482 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783297 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783297 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246111 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246111 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.038840 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.038840 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61986.826021 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63479.273949 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63225.991053 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21565.936570 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21565.936570 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.708273 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.708273 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61281.495461 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61281.495461 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.037478 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1189,62 +1175,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 21752331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21744344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7913457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339455 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 45725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 45727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2171658 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2171658 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27670608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28704497 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624113 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1013195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 58012413 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 882871956 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1164737260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2043192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3078296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2052730704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 473368 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 33145716 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.058938 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 470306 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 33030174 99.65% 99.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 33145716 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25733748000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1332000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20755677476 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14427270036 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 369197500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 628893000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40403 # Transaction distribution -system.iobus.trans_dist::ReadResp 40403 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40333 # Transaction distribution +system.iobus.trans_dist::ReadResp 40333 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1259,13 +1243,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1280,13 +1264,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1314,71 +1298,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042395169 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179037771 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115482 # number of replacements -system.iocache.tags.tagsinuse 10.457347 # Cycle average of tags in use +system.iocache.tags.replacements 115493 # number of replacements +system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153920852000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510781 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946566 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219424 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434160 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039866 # Number of tag accesses -system.iocache.tags.data_accesses 1039866 # Number of data accesses +system.iocache.tags.tag_accesses 1039965 # Number of tag accesses +system.iocache.tags.data_accesses 1039965 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses -system.iocache.demand_misses::total 8877 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses +system.iocache.demand_misses::total 8888 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8837 # number of overall misses -system.iocache.overall_misses::total 8877 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1901914612 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1907393612 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28843036786 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28843036786 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1901914612 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1907732612 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1901914612 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1907732612 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8848 # number of overall misses +system.iocache.overall_misses::total 8888 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1392,55 +1376,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 215221.750820 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 214941.808880 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270410.230125 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270410.230125 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 214907.357441 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 214907.357441 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 223600 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27526 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.123229 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3555000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1442304112 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1445859112 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23296466828 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23296466828 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3738000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1442304112 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1446042112 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3738000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1442304112 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1446042112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1454,71 +1438,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163211.962431 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 162932.061303 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218409.836758 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218409.836758 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 463332 # Transaction distribution -system.membus.trans_dist::ReadResp 463332 # Transaction distribution -system.membus.trans_dist::WriteReq 33872 # Transaction distribution -system.membus.trans_dist::WriteResp 33872 # Transaction distribution -system.membus.trans_dist::Writeback 1244337 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 618545 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 618545 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36281 # Transaction distribution +system.membus.trans_dist::ReadReq 448489 # Transaction distribution +system.membus.trans_dist::ReadResp 448489 # Transaction distribution +system.membus.trans_dist::WriteReq 33710 # Transaction distribution +system.membus.trans_dist::WriteResp 33710 # Transaction distribution +system.membus.trans_dist::Writeback 1214153 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36283 # Transaction distribution -system.membus.trans_dist::ReadExReq 533903 # Transaction distribution -system.membus.trans_dist::ReadExResp 533903 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution +system.membus.trans_dist::ReadExReq 512353 # Transaction distribution +system.membus.trans_dist::ReadExResp 512353 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4147646 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4277836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 334832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4612668 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164057632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164227968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14034624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14034624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 178262592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3539 # Total snoops (count) -system.membus.snoop_fanout::samples 2819489 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3324 # Total snoops (count) +system.membus.snoop_fanout::samples 2750930 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2819489 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2819489 # Request fanout histogram -system.membus.reqLayer0.occupancy 106085000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2750930 # Request fanout histogram +system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5679999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 17900056737 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9260714451 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186597229 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 5213927ce..f36b7859c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111151 # Number of seconds simulated -sim_ticks 51111150553500 # Number of ticks simulated -final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111153 # Number of seconds simulated +sim_ticks 51111152682000 # Number of ticks simulated +final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1151312 # Simulator instruction rate (inst/s) -host_op_rate 1352981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59753764865 # Simulator tick rate (ticks/s) -host_mem_usage 728116 # Number of bytes of host memory used -host_seconds 855.36 # Real time elapsed on the host -sim_insts 984789519 # Number of instructions simulated -sim_ops 1157289961 # Number of ops (including micro ops) simulated +host_inst_rate 1095499 # Simulator instruction rate (inst/s) +host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56869697369 # Simulator tick rate (ticks/s) +host_mem_usage 728040 # Number of bytes of host memory used +host_seconds 898.74 # Real time elapsed on the host +sim_insts 984570519 # Number of instructions simulated +sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 200576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 185152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3380276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 37995016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 209984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 187968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2175808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 37325312 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory -system.physmem.bytes_read::total 82097788 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3380276 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2175808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5556084 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103277696 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3328564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 37865864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 188288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2234176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 36967936 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory +system.physmem.bytes_read::total 81626364 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3328564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2234176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103043072 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298276 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3134 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2893 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 93224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 593685 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3281 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2937 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 33997 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 583208 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1323198 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613714 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103063652 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 92416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 591667 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2942 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 34909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 577624 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315832 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610048 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616287 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 66136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 743380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 42570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 730277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1606260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 66136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 42570 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108706 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020649 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1612621 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 65124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 740853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 723285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1597036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 65124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016058 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 66136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 743783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 42570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 730277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3627311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2016461 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 65124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 741256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 723285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3613497 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -121,45 +121,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 144982 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 144982 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 144982 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 144982 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 144734 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 144734 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 144734 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 144734 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 144734 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 108340 85.69% 85.69% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 18088 14.31% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 126428 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 107995 85.62% 85.62% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18140 14.38% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126135 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144734 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144982 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144734 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126135 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126428 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 271410 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126135 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 270869 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91965302 # DTB read hits -system.cpu0.dtb.read_misses 107321 # DTB read misses -system.cpu0.dtb.write_hits 84365950 # DTB write hits -system.cpu0.dtb.write_misses 37661 # DTB write misses +system.cpu0.dtb.read_hits 91873100 # DTB read hits +system.cpu0.dtb.read_misses 107254 # DTB read misses +system.cpu0.dtb.write_hits 84300346 # DTB write hits +system.cpu0.dtb.write_misses 37480 # DTB write misses system.cpu0.dtb.flush_tlb 51121 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 25055 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 566 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56687 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56998 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4951 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5021 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11060 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 92072623 # DTB read accesses -system.cpu0.dtb.write_accesses 84403611 # DTB write accesses +system.cpu0.dtb.perms_faults 11101 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91980354 # DTB read accesses +system.cpu0.dtb.write_accesses 84337826 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176331252 # DTB hits -system.cpu0.dtb.misses 144982 # DTB misses -system.cpu0.dtb.accesses 176476234 # DTB accesses +system.cpu0.dtb.hits 176173446 # DTB hits +system.cpu0.dtb.misses 144734 # DTB misses +system.cpu0.dtb.accesses 176318180 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -189,219 +189,219 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 70785 # Table walker walks requested -system.cpu0.itb.walker.walksLong 70785 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 70785 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 70785 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 70623 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70623 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70623 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70623 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70623 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 62159 96.07% 96.07% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2545 3.93% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 64704 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 62003 96.05% 96.05% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2552 3.95% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64555 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70785 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70623 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70623 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64704 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64704 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 135489 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 493804573 # ITB inst hits -system.cpu0.itb.inst_misses 70785 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64555 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64555 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135178 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 493558289 # ITB inst hits +system.cpu0.itb.inst_misses 70623 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51121 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 25055 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 566 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40296 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40618 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 493875358 # ITB inst accesses -system.cpu0.itb.hits 493804573 # DTB hits -system.cpu0.itb.misses 70785 # DTB misses -system.cpu0.itb.accesses 493875358 # DTB accesses -system.cpu0.numCycles 98036815347 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 493628912 # ITB inst accesses +system.cpu0.itb.hits 493558289 # DTB hits +system.cpu0.itb.misses 70623 # DTB misses +system.cpu0.itb.accesses 493628912 # DTB accesses +system.cpu0.numCycles 98036732821 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 493589418 # Number of instructions committed -system.cpu0.committedOps 579610206 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 531010156 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 454321 # Number of float alu accesses -system.cpu0.num_func_calls 28538505 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 76169999 # number of instructions that are conditional controls -system.cpu0.num_int_insts 531010156 # number of integer instructions -system.cpu0.num_fp_insts 454321 # number of float instructions -system.cpu0.num_int_register_reads 784912346 # number of times the integer registers were read -system.cpu0.num_int_register_writes 421695474 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 742936 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 362460 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132983142 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132661017 # number of times the CC registers were written -system.cpu0.num_mem_refs 176454648 # number of memory refs -system.cpu0.num_load_insts 92059270 # Number of load instructions -system.cpu0.num_store_insts 84395378 # Number of store instructions -system.cpu0.num_idle_cycles 96925999292.039536 # Number of idle cycles -system.cpu0.num_busy_cycles 1110816054.960464 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011331 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988669 # Percentage of idle cycles -system.cpu0.Branches 110347037 # Number of branches fetched +system.cpu0.committedInsts 493343054 # Number of instructions committed +system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 453665 # Number of float alu accesses +system.cpu0.num_func_calls 28504103 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76145406 # number of instructions that are conditional controls +system.cpu0.num_int_insts 530703417 # number of integer instructions +system.cpu0.num_fp_insts 453665 # number of float instructions +system.cpu0.num_int_register_reads 784985742 # number of times the integer registers were read +system.cpu0.num_int_register_writes 421507499 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 741739 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 362084 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133043946 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132723498 # number of times the CC registers were written +system.cpu0.num_mem_refs 176296730 # number of memory refs +system.cpu0.num_load_insts 91967123 # Number of load instructions +system.cpu0.num_store_insts 84329607 # Number of store instructions +system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles +system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles +system.cpu0.Branches 110281342 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 402205176 69.35% 69.35% # Class of executed instruction -system.cpu0.op_class::IntMult 1169973 0.20% 69.56% # Class of executed instruction -system.cpu0.op_class::IntDiv 50634 0.01% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 52759 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::MemRead 92059270 15.87% 85.45% # Class of executed instruction -system.cpu0.op_class::MemWrite 84395378 14.55% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 402074699 69.37% 69.37% # Class of executed instruction +system.cpu0.op_class::IntMult 1168928 0.20% 69.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 50558 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 52783 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::MemRead 91967123 15.87% 85.45% # Class of executed instruction +system.cpu0.op_class::MemWrite 84329607 14.55% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 579933190 # Class of executed instruction +system.cpu0.op_class::total 579643698 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 11615783 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 340859093 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 11616295 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.343185 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 11612141 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 340775537 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.345192 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 265.932740 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 246.066978 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.519400 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.480600 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 264.268132 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 247.731587 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.516149 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.483851 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1421517922 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1421517922 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 85766676 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 85839710 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 171606386 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79896763 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 79669373 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 159566136 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208546 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 215430 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 423976 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 146337 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 191461 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 337798 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2132895 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2177393 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 4310288 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2256573 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2306673 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4563246 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165663439 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 165509083 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 331172522 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165871985 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 165724513 # number of overall hits -system.cpu0.dcache.overall_hits::total 331596498 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3019403 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2994182 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6013585 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1302154 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1267314 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2569468 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 789306 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 795194 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1584500 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766302 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 478957 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1245259 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2250403 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2312062 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169837131 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 169833335 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 170838569 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 170839843 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 341678412 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033995 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033698 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033846 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016091 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015622 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791769 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786064 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788910 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839728 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.714722 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055034 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056170 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055610 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025423 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025101 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025262 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029891 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029609 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029750 # 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Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 267.813987 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 244.170612 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523074 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476896 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.250565 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.734034 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523927 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476043 # 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number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 985381235 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014495 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014504 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014500 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014495 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014504 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014500 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014495 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014504 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014500 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 999458178 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 999458178 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 486466334 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 484399528 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 970865862 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 486466334 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 484399528 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 970865862 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 486466334 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 484399528 # number of overall hits +system.cpu0.icache.overall_hits::total 970865862 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7156510 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 7139648 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14296158 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7156510 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 7139648 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14296158 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7156510 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 7139648 # number of overall misses +system.cpu0.icache.overall_misses::total 14296158 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 493622844 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 491539176 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 493622844 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 491539176 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 493622844 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 491539176 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014498 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014525 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014498 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014525 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014498 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014525 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,45 +505,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 143312 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 143312 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 143312 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 143312 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 143589 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143589 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143589 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143589 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143589 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 106567 85.62% 85.62% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17903 14.38% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 124470 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 106707 85.51% 85.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 18085 14.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124792 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143589 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143312 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143589 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124792 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124470 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 267782 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124792 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 268381 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 92072581 # DTB read hits -system.cpu1.dtb.read_misses 106555 # DTB read misses -system.cpu1.dtb.write_hits 83907281 # DTB write hits -system.cpu1.dtb.write_misses 36757 # DTB write misses +system.cpu1.dtb.read_hits 92120843 # DTB read hits +system.cpu1.dtb.read_misses 106565 # DTB read misses +system.cpu1.dtb.write_hits 83929435 # DTB write hits +system.cpu1.dtb.write_misses 37024 # DTB write misses system.cpu1.dtb.flush_tlb 51112 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 24716 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 573 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56101 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56458 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4637 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4753 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10591 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 92179136 # DTB read accesses -system.cpu1.dtb.write_accesses 83944038 # DTB write accesses +system.cpu1.dtb.perms_faults 10550 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 92227408 # DTB read accesses +system.cpu1.dtb.write_accesses 83966459 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175979862 # DTB hits -system.cpu1.dtb.misses 143312 # DTB misses -system.cpu1.dtb.accesses 176123174 # DTB accesses +system.cpu1.dtb.hits 176050278 # DTB hits +system.cpu1.dtb.misses 143589 # DTB misses +system.cpu1.dtb.accesses 176193867 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -573,113 +573,113 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 69790 # Table walker walks requested -system.cpu1.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 69863 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69863 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69863 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69863 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69863 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61179 95.99% 95.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2554 4.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 63733 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 61226 95.98% 95.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2567 4.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63793 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69863 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69863 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63733 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63733 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 133523 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 491448225 # ITB inst hits -system.cpu1.itb.inst_misses 69790 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63793 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63793 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 133656 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 491475383 # ITB inst hits +system.cpu1.itb.inst_misses 69863 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51112 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 24716 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 573 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40454 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40934 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 491518015 # ITB inst accesses -system.cpu1.itb.hits 491448225 # DTB hits -system.cpu1.itb.misses 69790 # DTB misses -system.cpu1.itb.accesses 491518015 # DTB accesses -system.cpu1.numCycles 97463256917 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 491545246 # ITB inst accesses +system.cpu1.itb.hits 491475383 # DTB hits +system.cpu1.itb.misses 69863 # DTB misses +system.cpu1.itb.accesses 491545246 # DTB accesses +system.cpu1.numCycles 97463064529 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 491200101 # Number of instructions committed -system.cpu1.committedOps 577679755 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 529688376 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 426452 # Number of float alu accesses -system.cpu1.num_func_calls 28536988 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 75796446 # number of instructions that are conditional controls -system.cpu1.num_int_insts 529688376 # number of integer instructions -system.cpu1.num_fp_insts 426452 # number of float instructions -system.cpu1.num_int_register_reads 779402047 # number of times the integer registers were read -system.cpu1.num_int_register_writes 420937852 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 676063 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 385332 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 131460069 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 131204494 # number of times the CC registers were written -system.cpu1.num_mem_refs 176098133 # number of memory refs -system.cpu1.num_load_insts 92164972 # Number of load instructions -system.cpu1.num_store_insts 83933161 # Number of store instructions -system.cpu1.num_idle_cycles 96357264034.410416 # Number of idle cycles -system.cpu1.num_busy_cycles 1105992882.589586 # Number of busy cycles +system.cpu1.committedInsts 491227465 # Number of instructions committed +system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 427140 # Number of float alu accesses +system.cpu1.num_func_calls 28552264 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 75795428 # number of instructions that are conditional controls +system.cpu1.num_int_insts 529752049 # number of integer instructions +system.cpu1.num_fp_insts 427140 # number of float instructions +system.cpu1.num_int_register_reads 779016428 # number of times the integer registers were read +system.cpu1.num_int_register_writes 420937292 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 677260 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 385836 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 131363112 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 131105905 # number of times the CC registers were written +system.cpu1.num_mem_refs 176168876 # number of memory refs +system.cpu1.num_load_insts 92213308 # Number of load instructions +system.cpu1.num_store_insts 83955568 # Number of store instructions +system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles +system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles -system.cpu1.Branches 109788123 # Number of branches fetched +system.cpu1.Branches 109807220 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 400601727 69.31% 69.31% # Class of executed instruction -system.cpu1.op_class::IntMult 1185429 0.21% 69.51% # Class of executed instruction -system.cpu1.op_class::IntDiv 51217 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 55063 0.01% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::MemRead 92164972 15.95% 85.48% # Class of executed instruction -system.cpu1.op_class::MemWrite 83933161 14.52% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 400561917 69.30% 69.30% # Class of executed instruction +system.cpu1.op_class::IntMult 1185819 0.21% 69.50% # Class of executed instruction +system.cpu1.op_class::IntDiv 51201 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 55039 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::MemRead 92213308 15.95% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 83955568 14.52% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 577991612 # Class of executed instruction +system.cpu1.op_class::total 578022895 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 40296 # Transaction distribution -system.iobus.trans_dist::ReadResp 40296 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 29957 # Transaction distribution +system.iobus.trans_dist::ReadReq 40246 # Transaction distribution +system.iobus.trans_dist::ReadResp 40246 # Transaction distribution +system.iobus.trans_dist::WriteReq 136515 # Transaction distribution +system.iobus.trans_dist::WriteResp 29851 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -694,13 +694,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -715,54 +715,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115460 # number of replacements +system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115463 # number of replacements system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039659 # Number of tag accesses -system.iocache.tags.data_accesses 1039659 # Number of data accesses +system.iocache.tags.tag_accesses 1039686 # Number of tag accesses +system.iocache.tags.data_accesses 1039686 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses -system.iocache.demand_misses::total 8854 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses +system.iocache.demand_misses::total 8857 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8814 # number of overall misses -system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.overall_misses::realview.ide 8817 # number of overall misses +system.iocache.overall_misses::total 8857 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -787,198 +787,197 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1726938 # number of replacements -system.l2c.tags.tagsinuse 65261.456077 # Cycle average of tags in use -system.l2c.tags.total_refs 30061688 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1789677 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 16.797270 # Average number of references to valid blocks. +system.l2c.tags.replacements 1722682 # number of replacements +system.l2c.tags.tagsinuse 65341.862498 # Cycle average of tags in use +system.l2c.tags.total_refs 30065488 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1785979 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 16.834178 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37843.446470 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.851039 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 182.256334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3658.181664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9398.442867 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 138.187628 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 187.456005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2615.769048 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11103.865022 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.577445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002781 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.055819 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.143409 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002109 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.039913 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.169432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995811 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62493 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 597 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2750 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4968 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54021 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003754 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.953568 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 291022560 # Number of tag accesses -system.l2c.tags.data_accesses 291022560 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 283104 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 147368 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7108650 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3755195 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 278245 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 144464 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 7094952 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3753176 # number of ReadReq hits -system.l2c.ReadReq_hits::total 22565154 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8923646 # number of Writeback hits -system.l2c.Writeback_hits::total 8923646 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 347701 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 349614 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 697315 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 5665 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5567 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11232 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 860452 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 824150 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1684602 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 283104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 147368 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7108650 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4615647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 278245 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 144464 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7094952 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4577326 # number of demand (read+write) hits -system.l2c.demand_hits::total 24249756 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 283104 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 147368 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7108650 # number of overall hits -system.l2c.overall_hits::cpu0.data 4615647 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 278245 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 144464 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7094952 # number of overall hits -system.l2c.overall_hits::cpu1.data 4577326 # number of overall hits -system.l2c.overall_hits::total 24249756 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3134 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2893 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 50123 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 178100 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3281 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2937 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 34010 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 166374 # number of ReadReq misses -system.l2c.ReadReq_misses::total 440852 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 418601 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 129343 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 547944 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 19998 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 20032 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 40030 # number of UpgradeReq misses +system.l2c.tags.occ_blocks::writebacks 37141.097811 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.460660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.495240 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3601.604762 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9619.799415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.654107 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 201.240500 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2659.657984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11566.852019 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.566728 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002387 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003715 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.054956 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146786 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002314 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003071 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.176496 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 276 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 63021 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 276 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54671 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.961624 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 290964090 # Number of tag accesses +system.l2c.tags.data_accesses 290964090 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 279435 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 145257 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 7107195 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3754972 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 276854 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 142760 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 7104726 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3749259 # number of ReadReq hits +system.l2c.ReadReq_hits::total 22560458 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 8921315 # number of Writeback hits +system.l2c.Writeback_hits::total 8921315 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 345123 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 349209 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 694332 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 5687 # 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miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.113608 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.020192 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004891 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.112185 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049648 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.113608 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.020192 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.112185 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049648 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -987,49 +986,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1507083 # number of writebacks -system.l2c.writebacks::total 1507083 # number of writebacks +system.l2c.writebacks::writebacks 1503417 # number of writebacks +system.l2c.writebacks::total 1503417 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 526435 # Transaction distribution -system.membus.trans_dist::ReadResp 526435 # Transaction distribution -system.membus.trans_dist::WriteReq 33712 # Transaction distribution -system.membus.trans_dist::WriteResp 33712 # Transaction distribution -system.membus.trans_dist::Writeback 1613714 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 654603 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 654603 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40598 # Transaction distribution +system.membus.trans_dist::ReadReq 526050 # Transaction distribution +system.membus.trans_dist::ReadResp 526050 # Transaction distribution +system.membus.trans_dist::WriteReq 33606 # Transaction distribution +system.membus.trans_dist::WriteResp 33606 # Transaction distribution +system.membus.trans_dist::Writeback 1610048 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 657676 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 657676 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40599 # Transaction distribution -system.membus.trans_dist::ReadExReq 833044 # Transaction distribution -system.membus.trans_dist::ReadExResp 833044 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution +system.membus.trans_dist::ReadExReq 825949 # Transaction distribution +system.membus.trans_dist::ReadExResp 825949 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5323323 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5452833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5790500 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5310719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5439911 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5777584 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 213243872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 213413240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 227630584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212730400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 212899450 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3591663 # Request fanout histogram +system.membus.snoop_fanout::samples 3583531 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3591663 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3583531 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3591663 # Request fanout histogram +system.membus.snoop_fanout::total 3583531 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1072,43 +1071,41 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 23461417 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23461417 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8923646 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1245259 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1245259 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 51262 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 23464706 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51263 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2518206 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2518206 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28661720 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32393430 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 63543360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 914587540 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314747172 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3330800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6622040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2239287552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 116335 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 36238577 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003188 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.056370 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28678566 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32383249 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 63549157 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 116338 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 36123059 99.68% 99.68% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 36238577 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index b290fab5a..3b1b184c8 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,129 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.188464 # Number of seconds simulated -sim_ticks 5188464227000 # Number of ticks simulated -final_tick 5188464227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.184750 # Number of seconds simulated +sim_ticks 5184749789500 # Number of ticks simulated +final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 671592 # Simulator instruction rate (inst/s) -host_op_rate 1294539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27056983658 # Simulator tick rate (ticks/s) -host_mem_usage 641928 # Number of bytes of host memory used -host_seconds 191.76 # Real time elapsed on the host -sim_insts 128784844 # Number of instructions simulated -sim_ops 248241672 # Number of ops (including micro ops) simulated +host_inst_rate 858252 # Simulator instruction rate (inst/s) +host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34581252938 # Simulator tick rate (ticks/s) +host_mem_usage 653812 # Number of bytes of host memory used +host_seconds 149.93 # Real time elapsed on the host +sim_insts 128677191 # Number of instructions simulated +sim_ops 248045844 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 828672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9042304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 827904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9015040 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9899712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 828672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 828672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8125568 # Number of bytes written to this memory -system.physmem.bytes_written::total 8125568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 9871616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 827904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 827904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8126080 # Number of bytes written to this memory +system.physmem.bytes_written::total 8126080 # Number of bytes written to this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141286 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140860 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154683 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126962 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126962 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 154244 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126970 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126970 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1742771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1908024 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1566083 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1566083 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1566083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1738761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1903972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1567304 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1567304 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1567304 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1742771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3474107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154683 # Number of read requests accepted -system.physmem.writeReqs 173682 # Number of write requests accepted -system.physmem.readBursts 154683 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 173682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9893504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 10954816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9899712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11115648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2485 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1609 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10173 # Per bank write bursts -system.physmem.perBankRdBursts::1 9740 # Per bank write bursts -system.physmem.perBankRdBursts::2 9593 # Per bank write bursts -system.physmem.perBankRdBursts::3 9430 # Per bank write bursts -system.physmem.perBankRdBursts::4 10001 # Per bank write bursts -system.physmem.perBankRdBursts::5 9691 # Per bank write bursts -system.physmem.perBankRdBursts::6 9399 # Per bank write bursts -system.physmem.perBankRdBursts::7 9276 # Per bank write bursts -system.physmem.perBankRdBursts::8 9154 # Per bank write bursts -system.physmem.perBankRdBursts::9 9223 # Per bank write bursts -system.physmem.perBankRdBursts::10 9471 # Per bank write bursts -system.physmem.perBankRdBursts::11 9338 # Per bank write bursts -system.physmem.perBankRdBursts::12 9899 # Per bank write bursts -system.physmem.perBankRdBursts::13 10266 # Per bank write bursts -system.physmem.perBankRdBursts::14 9992 # Per bank write bursts -system.physmem.perBankRdBursts::15 9940 # Per bank write bursts -system.physmem.perBankWrBursts::0 11451 # Per bank write bursts -system.physmem.perBankWrBursts::1 10885 # Per bank write bursts -system.physmem.perBankWrBursts::2 11361 # Per bank write bursts -system.physmem.perBankWrBursts::3 10717 # Per bank write bursts -system.physmem.perBankWrBursts::4 11001 # Per bank write bursts -system.physmem.perBankWrBursts::5 10578 # Per bank write bursts -system.physmem.perBankWrBursts::6 10603 # Per bank write bursts -system.physmem.perBankWrBursts::7 9872 # Per bank write bursts -system.physmem.perBankWrBursts::8 10400 # Per bank write bursts -system.physmem.perBankWrBursts::9 10659 # Per bank write bursts -system.physmem.perBankWrBursts::10 10851 # Per bank write bursts -system.physmem.perBankWrBursts::11 10912 # Per bank write bursts -system.physmem.perBankWrBursts::12 10837 # Per bank write bursts -system.physmem.perBankWrBursts::13 10879 # Per bank write bursts -system.physmem.perBankWrBursts::14 9964 # Per bank write bursts -system.physmem.perBankWrBursts::15 10199 # Per bank write bursts +system.physmem.bw_total::cpu.inst 159681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1738761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3471276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154244 # Number of read requests accepted +system.physmem.writeReqs 173690 # Number of write requests accepted +system.physmem.readBursts 154244 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 173690 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9865536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue +system.physmem.bytesWritten 9446080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9871616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9927 # Per bank write bursts +system.physmem.perBankRdBursts::1 9220 # Per bank write bursts +system.physmem.perBankRdBursts::2 9906 # Per bank write bursts +system.physmem.perBankRdBursts::3 9744 # Per bank write bursts +system.physmem.perBankRdBursts::4 9716 # Per bank write bursts +system.physmem.perBankRdBursts::5 9338 # Per bank write bursts +system.physmem.perBankRdBursts::6 9475 # Per bank write bursts +system.physmem.perBankRdBursts::7 9515 # Per bank write bursts +system.physmem.perBankRdBursts::8 8926 # Per bank write bursts +system.physmem.perBankRdBursts::9 9405 # Per bank write bursts +system.physmem.perBankRdBursts::10 9702 # Per bank write bursts +system.physmem.perBankRdBursts::11 9402 # Per bank write bursts +system.physmem.perBankRdBursts::12 9788 # Per bank write bursts +system.physmem.perBankRdBursts::13 10193 # Per bank write bursts +system.physmem.perBankRdBursts::14 9798 # Per bank write bursts +system.physmem.perBankRdBursts::15 10094 # Per bank write bursts +system.physmem.perBankWrBursts::0 9407 # Per bank write bursts +system.physmem.perBankWrBursts::1 8748 # Per bank write bursts +system.physmem.perBankWrBursts::2 9677 # Per bank write bursts +system.physmem.perBankWrBursts::3 9718 # Per bank write bursts +system.physmem.perBankWrBursts::4 9428 # Per bank write bursts +system.physmem.perBankWrBursts::5 9072 # Per bank write bursts +system.physmem.perBankWrBursts::6 8868 # Per bank write bursts +system.physmem.perBankWrBursts::7 9192 # Per bank write bursts +system.physmem.perBankWrBursts::8 8615 # Per bank write bursts +system.physmem.perBankWrBursts::9 8711 # Per bank write bursts +system.physmem.perBankWrBursts::10 9601 # Per bank write bursts +system.physmem.perBankWrBursts::11 9113 # Per bank write bursts +system.physmem.perBankWrBursts::12 9702 # Per bank write bursts +system.physmem.perBankWrBursts::13 9421 # Per bank write bursts +system.physmem.perBankWrBursts::14 9363 # Per bank write bursts +system.physmem.perBankWrBursts::15 8959 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5188464163500 # Total gap between requests +system.physmem.numWrRetry 68 # Number of times write queue was full causing retry +system.physmem.totGap 5184749726000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154683 # Read request sizes (log2) +system.physmem.readPktSize::6 154244 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 173682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 173690 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see @@ -156,209 +152,194 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 11279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58562 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 356.003142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.252442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.966719 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19491 33.28% 33.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13719 23.43% 56.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5713 9.76% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3485 5.95% 72.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2346 4.01% 76.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1652 2.82% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1138 1.94% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1007 1.72% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10011 17.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58562 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.303774 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 600.449814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6359 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 127 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 338.502226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.067588 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.604467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19329 33.88% 33.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13844 24.27% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5928 10.39% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3298 5.78% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2346 4.11% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.76% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1245 2.18% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 971 1.70% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8513 14.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57050 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.117303 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 658.027323 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5293 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6360 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6360 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.913365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.548238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.273775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4929 77.50% 77.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 43 0.68% 78.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 22 0.35% 78.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 287 4.51% 83.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 171 2.69% 85.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 54 0.85% 86.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 36 0.57% 87.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 31 0.49% 87.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 174 2.74% 90.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.30% 90.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 20 0.31% 90.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.14% 91.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 42 0.66% 91.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.30% 92.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.13% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 53 0.83% 93.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 89 1.40% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.17% 94.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.06% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 14 0.22% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 158 2.48% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 9 0.14% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.06% 97.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 23 0.36% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 5 0.08% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 8 0.13% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.44% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 11 0.17% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.14% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 14 0.22% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 8 0.13% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.06% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.11% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.09% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6360 # Writes before turning the bus around for reads -system.physmem.totQLat 1439298500 # Total ticks spent queuing -system.physmem.totMemAccLat 4337786000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9310.67 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.879675 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.284410 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 52.982511 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4909 92.73% 92.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 99 1.87% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 16 0.30% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 5 0.09% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 10 0.19% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 12 0.23% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 21 0.40% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 16 0.30% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 28 0.53% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 6 0.11% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 43 0.81% 97.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 33 0.62% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 9 0.17% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.08% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.06% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 9 0.17% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 7 0.13% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.06% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 17 0.32% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 15 0.28% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.04% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.08% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads +system.physmem.totQLat 1425327951 # Total ticks spent queuing +system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28060.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing -system.physmem.readRowHits 127137 # Number of row buffer hits during reads -system.physmem.writeRowHits 140055 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.81 # Row buffer hit rate for writes -system.physmem.avgGap 15800904.98 # Average gap between requests -system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 219436560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 119732250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 602963400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 560312640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 133861007610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2995654884750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3469903395930 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.773100 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4983444491000 # Time in different power states -system.physmem_0.memoryStateTime::REF 173254120000 # Time in different power states +system.physmem.avgWrQLen 22.98 # Average write queue length when enqueuing +system.physmem.readRowHits 126892 # Number of row buffer hits during reads +system.physmem.writeRowHits 117801 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes +system.physmem.avgGap 15810345.15 # Average gap between requests +system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 212315040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 115846500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.758961 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states +system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31762771500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 223292160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121836000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 602799600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 548862480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 134523004185 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2995074186000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3469979039145 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.787680 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4982479156750 # Time in different power states -system.physmem_1.memoryStateTime::REF 173254120000 # Time in different power states +system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 603002400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 476182800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 134835847830 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2992571337000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3467467313340 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.782314 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4978313509331 # Time in different power states +system.physmem_1.memoryStateTime::REF 173130100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32730835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33303731919 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10376928454 # number of cpu cycles simulated +system.cpu.numCycles 10369499579 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128784844 # Number of instructions committed -system.cpu.committedOps 248241672 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232811079 # Number of integer alu accesses +system.cpu.committedInsts 128677191 # Number of instructions committed +system.cpu.committedOps 248045844 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232619140 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2318021 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23218427 # number of instructions that are conditional controls -system.cpu.num_int_insts 232811079 # number of integer instructions +system.cpu.num_func_calls 2317433 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23196735 # number of instructions that are conditional controls +system.cpu.num_int_insts 232619140 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 436120957 # number of times the integer registers were read -system.cpu.num_int_register_writes 198544312 # number of times the integer registers were written +system.cpu.num_int_register_reads 435790308 # number of times the integer registers were read +system.cpu.num_int_register_writes 198379629 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133281322 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95783918 # number of times the CC registers were written -system.cpu.num_mem_refs 22376754 # number of memory refs -system.cpu.num_load_insts 13962110 # Number of load instructions -system.cpu.num_store_insts 8414644 # Number of store instructions -system.cpu.num_idle_cycles 9778737102.998116 # Number of idle cycles -system.cpu.num_busy_cycles 598191351.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057646 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942354 # Percentage of idle cycles -system.cpu.Branches 26395735 # Number of branches fetched -system.cpu.op_class::No_OpClass 172520 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225434965 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140546 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 123415 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 133146964 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95675934 # number of times the CC registers were written +system.cpu.num_mem_refs 22361713 # number of memory refs +system.cpu.num_load_insts 13951833 # Number of load instructions +system.cpu.num_store_insts 8409880 # Number of store instructions +system.cpu.num_idle_cycles 9769324889.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600174689.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057879 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942121 # Percentage of idle cycles +system.cpu.Branches 26373024 # Number of branches fetched +system.cpu.op_class::No_OpClass 172503 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 225254349 90.81% 90.88% # Class of executed instruction +system.cpu.op_class::IntMult 140413 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 123366 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -385,150 +366,149 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13957123 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8414644 3.39% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13946864 5.62% 96.61% # Class of executed instruction +system.cpu.op_class::MemWrite 8409880 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 248243229 # Class of executed instruction +system.cpu.op_class::total 248047391 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1624253 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996840 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20159481 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1624765 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.407629 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996840 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1622522 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996992 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20153045 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623034 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.416896 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54942250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996992 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88800329 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88800329 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12017170 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12017170 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8080876 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8080876 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59251 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59251 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20098046 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20098046 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20157297 # number of overall hits -system.cpu.dcache.overall_hits::total 20157297 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 908286 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 908286 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325792 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325792 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402501 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402501 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1234078 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1234078 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1636579 # number of overall misses -system.cpu.dcache.overall_misses::total 1636579 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12749281750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12749281750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11335230829 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11335230829 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24084512579 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24084512579 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24084512579 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24084512579 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12925456 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12925456 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8406668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8406668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461752 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461752 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21332124 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21332124 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21793876 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21793876 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070271 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070271 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038754 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038754 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871682 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871682 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057851 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057851 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075094 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075094 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14036.637964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14036.637964 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34792.845831 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34792.845831 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19516.199607 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19516.199607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14716.376404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14716.376404 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9103 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88765477 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88765477 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12014873 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12014873 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8077139 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8077139 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58853 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58853 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20092012 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20092012 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20150865 # number of overall hits +system.cpu.dcache.overall_hits::total 20150865 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906821 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906821 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 324755 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 324755 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403161 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403161 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1231576 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1231576 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1634737 # number of overall misses +system.cpu.dcache.overall_misses::total 1634737 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8401894 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 462014 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 462014 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21323588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21323588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21785602 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21785602 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070178 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070178 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038653 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038653 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872616 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872616 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057757 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057757 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075037 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.674465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.674465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.768935 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20287.768935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.372541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15284.372541 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 96 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.822917 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.301370 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1540563 # number of writebacks -system.cpu.dcache.writebacks::total 1540563 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1539491 # number of writebacks +system.cpu.dcache.writebacks::total 1539491 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9246 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9246 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9536 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9536 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9536 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9536 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907996 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 907996 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316546 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316546 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402467 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402467 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1224542 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1224542 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1627009 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1627009 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10925755250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10925755250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10200095361 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10200095361 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5340766250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5340766250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21125850611 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21125850611 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26466616861 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26466616861 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94247525000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94247525000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568413500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568413500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815938500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815938500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070249 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070249 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037654 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037654 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871609 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871609 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074654 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074654 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.823107 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.823107 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32223.106155 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32223.106155 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.072453 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.072453 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17252.042487 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17252.042487 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16267.037774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16267.037774 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9162 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9162 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9452 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9452 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9452 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9452 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906531 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906531 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315593 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315593 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403125 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 403125 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1222124 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117308860 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117308860 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586067642 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22586067642 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213365142 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28213365142 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593293500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96957757000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96957757000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037562 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037562 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872538 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872538 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057313 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057313 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074602 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.728286 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.728286 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18480.995089 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18480.995089 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.410861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.410861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -536,58 +516,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7518 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.053105 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13360 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7533 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.773530 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5157758038000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053105 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315819 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315819 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12184 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 8903 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.368527 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5156876909000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.045606 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315350 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315350 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52972 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52972 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13370 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13370 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13370 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13370 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13370 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13370 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8744 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8744 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8744 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8744 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8744 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8744 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92278000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92278000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92278000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 92278000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92278000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 92278000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22114 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22114 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22114 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22114 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22114 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22114 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395406 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395406 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395406 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395406 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395406 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395406 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.293687 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.293687 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.293687 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.293687 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 54641 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 54641 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12184 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12184 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12184 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12184 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12184 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12184 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 10091 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 10091 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 10091 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 10091 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 10091 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 10091 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 104642000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 104642000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 104642000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 104642000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 104642000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 104642000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22275 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22275 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22275 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22275 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22275 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22275 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.453019 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.453019 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.453019 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.453019 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.453019 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.453019 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10369.834506 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10369.834506 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10369.834506 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10369.834506 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,86 +576,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2885 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2885 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8744 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8744 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8744 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8744 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8744 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8744 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74789500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74789500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74789500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74789500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395406 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395406 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395406 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.236505 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3116 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3116 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 10091 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 10091 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 10091 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 10091 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 10091 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 10091 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 89505500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 89505500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 89505500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 89505500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 89505500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 89505500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.453019 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.453019 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.453019 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8869.834506 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 794079 # number of replacements -system.cpu.icache.tags.tagsinuse 510.347189 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145115978 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 794591 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.629778 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161164789250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.347189 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996772 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996772 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 794465 # number of replacements +system.cpu.icache.tags.tagsinuse 510.329327 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144962865 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 794977 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.348502 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161575846250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.329327 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996737 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996737 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146705174 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146705174 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145115978 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145115978 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145115978 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145115978 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145115978 # number of overall hits -system.cpu.icache.overall_hits::total 145115978 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 794598 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 794598 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 794598 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 794598 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 794598 # number of overall misses -system.cpu.icache.overall_misses::total 794598 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11149966366 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11149966366 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11149966366 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11149966366 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11149966366 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11149966366 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145910576 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145910576 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145910576 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145910576 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145910576 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145910576 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005446 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005446 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005446 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005446 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005446 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005446 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14032.210459 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14032.210459 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14032.210459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14032.210459 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146552833 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146552833 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144962865 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144962865 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144962865 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144962865 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144962865 # number of overall hits +system.cpu.icache.overall_hits::total 144962865 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 794984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 794984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 794984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses +system.cpu.icache.overall_misses::total 794984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253089237 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11253089237 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11253089237 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11253089237 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11253089237 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11253089237 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145757849 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145757849 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145757849 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005454 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005454 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005454 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.114112 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14155.114112 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14155.114112 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14155.114112 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -684,88 +664,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794598 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 794598 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 794598 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 794598 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 794598 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 794598 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9555900634 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9555900634 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9555900634 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9555900634 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9555900634 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9555900634 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005446 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005446 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005446 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.081911 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.081911 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794984 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 794984 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 794984 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055827763 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10055827763 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055827763 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10055827763 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055827763 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10055827763 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.094526 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.094526 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3473 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.069566 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7987 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3486 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.291165 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161163241000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069566 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191848 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191848 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7028 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 4451 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.578971 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5161420260000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.061283 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191330 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191330 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 28991 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 28991 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7985 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7985 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29974 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29974 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7029 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7029 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7987 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7987 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7987 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7987 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4339 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4339 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4339 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4339 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4339 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4339 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42562750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42562750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42562750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 42562750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42562750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 42562750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12324 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12324 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7031 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7031 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7031 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7031 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 5304 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 5304 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 5304 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 5304 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 5304 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 5304 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51550250 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51550250 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51550250 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 51550250 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51550250 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 51550250 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12333 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12333 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12326 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12326 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12326 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12326 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352077 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352077 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352020 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.352020 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352020 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.352020 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9809.345471 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9809.345471 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9809.345471 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9809.345471 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12335 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12335 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12335 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12335 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.430066 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.430066 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.429996 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.429996 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.429996 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.429996 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9719.127074 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9719.127074 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9719.127074 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9719.127074 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,177 +754,163 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 618 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 618 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4339 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4339 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4339 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4339 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4339 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4339 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33883250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33883250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33883250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33883250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33883250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33883250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352077 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352077 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352020 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352020 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7808.999770 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 759 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 759 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 5304 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 5304 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 5304 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 5304 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 5304 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 5304 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 43592750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 43592750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 43592750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 43592750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 43592750 # 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average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87360 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64748.911122 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3495788 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 152066 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 22.988623 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87146 # 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number of cycles access was blocked @@ -953,90 +919,78 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80295 # number of writebacks -system.cpu.l2cache.writebacks::total 80295 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 80303 # number of writebacks +system.cpu.l2cache.writebacks::total 80303 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12949 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28624 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41579 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8989282530 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86686810500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86686810500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088095000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088095000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021856 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019674 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807554 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807554 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361350 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361350 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016297 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62409.079793 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61796.495827 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.780995 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.780995 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56516.211650 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56516.211650 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57702.268575 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872181717 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887295749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10108406746 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411090500 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1044,59 +998,59 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2700583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2700055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13918 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13918 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1544066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314362 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314362 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5984618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7599506 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50853440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204220931 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 216256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 591552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255882179 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53190 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4026335 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011814 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108047 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1543366 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20349 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7586177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50878144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204018925 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 54167 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3978769 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47566 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4026335 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3838165000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 477000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1194331866 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3057201859 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6509250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13116250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 15136500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 230298 # Transaction distribution -system.iobus.trans_dist::ReadResp 230298 # Transaction distribution +system.iobus.trans_dist::ReadReq 228399 # Transaction distribution +system.iobus.trans_dist::ReadResp 228399 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 11006 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1653 # Transaction distribution -system.iobus.trans_dist::MessageResp 1653 # Transaction distribution +system.iobus.trans_dist::MessageReq 1652 # Transaction distribution +system.iobus.trans_dist::MessageResp 1652 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -1105,7 +1059,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 432904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1115,12 +1069,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 480916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3306 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3306 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579354 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 477136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95114 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 575554 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1129,7 +1083,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 216452 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1139,13 +1093,13 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 246738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280662 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3941856 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 244848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3278696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3940536 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1163,7 +1117,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 216453000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1181,54 +1135,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448396611 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 257203754 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 469910000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 466130000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52232002 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50194752 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1653000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47511 # number of replacements -system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use +system.iocache.tags.replacements 47502 # number of replacements +system.iocache.tags.tagsinuse 0.095966 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47518 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045849712000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5046161981000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095966 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005998 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005998 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428094 # Number of tag accesses -system.iocache.tags.data_accesses 428094 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses -system.iocache.ReadReq_misses::total 846 # number of ReadReq misses +system.iocache.tags.tag_accesses 428013 # Number of tag accesses +system.iocache.tags.data_accesses 428013 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 837 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses -system.iocache.demand_misses::total 846 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses -system.iocache.overall_misses::total 846 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144419686 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144419686 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361743923 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12361743923 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 144419686 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 144419686 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 144419686 # number of overall miss cycles -system.iocache.overall_miss_latency::total 144419686 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 837 # number of demand (read+write) misses +system.iocache.demand_misses::total 837 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 837 # number of overall misses +system.iocache.overall_misses::total 837 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132288440 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 132288440 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8590965562 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8590965562 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 132288440 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 132288440 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 132288440 # number of overall miss cycles +system.iocache.overall_miss_latency::total 132288440 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 837 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 837 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1237,40 +1191,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 170708.848700 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264592.121640 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264592.121640 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 170708.848700 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 170708.848700 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70486 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158050.704898 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183881.968365 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183881.968365 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 158050.704898 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 158050.704898 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9156 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4442 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.698340 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.674246 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100401686 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9932299927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9932299927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 100401686 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 100401686 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 837 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88419930 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6161511576 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6161511576 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 88419930 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 88419930 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1279,71 +1233,71 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 118678.115839 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212592.036109 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212592.036109 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105639.103943 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131881.669007 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131881.669007 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 624018 # Transaction distribution -system.membus.trans_dist::ReadResp 624018 # Transaction distribution -system.membus.trans_dist::WriteReq 13918 # Transaction distribution -system.membus.trans_dist::WriteResp 13918 # Transaction distribution -system.membus.trans_dist::Writeback 126962 # Transaction distribution +system.membus.trans_dist::ReadReq 617109 # Transaction distribution +system.membus.trans_dist::ReadResp 617109 # Transaction distribution +system.membus.trans_dist::WriteReq 13916 # Transaction distribution +system.membus.trans_dist::WriteResp 13916 # Transaction distribution +system.membus.trans_dist::Writeback 126970 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1627 # Transaction distribution -system.membus.trans_dist::ReadExReq 113313 # Transaction distribution -system.membus.trans_dist::ReadExResp 113313 # Transaction distribution -system.membus.trans_dist::MessageReq 1653 # Transaction distribution -system.membus.trans_dist::MessageResp 1653 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584214 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141396 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141396 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1728916 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246738 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420209 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15010240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16677187 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution +system.membus.trans_dist::ReadExReq 112993 # Transaction distribution +system.membus.trans_dist::ReadExResp 112993 # Transaction distribution +system.membus.trans_dist::MessageReq 1652 # Transaction distribution +system.membus.trans_dist::MessageResp 1652 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14982656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16628141 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22688919 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1602 # Total snoops (count) -system.membus.snoop_fanout::samples 331576 # Request fanout histogram +system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1583 # Total snoops (count) +system.membus.snoop_fanout::samples 331203 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 331576 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 331576 # Request fanout histogram -system.membus.reqLayer0.occupancy 257309000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 331203 # Request fanout histogram +system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358083500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1729903000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2619799141 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54348998 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index eedb7e6a0..f228f639d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 34993500 # Number of ticks simulated -final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000038 # Number of seconds simulated +sim_ticks 37928000 # Number of ticks simulated +final_tick 37928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25302 # Simulator instruction rate (inst/s) -host_op_rate 25300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138325772 # Simulator tick rate (ticks/s) -host_mem_usage 279800 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 174102 # Simulator instruction rate (inst/s) +host_op_rate 174036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1031016392 # Simulator tick rate (ticks/s) +host_mem_usage 293404 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 665723634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309085973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 665723634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309085973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 614216410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 285171905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 899388315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 614216410 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 614216410 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 614216410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 285171905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 899388315 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34895000 # Total gap between requests +system.physmem.totGap 37822500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 86 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,77 +186,77 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 365.511111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 232.220198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.209697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22 24.44% 24.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 24 26.67% 51.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3849750 # Total ticks spent queuing -system.physmem.totMemAccLat 13843500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.714286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 247.680361 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.730884 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19 22.62% 22.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 23.81% 46.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.57% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.38% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 7.14% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 10.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation +system.physmem.totQLat 3251500 # Total ticks spent queuing +system.physmem.totMemAccLat 13245250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7222.80 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6100.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25972.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 974.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24850.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 899.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 899.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.62 # Data bus utilization in percentage -system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.03 # Data bus utilization in percentage +system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 435 # Number of row buffer hits during reads +system.physmem.readRowHits 437 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65469.04 # Average gap between requests -system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 257040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 70961.54 # Average gap between requests +system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25985700 # Total energy per rank (pJ) -system.physmem_0.averagePower 827.438306 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15500 # Time in different power states +system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) +system.physmem_0.averagePower 825.080242 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 371750 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1677000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20164320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1173750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25645245 # Total energy per rank (pJ) -system.physmem_1.averagePower 815.785757 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2149750 # Time in different power states +system.physmem_1.actBackEnergy 20293425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1041750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25416240 # Total energy per rank (pJ) +system.physmem_1.averagePower 809.305525 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1595750 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28549750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28783000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1972 # Number of BP lookups -system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1968 # Number of BP lookups +system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1559 # Number of BTB lookups system.cpu.branchPred.BTBHits 385 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 24.695318 # BTB Hit Percentage system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 2254 # DT system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2268 # DTB accesses -system.cpu.itb.fetch_hits 2642 # ITB hits +system.cpu.itb.fetch_hits 2639 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2659 # ITB accesses +system.cpu.itb.fetch_accesses 2656 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,80 +293,80 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 69987 # number of cpu cycles simulated +system.cpu.numCycles 75856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1110 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.935469 # CPI: cycles per instruction -system.cpu.ipc 0.091446 # IPC: instructions per cycle -system.cpu.tickCycles 12616 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57371 # Total number of cycles that the object has spent stopped +system.cpu.cpi 11.852500 # CPI: cycles per instruction +system.cpu.ipc 0.084370 # IPC: instructions per cycle +system.cpu.tickCycles 12576 # Number of cycles that the object actually ticked +system.cpu.idleCycles 63280 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.036694 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 103.896503 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.036694 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025400 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.896503 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025365 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025365 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1233 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1973 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1973 # number of overall hits -system.cpu.dcache.overall_hits::total 1973 # number of overall hits +system.cpu.dcache.tags.tag_accesses 4571 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4571 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 741 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 741 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits +system.cpu.dcache.overall_hits::total 1975 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses -system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7703250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8670250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16373500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16373500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1335 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 124 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 124 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 226 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 226 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 226 # number of overall misses +system.cpu.dcache.overall_misses::total 226 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8143750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8143750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9234250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9234250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17378000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17378000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17378000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17378000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2200 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2200 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076404 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.103182 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.103182 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75522.058824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69362 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2201 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2201 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2201 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2201 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076347 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076347 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.143353 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.143353 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.102681 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.102681 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102681 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102681 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79840.686275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79840.686275 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74469.758065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74469.758065 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76893.805310 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76893.805310 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,12 +377,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 51 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 57 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5119000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5119000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12250000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12250000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12250000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12250000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071910 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7563250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7563250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5364250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5364250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12927500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071856 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071856 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70123.287671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076783 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076783 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78783.854167 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78783.854167 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73482.876712 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73482.876712 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.047314 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.733533 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.047314 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085961 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.733533 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5649 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2277 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2277 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2277 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2277 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2277 # number of overall hits -system.cpu.icache.overall_hits::total 2277 # number of overall hits +system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5643 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits +system.cpu.icache.overall_hits::total 2274 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25886500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25886500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25886500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25886500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25886500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25886500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2642 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2642 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2642 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138153 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138153 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70921.917808 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70921.917808 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70921.917808 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70921.917808 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28333250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28333250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28333250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28333250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28333250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77625.342466 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77625.342466 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77625.342466 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77625.342466 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24998500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24998500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24998500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24998500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24998500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24998500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68489.041096 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68489.041096 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27622250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27622250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27622250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75677.397260 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75677.397260 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.762820 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.387081 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 176.091079 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.671740 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.765541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.621541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005364 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001758 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007122 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses @@ -534,17 +534,17 @@ system.cpu.l2cache.demand_misses::total 533 # nu system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24623500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7033500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31657000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5044000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5044000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24623500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12077500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36701000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24623500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12077500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36701000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 34712000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5290250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5290250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27246250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12756000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40002250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27246250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12756000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40002250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 365 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 96 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) @@ -567,17 +567,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67646.978022 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73265.625000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69095.890411 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67646.978022 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71464.497041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67646.978022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71464.497041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74852.335165 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77768.229167 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75460.869565 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72469.178082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72469.178082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75051.125704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75051.125704 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,17 +597,17 @@ system.cpu.l2cache.demand_mshr_misses::total 533 system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20056500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5835000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25891500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20056500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9973000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30029500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20056500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9973000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30029500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6259250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28945500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4378250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4378250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10637500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 33323750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10637500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 33323750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses @@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55100.274725 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60781.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62324.862637 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65200.520833 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution @@ -654,10 +654,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 629250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 286000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 460 # Transaction distribution system.membus.trans_dist::ReadResp 460 # Transaction distribution @@ -678,9 +678,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4968000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.2 # Layer utilization (%) +system.membus.reqLayer0.occupancy 604000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2833250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 7064bc28f..edf4ba710 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20537500 # Number of ticks simulated -final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 22074000 # Number of ticks simulated +final_tick 22074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92569 # Simulator instruction rate (inst/s) -host_op_rate 92553 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 298254404 # Simulator tick rate (ticks/s) -host_mem_usage 293992 # Number of bytes of host memory used +host_inst_rate 94896 # Simulator instruction rate (inst/s) +host_op_rate 94876 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 328609283 # Simulator tick rate (ticks/s) +host_mem_usage 293652 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory -system.physmem.bytes_read::total 31168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory +system.physmem.bytes_read::total 31104 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975386488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 542227632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1517614121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975386488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975386488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975386488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 542227632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1517614121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 487 # Number of read requests accepted +system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory +system.physmem.num_reads::total 486 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 907492978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 501585576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1409078554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 907492978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 907492978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 907492978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 501585576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1409078554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 486 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 487 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 31168 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 31104 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 31168 # Total read bytes from the system interface side +system.physmem.bytesReadSys 31104 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,7 +51,7 @@ system.physmem.perBankRdBursts::6 1 # Pe system.physmem.perBankRdBursts::7 3 # Per bank write bursts system.physmem.perBankRdBursts::8 0 # Per bank write bursts system.physmem.perBankRdBursts::9 1 # Per bank write bursts -system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::10 22 # Per bank write bursts system.physmem.perBankRdBursts::11 25 # Per bank write bursts system.physmem.perBankRdBursts::12 14 # Per bank write bursts system.physmem.perBankRdBursts::13 120 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20412000 # Total gap between requests +system.physmem.totGap 21941500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 487 # Read request sizes (log2) +system.physmem.readPktSize::6 486 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,100 +186,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.853659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 204.819475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.253502 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28 34.15% 34.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 20.73% 54.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 10.98% 65.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 9.76% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.88% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.22% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation -system.physmem.totQLat 4742750 # Total ticks spent queuing -system.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.818416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.662840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 11.11% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 7.41% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation +system.physmem.totQLat 4363750 # Total ticks spent queuing +system.physmem.totMemAccLat 13476250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8978.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27728.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1409.08 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1409.08 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.86 # Data bus utilization in percentage -system.physmem.busUtilRead 11.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.01 # Data bus utilization in percentage +system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 390 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41913.76 # Average gap between requests -system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1755000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 45147.12 # Average gap between requests +system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10809765 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13982370 # Total energy per rank (pJ) -system.physmem_0.averagePower 881.195525 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ) +system.physmem_0.averagePower 873.750829 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 118250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1365000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10541295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 252750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13690305 # Total energy per rank (pJ) -system.physmem_1.averagePower 864.696352 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 637250 # Time in different power states +system.physmem_1.actBackEnergy 10123200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 619500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13518075 # Total energy per rank (pJ) +system.physmem_1.averagePower 853.818096 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 963500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14974750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14362750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2806 # Number of BP lookups -system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2808 # Number of BP lookups +system.cpu.branchPred.condPredicted 1660 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups -system.cpu.branchPred.BTBHits 686 # Number of BTB hits +system.cpu.branchPred.BTBHits 676 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.007576 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 398 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2085 # DTB read hits -system.cpu.dtb.read_misses 55 # DTB read misses +system.cpu.dtb.read_hits 2105 # DTB read hits +system.cpu.dtb.read_misses 56 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2140 # DTB read accesses -system.cpu.dtb.write_hits 1069 # DTB write hits +system.cpu.dtb.read_accesses 2161 # DTB read accesses +system.cpu.dtb.write_hits 1074 # DTB write hits system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1099 # DTB write accesses -system.cpu.dtb.data_hits 3154 # DTB hits -system.cpu.dtb.data_misses 85 # DTB misses +system.cpu.dtb.write_accesses 1104 # DTB write accesses +system.cpu.dtb.data_hits 3179 # DTB hits +system.cpu.dtb.data_misses 86 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3239 # DTB accesses -system.cpu.itb.fetch_hits 2196 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 3265 # DTB accesses +system.cpu.itb.fetch_hits 2195 # ITB hits +system.cpu.itb.fetch_misses 34 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2234 # ITB accesses +system.cpu.itb.fetch_accesses 2229 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,237 +292,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 41076 # number of cpu cycles simulated +system.cpu.numCycles 44149 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8744 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16221 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2806 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1081 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4165 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 8603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16272 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1074 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4302 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 801 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2196 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.137917 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547719 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 735 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2195 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 341 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.147127 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.556854 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11405 80.01% 80.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 289 2.03% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 215 1.51% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 201 1.41% 84.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 243 1.70% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 210 1.47% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 240 1.68% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 179 1.26% 91.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1273 8.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11330 79.87% 79.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 287 2.02% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 214 1.51% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 242 1.71% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 209 1.47% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 241 1.70% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 178 1.25% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1280 9.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068312 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.394902 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8821 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2387 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2410 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 194 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 14185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.063603 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.368570 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8626 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2413 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 199 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 229 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14785 # Number of instructions handled by decode +system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14877 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8987 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1032 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 429 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 8799 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1077 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 424 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2422 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 942 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14195 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 42 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 850 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10723 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17814 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17805 # Number of integer rename lookups +system.cpu.rename.UnblockCycles 1020 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14259 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 32 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 922 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10782 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17904 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17895 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6153 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6212 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 32 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 504 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2660 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1309 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.rename.skidInsts 534 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12882 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12936 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10718 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6142 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3483 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 10742 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6197 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3553 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14255 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.751877 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485144 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.757279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.490412 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10249 71.90% 71.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1278 8.97% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 900 6.31% 87.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 686 4.81% 91.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 522 3.66% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 330 2.31% 97.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 212 1.49% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.36% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10181 71.77% 71.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1265 8.92% 80.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 910 6.42% 87.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 677 4.77% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 530 3.74% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 330 2.33% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 213 1.50% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 54 0.38% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 25 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14255 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14185 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 30 20.69% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 73 50.34% 71.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 42 28.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29 19.86% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 74 50.68% 70.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 43 29.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7258 67.72% 67.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2331 21.75% 89.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1124 10.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7248 67.47% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2358 21.95% 89.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1131 10.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10718 # Type of FU issued -system.cpu.iq.rate 0.260931 # Inst issue rate -system.cpu.iq.fu_busy_cnt 145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013529 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35836 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19060 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9783 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10742 # Type of FU issued +system.cpu.iq.rate 0.243312 # Inst issue rate +system.cpu.iq.fu_busy_cnt 146 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013592 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35814 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19169 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9787 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10850 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10875 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1477 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 444 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1002 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12999 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1309 # Number of dispatched store instructions +system.cpu.iew.iewBlockCycles 1035 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13050 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 470 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10224 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2143 # Number of load instructions executed +system.cpu.iew.branchMispredicts 472 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10248 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2164 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3244 # number of memory reference insts executed -system.cpu.iew.exec_branches 1603 # Number of branches executed -system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.248904 # Inst execution rate -system.cpu.iew.wb_sent 9953 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9793 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5300 # num instructions producing a value -system.cpu.iew.wb_consumers 7279 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 3270 # number of memory reference insts executed +system.cpu.iew.exec_branches 1599 # Number of branches executed +system.cpu.iew.exec_stores 1106 # Number of stores executed +system.cpu.iew.exec_rate 0.232123 # Inst execution rate +system.cpu.iew.wb_sent 9960 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9797 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5308 # num instructions producing a value +system.cpu.iew.wb_consumers 7306 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.238412 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.728122 # average fanout of values written-back +system.cpu.iew.wb_rate 0.221908 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.726526 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6609 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6660 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489541 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.404135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12983 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.404730 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10600 81.22% 81.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1162 8.90% 90.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 501 3.84% 93.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 211 1.62% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 133 1.02% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 75 0.57% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 89 0.68% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 89 0.68% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 191 1.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10525 81.07% 81.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1166 8.98% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 505 3.89% 93.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 137 1.06% 96.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 75 0.58% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12983 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,187 +568,187 @@ system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction -system.cpu.commit.bw_lim_events 191 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25507 # The number of ROB reads -system.cpu.rob.rob_writes 27214 # The number of ROB writes -system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25491 # The number of ROB reads +system.cpu.rob.rob_writes 27316 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29964 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.446328 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.446328 # CPI: Total CPI of All Threads -system.cpu.ipc 0.155127 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.155127 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12992 # number of integer regfile reads -system.cpu.int_regfile_writes 7455 # number of integer regfile writes +system.cpu.cpi 6.928594 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.928594 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144329 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144329 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13019 # number of integer regfile reads +system.cpu.int_regfile_writes 7461 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.596270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2347 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.566474 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits -system.cpu.dcache.overall_hits::total 2314 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses -system.cpu.dcache.overall_misses::total 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 107.596270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5893 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5893 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2347 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2347 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2347 # number of overall hits +system.cpu.dcache.overall_hits::total 2347 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 157 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 157 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses +system.cpu.dcache.overall_misses::total 513 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12056250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12056250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24043225 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24043225 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36099475 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36099475 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36099475 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36099475 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078697 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078697 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.179371 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.179371 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.179371 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.179371 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76791.401274 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76791.401274 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67537.148876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67537.148876 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70369.346979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70369.346979 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2245 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.078947 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 340 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 340 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 340 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 340 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8557250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8557250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5645250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5645250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14202500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14202500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050627 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.060490 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.060490 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84725.247525 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84725.247525 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78406.250000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78406.250000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.400693 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1716 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.471338 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.464968 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.374396 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077331 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077331 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.400693 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077344 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077344 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4706 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4706 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1718 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1718 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1718 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1718 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1718 # number of overall hits -system.cpu.icache.overall_hits::total 1718 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses -system.cpu.icache.overall_misses::total 478 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31723500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31723500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31723500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31723500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31723500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31723500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2196 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2196 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2196 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2196 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2196 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2196 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217668 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.217668 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.217668 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.217668 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.217668 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.217668 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66367.154812 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66367.154812 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66367.154812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66367.154812 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4704 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4704 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1716 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1716 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1716 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1716 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1716 # number of overall hits +system.cpu.icache.overall_hits::total 1716 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses +system.cpu.icache.overall_misses::total 479 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34067500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34067500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34067500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34067500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34067500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34067500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2195 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2195 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218223 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.218223 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.218223 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.218223 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.218223 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60.312564 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.471795 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 60.723240 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006676 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4391 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4522750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11184000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29227000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11184000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29227000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20032750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7188250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 27221000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20032750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11862500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31895250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20032750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11862500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31895250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57645.367412 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65306.372549 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59528.313253 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62815.972222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62815.972222 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64002.396166 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71170.792079 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65751.207729 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64920.138889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64920.138889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 487 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 487 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 535750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 285500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 415 # Transaction distribution -system.membus.trans_dist::ReadResp 415 # Transaction distribution +system.membus.trans_dist::ReadReq 414 # Transaction distribution +system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 487 # Request fanout histogram +system.membus.snoop_fanout::samples 486 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 486 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 487 # Request fanout histogram -system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.2 # Layer utilization (%) +system.membus.snoop_fanout::total 486 # Request fanout histogram +system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2581250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index dcfebc3a2..95d6f5391 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32544000 # Number of ticks simulated -final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32544500 # Number of ticks simulated +final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 485157 # Simulator instruction rate (inst/s) -host_op_rate 484642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2465828156 # Simulator tick rate (ticks/s) -host_mem_usage 286540 # Number of bytes of host memory used +host_inst_rate 643051 # Simulator instruction rate (inst/s) +host_op_rate 642147 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3266208350 # Simulator tick rate (ticks/s) +host_mem_usage 291356 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 373 # Transaction distribution -system.membus.trans_dist::ReadResp 373 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 446 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 446 # Request fanout histogram -system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.3 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 65088 # number of cpu cycles simulated +system.cpu.numCycles 65089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 65088 # Number of busy cycles +system.cpu.num_busy_cycles 65089 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -144,15 +121,119 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits +system.cpu.dcache.overall_hits::total 1880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.dcache.overall_misses::total 168 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id @@ -171,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -189,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -209,33 +290,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy @@ -262,17 +343,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) @@ -295,17 +376,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -325,17 +406,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses @@ -347,122 +428,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits -system.cpu.dcache.overall_hits::total 1880 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses -system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -491,5 +468,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 373 # Transaction distribution +system.membus.trans_dist::ReadResp 373 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 446 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 446 # Request fanout histogram +system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 6a0f7583b..a634edee1 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18733500 # Number of ticks simulated -final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20287000 # Number of ticks simulated +final_tick 20287000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33056 # Simulator instruction rate (inst/s) -host_op_rate 33048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 239448729 # Simulator tick rate (ticks/s) -host_mem_usage 278492 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 136939 # Simulator instruction rate (inst/s) +host_op_rate 136838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1073215892 # Simulator tick rate (ticks/s) +host_mem_usage 292092 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14272 # Nu system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 761843756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 290388876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1052232631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 761843756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 761843756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 761843756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 290388876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1052232631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 703504707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 268152019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 971656726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 703504707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 703504707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 703504707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 268152019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 971656726 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 308 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18651500 # Total gap between requests +system.physmem.totGap 20198000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 43 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 421.209302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.192017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.893842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 23.26% 23.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8 18.60% 41.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 6.98% 48.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 6.98% 55.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 13.95% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 9.30% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation -system.physmem.totQLat 1952250 # Total ticks spent queuing -system.physmem.totMemAccLat 7727250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 427.707317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 281.056415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.596590 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 17.07% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation +system.physmem.totQLat 1763250 # Total ticks spent queuing +system.physmem.totMemAccLat 7538250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6338.47 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5724.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25088.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24474.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 971.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 971.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.22 # Data bus utilization in percentage -system.physmem.busUtilRead 8.22 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.59 # Data bus utilization in percentage +system.physmem.busUtilRead 7.59 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 257 # Number of row buffer hits during reads +system.physmem.readRowHits 258 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 60556.82 # Average gap between requests -system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined +system.physmem.avgGap 65577.92 # Average gap between requests +system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12765855 # Total energy per rank (pJ) -system.physmem_0.averagePower 806.306964 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 894750 # Time in different power states +system.physmem_0.actBackEnergy 10555830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12721485 # Total energy per rank (pJ) +system.physmem_0.averagePower 803.504500 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 765250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14968250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 219240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1294800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10507095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 282750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13440630 # Total energy per rank (pJ) -system.physmem_1.averagePower 848.926575 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 429000 # Time in different power states +system.physmem_1.actBackEnergy 10492560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 300000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13287405 # Total energy per rank (pJ) +system.physmem_1.averagePower 838.851326 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 458000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14897250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14875250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 793 # Number of BP lookups +system.cpu.branchPred.lookups 791 # Number of BP lookups system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 563 # Number of BTB lookups system.cpu.branchPred.BTBHits 58 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.320285 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 10.301954 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 136 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 816 # DT system.cpu.dtb.data_misses 13 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_accesses 829 # DTB accesses -system.cpu.itb.fetch_hits 974 # ITB hits +system.cpu.itb.fetch_hits 969 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 987 # ITB accesses +system.cpu.itb.fetch_accesses 982 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,29 +293,29 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 37467 # number of cpu cycles simulated +system.cpu.numCycles 40574 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 596 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 595 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.494004 # CPI: cycles per instruction -system.cpu.ipc 0.068994 # IPC: instructions per cycle -system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked -system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped +system.cpu.cpi 15.695938 # CPI: cycles per instruction +system.cpu.ipc 0.063711 # IPC: instructions per cycle +system.cpu.tickCycles 5396 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35178 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.478730 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.342007 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.478730 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011836 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.342007 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses @@ -335,14 +335,14 @@ system.cpu.dcache.demand_misses::cpu.data 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4644500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4644500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3502000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3502000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8146500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8146500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8146500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8146500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4962000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4962000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3282500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3282500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8244500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8244500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8244500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8244500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -359,14 +359,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130653 system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76139.344262 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81441.860465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78331.730769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78331.730769 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81344.262295 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81344.262295 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76337.209302 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76337.209302 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79274.038462 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79274.038462 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4310500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4310500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2079250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2079250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6389750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6389750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6389750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6389750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4628250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4628250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2009000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2009000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6637250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6637250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6637250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6637250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106784 system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74318.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77009.259259 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79797.413793 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79797.413793 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74407.407407 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74407.407407 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.465909 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 117.949271 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 746 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.345291 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.465909 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057845 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.949271 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057592 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057592 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2171 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2171 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 751 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 751 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 751 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 751 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 751 # number of overall hits -system.cpu.icache.overall_hits::total 751 # number of overall hits +system.cpu.icache.tags.tag_accesses 2161 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2161 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 746 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 746 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 746 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 746 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 746 # number of overall hits +system.cpu.icache.overall_hits::total 746 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15423500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15423500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15423500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15423500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15423500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15423500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 974 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 974 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 974 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69163.677130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69163.677130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69163.677130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69163.677130 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17117250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17117250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17117250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17117250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17117250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17117250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 969 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 969 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 969 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 969 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 969 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 969 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230134 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.230134 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.230134 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.230134 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.230134 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.230134 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76758.968610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76758.968610 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76758.968610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76758.968610 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14884500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14884500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14884500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14884500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14884500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14884500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.228953 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.228953 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.228953 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66746.636771 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66746.636771 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16684250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16684250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16684250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16684250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16684250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16684250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.230134 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.230134 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.230134 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74817.264574 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74817.264574 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 146.534478 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 145.900805 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.615214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.919264 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003620 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.086871 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.813934 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003604 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000849 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004453 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses @@ -528,17 +528,17 @@ system.cpu.l2cache.demand_misses::total 308 # nu system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14661500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4251500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2052250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2052250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14661500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6303750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20965250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14661500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6303750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20965250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16461250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4569250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21030500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1982000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1982000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16461250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6551250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23012500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16461250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6551250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23012500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 223 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 58 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) @@ -561,17 +561,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65746.636771 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73301.724138 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76009.259259 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73817.264574 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78780.172414 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74841.637011 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.407407 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.407407 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74715.909091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74715.909091 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,17 +591,17 @@ system.cpu.l2cache.demand_mshr_misses::total 308 system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11864500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3534000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1718250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11864500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5252250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11864500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5252250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13669750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3841250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17511000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1642000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1642000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13669750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5483250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19153000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13669750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5483250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19153000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -613,17 +613,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53204.035874 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60931.034483 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63638.888889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61299.327354 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66228.448276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62316.725979 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60814.814815 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60814.814815 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution @@ -649,9 +649,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 136750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 383750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 143250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution @@ -672,9 +672,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 308 # Request fanout histogram -system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2868750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 15.3 # Layer utilization (%) +system.membus.reqLayer0.occupancy 360000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 1638500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 49b58755c..165a7d5f5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11765500 # Number of ticks simulated -final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12774000 # Number of ticks simulated +final_tick 12774000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73154 # Simulator instruction rate (inst/s) -host_op_rate 73124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 360297045 # Simulator tick rate (ticks/s) -host_mem_usage 293708 # Number of bytes of host memory used +host_inst_rate 77109 # Simulator instruction rate (inst/s) +host_op_rate 77075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 412290611 # Simulator tick rate (ticks/s) +host_mem_usage 293132 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1017211338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 462368790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1479580128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1017211338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1017211338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1017211338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 462368790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1479580128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 936903084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 425865038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1362768123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 936903084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 936903084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 936903084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 425865038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1362768123 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11676000 # Total gap between requests +system.physmem.totGap 12677500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 82 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.076923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 220.895953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 363.044972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 33.33% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7 17.95% 51.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 7.69% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 7.69% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 5.13% 71.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 7.69% 79.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 2.56% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 2.56% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 15.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39 # Bytes accessed per row activation -system.physmem.totQLat 1802000 # Total ticks spent queuing -system.physmem.totMemAccLat 6902000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 8.33% 63.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 8.33% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 5.56% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation +system.physmem.totQLat 1960500 # Total ticks spent queuing +system.physmem.totMemAccLat 7060500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6625.00 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7207.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25375.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1479.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25957.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1362.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1479.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1362.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.56 # Data bus utilization in percentage -system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.65 # Data bus utilization in percentage +system.physmem.busUtilRead 10.65 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 223 # Number of row buffer hits during reads +system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42926.47 # Average gap between requests -system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined +system.physmem.avgGap 46608.46 # Average gap between requests +system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 631800 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6746115 # Total energy per rank (pJ) -system.physmem_0.averagePower 838.417275 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 206000 # Time in different power states +system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) +system.physmem_0.averagePower 832.600901 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7778000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7777500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 158760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 86625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 850200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5222340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 7073235 # Total energy per rank (pJ) -system.physmem_1.averagePower 879.072239 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 397500 # Time in different power states +system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 6961470 # Total energy per rank (pJ) +system.physmem_1.averagePower 865.181917 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 428500 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7402500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1090 # Number of BP lookups -system.cpu.branchPred.condPredicted 548 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 734 # Number of BTB lookups -system.cpu.branchPred.BTBHits 202 # Number of BTB hits +system.cpu.branchPred.lookups 1106 # Number of BP lookups +system.cpu.branchPred.condPredicted 562 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 228 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 735 # Number of BTB lookups +system.cpu.branchPred.BTBHits 214 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 27.520436 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 29.115646 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 201 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 689 # DTB read hits -system.cpu.dtb.read_misses 23 # DTB read misses +system.cpu.dtb.read_hits 705 # DTB read hits +system.cpu.dtb.read_misses 25 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 712 # DTB read accesses -system.cpu.dtb.write_hits 352 # DTB write hits -system.cpu.dtb.write_misses 18 # DTB write misses +system.cpu.dtb.read_accesses 730 # DTB read accesses +system.cpu.dtb.write_hits 367 # DTB write hits +system.cpu.dtb.write_misses 19 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 370 # DTB write accesses -system.cpu.dtb.data_hits 1041 # DTB hits -system.cpu.dtb.data_misses 41 # DTB misses +system.cpu.dtb.write_accesses 386 # DTB write accesses +system.cpu.dtb.data_hits 1072 # DTB hits +system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1082 # DTB accesses -system.cpu.itb.fetch_hits 938 # ITB hits +system.cpu.dtb.data_accesses 1116 # DTB accesses +system.cpu.itb.fetch_hits 947 # ITB hits system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 964 # ITB accesses +system.cpu.itb.fetch_accesses 973 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,236 +293,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23532 # number of cpu cycles simulated +system.cpu.numCycles 25549 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4442 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6549 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1090 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 401 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1376 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 4412 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6683 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1106 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 415 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1107 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 938 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 155 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.330561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 152 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.910863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.331734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6093 84.50% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 49 0.68% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 123 1.71% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 84 1.16% 88.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 131 1.82% 89.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 58 0.80% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 67 0.93% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 62 0.86% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 544 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6194 84.42% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 50 0.68% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 126 1.72% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 86 1.17% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 137 1.87% 89.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 59 0.80% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 69 0.94% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 62 0.85% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 554 7.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.046320 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.278302 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5244 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 757 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 975 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 55 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 180 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 156 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.043289 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.261576 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5200 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 911 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 995 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 54 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 177 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 159 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5674 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 180 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5327 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 452 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 942 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 30 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5438 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 5779 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 271 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 177 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5279 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 611 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 960 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5531 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3913 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6138 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6131 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.RenamedOperands 3966 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6270 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2145 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2198 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 115 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 883 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 455 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4685 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4768 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3891 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2057 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3966 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2151 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1238 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7211 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.539592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.280898 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7337 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.540548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.288327 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5712 79.21% 79.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 492 6.82% 86.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 353 4.90% 90.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 253 3.51% 94.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 197 2.73% 97.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 121 1.68% 98.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 52 0.72% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19 0.26% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5813 79.23% 79.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 503 6.86% 86.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 359 4.89% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 255 3.48% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 198 2.70% 97.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 113 1.54% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 62 0.85% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 21 0.29% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7337 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 18.97% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 37.93% 56.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 25 43.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2776 71.34% 71.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 739 18.99% 90.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 375 9.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2817 71.03% 71.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 757 19.09% 90.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 391 9.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3891 # Type of FU issued -system.cpu.iq.rate 0.165349 # Inst issue rate -system.cpu.iq.fu_busy_cnt 51 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013107 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15045 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6745 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3580 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3966 # Type of FU issued +system.cpu.iq.rate 0.155231 # Inst issue rate +system.cpu.iq.fu_busy_cnt 58 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014624 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15337 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6922 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3670 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3935 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4017 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 468 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 480 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 161 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 180 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 393 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5027 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 177 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 538 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5114 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 883 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 455 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 22 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 169 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 191 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3755 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 713 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 136 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 21 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 188 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3845 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 731 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 121 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 336 # number of nop insts executed -system.cpu.iew.exec_refs 1083 # number of memory reference insts executed -system.cpu.iew.exec_branches 638 # Number of branches executed -system.cpu.iew.exec_stores 370 # Number of stores executed -system.cpu.iew.exec_rate 0.159570 # Inst execution rate -system.cpu.iew.wb_sent 3650 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3586 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1711 # num instructions producing a value -system.cpu.iew.wb_consumers 2190 # num instructions consuming a value +system.cpu.iew.exec_nop 340 # number of nop insts executed +system.cpu.iew.exec_refs 1117 # number of memory reference insts executed +system.cpu.iew.exec_branches 655 # Number of branches executed +system.cpu.iew.exec_stores 386 # Number of stores executed +system.cpu.iew.exec_rate 0.150495 # Inst execution rate +system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3676 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1745 # num instructions producing a value +system.cpu.iew.wb_consumers 2262 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152388 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.781279 # average fanout of values written-back +system.cpu.iew.wb_rate 0.143880 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.771441 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2437 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 157 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6757 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.381234 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.252230 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 154 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.374800 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.238011 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5909 87.45% 87.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193 2.86% 90.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 297 4.40% 94.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 108 1.60% 96.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.07% 97.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.78% 98.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.49% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22 0.33% 98.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70 1.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6022 87.62% 87.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192 2.79% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 299 4.35% 94.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 111 1.62% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.05% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 55 0.80% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.48% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.29% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6757 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6873 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,102 +568,102 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 70 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11453 # The number of ROB reads -system.cpu.rob.rob_writes 10498 # The number of ROB writes -system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16321 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11659 # The number of ROB reads +system.cpu.rob.rob_writes 10686 # The number of ROB writes +system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18212 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.858400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.858400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.101436 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.101436 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4543 # number of integer regfile reads -system.cpu.int_regfile_writes 2774 # number of integer regfile writes +system.cpu.cpi 10.703393 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.703393 # CPI: Total CPI of All Threads +system.cpu.ipc 0.093428 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.093428 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4655 # number of integer regfile reads +system.cpu.int_regfile_writes 2832 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 46.039302 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 46.039302 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011240 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011240 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits -system.cpu.dcache.overall_hits::total 729 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses -system.cpu.dcache.overall_misses::total 198 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1969 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1969 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 525 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 525 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 218 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 218 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits +system.cpu.dcache.overall_hits::total 743 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses +system.cpu.dcache.overall_misses::total 199 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8172750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8172750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5678000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5678000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13850750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13850750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13850750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13850750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 648 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 942 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 942 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 942 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 942 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.189815 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.189815 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.258503 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.258503 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.211253 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.211253 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.211253 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.211253 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66445.121951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66445.121951 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74710.526316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74710.526316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69601.758794 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69601.758794 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -672,87 +672,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4793500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4793500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1841500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1841500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6635000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6635000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094136 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090234 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090234 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78581.967213 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78581.967213 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 92.065177 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 685 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 91.893913 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 694 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.663102 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.711230 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 92.065177 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044954 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044954 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.893913 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2063 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2063 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 685 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 685 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 685 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 685 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 685 # number of overall hits -system.cpu.icache.overall_hits::total 685 # number of overall hits +system.cpu.icache.tags.tag_accesses 2081 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2081 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 694 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 694 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 694 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 694 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 694 # number of overall hits +system.cpu.icache.overall_hits::total 694 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17329249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17329249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17329249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17329249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17329249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17329249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 938 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 938 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 938 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 938 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.269723 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.269723 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.269723 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.269723 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.269723 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.269723 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68495.055336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68495.055336 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68495.055336 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68495.055336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68495.055336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68495.055336 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18914999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18914999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18914999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18914999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18914999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18914999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 947 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 947 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 947 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 947 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.267159 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.267159 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.267159 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.267159 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.267159 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.267159 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74762.841897 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74762.841897 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74762.841897 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74762.841897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74762.841897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74762.841897 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -768,39 +768,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187 system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12893999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12893999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12893999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12893999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12893999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12893999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.199360 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.199360 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.199360 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68951.866310 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68951.866310 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68951.866310 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68951.866310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68951.866310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68951.866310 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14404999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14404999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14404999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14404999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14404999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14404999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.197466 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.197466 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.197466 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77032.080214 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77032.080214 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77032.080214 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77032.080214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77032.080214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77032.080214 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 121.503793 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 121.236486 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 92.265551 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29.238242 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002816 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000892 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 92.076745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29.159741 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000890 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003700 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 214 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses @@ -815,17 +815,17 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12706250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4451500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17157750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1694250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1694250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12706250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6145750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12706250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6145750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14216750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4732500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18949250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1816000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1816000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14216750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6548500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20765250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14216750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6548500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20765250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -848,17 +848,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67947.860963 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72975.409836 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69184.475806 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70593.750000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70593.750000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69308.823529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69308.823529 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76025.401070 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77581.967213 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76408.266129 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76025.401070 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77041.176471 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76342.830882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76025.401070 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77041.176471 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76342.830882 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -878,17 +878,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10348750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3702000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14050750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1400750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1400750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10348750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5102750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15451500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10348750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5102750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15451500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11881250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15850750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11881250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5489500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17370750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11881250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5489500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17370750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -900,17 +900,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58364.583333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58364.583333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63536.096257 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65073.770492 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63914.314516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63333.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63333.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution @@ -935,10 +935,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 318750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 139500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.trans_dist::ReadReq 248 # Transaction distribution system.membus.trans_dist::ReadResp 248 # Transaction distribution @@ -959,9 +959,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.membus.reqLayer0.occupancy 341000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1440250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 6695f502c..364bc6f05 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16524000 # Number of ticks simulated -final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16524500 # Number of ticks simulated +final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428144 # Simulator instruction rate (inst/s) -host_op_rate 427151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2733498759 # Simulator tick rate (ticks/s) -host_mem_usage 286260 # Number of bytes of host memory used +host_inst_rate 396950 # Simulator instruction rate (inst/s) +host_op_rate 396157 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2535599202 # Simulator tick rate (ticks/s) +host_mem_usage 290048 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 631324135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 317598644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 948922779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 631324135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 631324135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 218 # Transaction distribution -system.membus.trans_dist::ReadResp 218 # Transaction distribution -system.membus.trans_dist::ReadExReq 27 # Transaction distribution -system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 245 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 245 # Request fanout histogram -system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 13.3 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 631305032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 317589034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 948894066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 631305032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 631305032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 631305032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 317589034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 948894066 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 33048 # number of cpu cycles simulated +system.cpu.numCycles 33049 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 33048 # Number of busy cycles +system.cpu.num_busy_cycles 33049 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -144,15 +121,119 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 47.433873 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 47.433873 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits +system.cpu.dcache.overall_hits::total 627 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses +system.cpu.dcache.overall_misses::total 82 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4387000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4387000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4387000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4387000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 80.042941 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 80.042941 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039083 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039083 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id @@ -171,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8965000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8965000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8965000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8965000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8965000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8965500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8965500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8965500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8965500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8965500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses @@ -189,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55003.067485 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55003.067485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55003.067485 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -209,34 +290,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8721000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 8721000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8721000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 8721000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8721000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 8721000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53503.067485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53503.067485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 107.153052 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.161341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.991711 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id @@ -256,17 +337,17 @@ system.cpu.l2cache.demand_misses::total 245 # nu system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8558000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11445500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses) @@ -289,17 +370,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52502.293578 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52502.040816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,17 +400,17 @@ system.cpu.l2cache.demand_mshr_misses::total 245 system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6601500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8829000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6601500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3321000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6601500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3321000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9922500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -341,122 +422,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits -system.cpu.dcache.overall_hits::total 627 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses -system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution @@ -485,5 +462,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 218 # Transaction distribution +system.membus.trans_dist::ReadResp 218 # Transaction distribution +system.membus.trans_dist::ReadExReq 27 # Transaction distribution +system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 245 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 245 # Request fanout histogram +system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1225500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 452f74fef..a4c548b0e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27981000 # Number of ticks simulated -final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 30427500 # Number of ticks simulated +final_tick 30427500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40383 # Simulator instruction rate (inst/s) -host_op_rate 47269 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 245344554 # Simulator tick rate (ticks/s) -host_mem_usage 297404 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 90683 # Simulator instruction rate (inst/s) +host_op_rate 106136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 599001910 # Simulator tick rate (ticks/s) +host_mem_usage 308040 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 697616240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 265322898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 697616240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 265322898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 641524936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 243989812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 885514748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 641524936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 641524936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 641524936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 243989812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 885514748 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27895500 # Total gap between requests +system.physmem.totGap 30336000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,75 +187,76 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 401.269841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 285.929811 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.144791 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14 22.22% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.35% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2478000 # Total ticks spent queuing -system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2605000 # Total ticks spent queuing +system.physmem.totMemAccLat 10498750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6187.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24937.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 885.51 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 885.51 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.52 # Data bus utilization in percentage -system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.92 # Data bus utilization in percentage +system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 350 # Number of row buffer hits during reads +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 66260.10 # Average gap between requests -system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 72057.01 # Average gap between requests +system.physmem.pageHitRate 82.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1934400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ) -system.physmem_0.averagePower 856.107753 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states +system.physmem_0.totalEnergy 20029140 # Total energy per rank (pJ) +system.physmem_0.averagePower 848.018629 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ) -system.physmem_1.averagePower 786.272135 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states +system.physmem_1.actBackEnergy 15437025 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ) +system.physmem_1.averagePower 782.664197 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2527750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1926 # Number of BP lookups +system.cpu.branchPred.lookups 1927 # Number of BP lookups system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1597 # Number of BTB lookups system.cpu.branchPred.BTBHits 326 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 20.413275 # BTB Hit Percentage system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -376,44 +377,44 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 55962 # number of cpu cycles simulated +system.cpu.numCycles 60855 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4604 # Number of instructions committed system.cpu.committedOps 5390 # Number of ops (including micro ops) committed system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 12.155083 # CPI: cycles per instruction -system.cpu.ipc 0.082270 # IPC: instructions per cycle -system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked -system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.217854 # CPI: cycles per instruction +system.cpu.ipc 0.075655 # IPC: instructions per cycle +system.cpu.tickCycles 10633 # Number of cycles that the object actually ticked +system.cpu.idleCycles 50222 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.476010 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1921 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.157534 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.669090 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.476010 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021112 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021112 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1054 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4352 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4352 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1053 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1053 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1900 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1900 # number of overall hits -system.cpu.dcache.overall_hits::total 1900 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits +system.cpu.dcache.overall_hits::total 1899 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses @@ -422,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6708741 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4576500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11285241 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11285241 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1169 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7247491 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7247491 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12300991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12300991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12300991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12300991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2082 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2082 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098375 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2081 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2081 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2081 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2081 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098459 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.087416 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087416 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.087458 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087458 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087458 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087458 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63021.660870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63021.660870 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67587.862637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67587.862637 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8872758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8872758 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088109 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6561508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6561508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9740758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9740758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9740758 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9740758 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088185 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088185 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58400.563107 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66453.488372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070159 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63703.961165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63703.961165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.698962 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.698962 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078955 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078955 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4804 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits -system.cpu.icache.overall_hits::total 1919 # number of overall hits +system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4806 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits +system.cpu.icache.overall_hits::total 1920 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23941750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23941750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23941750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23941750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23941750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23941750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74353.260870 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74353.260870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74353.260870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74353.260870 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,39 +573,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23324250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23324250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23324250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23324250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23324250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23324250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72435.559006 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72435.559006 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.346707 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.764479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.217425 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001258 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.221063 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.125644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004706 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005962 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses @@ -628,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20459750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5689250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2814500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20459750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8503750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20459750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8503750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22823750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6224500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29048250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22823750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9360750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32184500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22823750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9360750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32184500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) @@ -661,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67081.147541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70237.654321 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65453.488372 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74831.967213 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76845.679012 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75254.533679 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75022.144522 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75022.144522 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,17 +698,17 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16622750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4317750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2273500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16622750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6591250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16622750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6591250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19001750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4779000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23780750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19001750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7377750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26379500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19001750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7377750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26379500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses @@ -719,17 +720,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54500.819672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59147.260274 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62300.819672 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65465.753425 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62912.037037 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution @@ -743,25 +744,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 550250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 378 # Transaction distribution system.membus.trans_dist::ReadResp 378 # Transaction distribution @@ -782,9 +781,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index bac015830..eb7b98cb0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16223000 # Number of ticks simulated -final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 17307500 # Number of ticks simulated +final_tick 17307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54860 # Simulator instruction rate (inst/s) -host_op_rate 64243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 193800024 # Simulator tick rate (ticks/s) -host_mem_usage 308908 # Number of bytes of host memory used +host_inst_rate 56147 # Simulator instruction rate (inst/s) +host_op_rate 65749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 211593476 # Simulator tick rate (ticks/s) +host_mem_usage 308560 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1020598007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447436083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1468034089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1020598007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1020598007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1020598007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447436083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1468034089 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16156000 # Total gap between requests +system.physmem.totGap 17240500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,76 +187,77 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 388.063492 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.022879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 340.382701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.40% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.29% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 84.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3126000 # Total ticks spent queuing -system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3336500 # Total ticks spent queuing +system.physmem.totMemAccLat 10780250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8404.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27154.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1468.03 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1468.03 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 12.24 # Data bus utilization in percentage -system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.47 # Data bus utilization in percentage +system.physmem.busUtilRead 11.47 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40695.21 # Average gap between requests -system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43426.95 # Average gap between requests +system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2074800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ) -system.physmem_0.averagePower 920.354334 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14395920 # Total energy per rank (pJ) +system.physmem_0.averagePower 909.263856 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ) -system.physmem_1.averagePower 810.522027 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states +system.physmem_1.actBackEnergy 10358325 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 414750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12772695 # Total energy per rank (pJ) +system.physmem_1.averagePower 806.611620 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 897000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14679500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2638 # Number of BP lookups -system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2634 # Number of BP lookups +system.cpu.branchPred.condPredicted 1633 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 783 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2098 # Number of BTB lookups +system.cpu.branchPred.BTBHits 781 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 37.225929 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 353 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -495,95 +496,95 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 32447 # number of cpu cycles simulated +system.cpu.numCycles 34616 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1011 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7775 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12462 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2634 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1134 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4935 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1009 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 273 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2063 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 315 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.090163 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.470015 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10832 80.12% 80.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 265 1.96% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 242 1.79% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 236 1.75% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 238 1.76% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 290 2.14% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 1.05% 90.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 172 1.27% 91.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1103 8.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2145 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 13520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.076092 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.360007 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6427 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4469 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2141 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 348 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12076 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2064 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups +system.cpu.rename.SquashCycles 348 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6634 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 859 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2379 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2057 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1243 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 177 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1054 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11789 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52593 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12687 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6295 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 43 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 434 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2310 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1632 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10336 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8345 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4743 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12819 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.617234 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373407 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10276 76.01% 76.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1181 8.74% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 737 5.45% 90.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 452 3.34% 93.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 368 2.72% 96.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 283 2.09% 98.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 137 1.01% 99.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 63 0.47% 99.83% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available @@ -619,113 +620,113 @@ system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5033 60.31% 60.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2011 24.10% 84.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1292 15.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8358 # Type of FU issued -system.cpu.iq.rate 0.257589 # Inst issue rate +system.cpu.iq.FU_type_0::total 8345 # Type of FU issued +system.cpu.iq.rate 0.241073 # Inst issue rate system.cpu.iq.fu_busy_cnt 169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.020252 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30336 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15016 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7551 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8471 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 694 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 348 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 819 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2310 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1632 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 251 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 363 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8047 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1910 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 11 # number of nop insts executed -system.cpu.iew.exec_refs 3148 # number of memory reference insts executed -system.cpu.iew.exec_branches 1457 # Number of branches executed -system.cpu.iew.exec_stores 1240 # Number of stores executed -system.cpu.iew.exec_rate 0.248498 # Inst execution rate -system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7601 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3572 # num instructions producing a value -system.cpu.iew.wb_consumers 6998 # num instructions consuming a value +system.cpu.iew.exec_refs 3142 # number of memory reference insts executed +system.cpu.iew.exec_branches 1452 # Number of branches executed +system.cpu.iew.exec_stores 1232 # Number of stores executed +system.cpu.iew.exec_rate 0.232465 # Inst execution rate +system.cpu.iew.wb_sent 7714 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7583 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3567 # num instructions producing a value +system.cpu.iew.wb_consumers 6985 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back +system.cpu.iew.wb_rate 0.219061 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.510666 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5019 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12644 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.425261 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.266647 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10588 83.74% 83.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 887 7.02% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 425 3.36% 94.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 213 1.68% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 117 0.93% 96.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 214 1.69% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.40% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.29% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 113 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12644 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -771,122 +772,122 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22692 # The number of ROB reads -system.cpu.rob.rob_writes 21720 # The number of ROB writes -system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22770 # The number of ROB reads +system.cpu.rob.rob_writes 21679 # The number of ROB writes +system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21096 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads -system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7945 # number of integer regfile reads -system.cpu.int_regfile_writes 4420 # number of integer regfile writes -system.cpu.fp_regfile_reads 31 # number of floating regfile reads -system.cpu.cc_regfile_reads 28734 # number of cc regfile reads -system.cpu.cc_regfile_writes 3302 # number of cc regfile writes -system.cpu.misc_regfile_reads 3189 # number of misc regfile reads +system.cpu.cpi 7.539970 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.539970 # CPI: Total CPI of All Threads +system.cpu.ipc 0.132627 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.132627 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7923 # number of integer regfile reads +system.cpu.int_regfile_writes 4408 # number of integer regfile writes +system.cpu.fp_regfile_reads 32 # number of floating regfile reads +system.cpu.cc_regfile_reads 28677 # number of cc regfile reads +system.cpu.cc_regfile_writes 3298 # number of cc regfile writes +system.cpu.misc_regfile_reads 3185 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.291293 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2178 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.917808 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.291293 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021311 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021311 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 5532 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5532 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1558 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1558 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits -system.cpu.dcache.overall_hits::total 2146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits +system.cpu.dcache.overall_hits::total 2156 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 198 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 198 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses -system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses +system.cpu.dcache.overall_misses::total 513 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12309993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12309993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22746000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22746000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35055993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35055993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35055993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35055993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2669 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2669 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2669 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2669 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.112756 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.112756 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.192207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.192207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.192207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.192207 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62171.681818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62171.681818 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72209.523810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72209.523810 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68335.269006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68335.269006 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 93 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -895,169 +896,169 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6906505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6906505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10297005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10297005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10297005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10297005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059795 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055077 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055077 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65776.238095 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65776.238095 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.998434 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1659 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.642857 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.998434 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073241 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073241 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4430 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits -system.cpu.icache.overall_hits::total 1666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses -system.cpu.icache.overall_misses::total 402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4420 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4420 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1659 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1659 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1659 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1659 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1659 # number of overall hits +system.cpu.icache.overall_hits::total 1659 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 404 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 404 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 404 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 404 # number of overall misses +system.cpu.icache.overall_misses::total 404 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28289500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28289500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28289500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28289500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28289500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28289500 # 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number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17683000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17683000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25835000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17683000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25835000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64068.840580 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67443.037975 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64819.718310 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67238.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67238.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution @@ -1162,7 +1163,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram @@ -1170,21 +1171,17 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 238495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.membus.trans_dist::ReadReq 355 # Transaction distribution system.membus.trans_dist::ReadResp 355 # Transaction distribution @@ -1205,9 +1202,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 499500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 9157ec7b3..9add0d45b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16487000 # Number of ticks simulated -final_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 17911000 # Number of ticks simulated +final_tick 17911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33036 # Simulator instruction rate (inst/s) -host_op_rate 38686 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118603969 # Simulator tick rate (ticks/s) -host_mem_usage 248576 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 61363 # Simulator instruction rate (inst/s) +host_op_rate 71855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 239307903 # Simulator tick rate (ticks/s) +host_mem_usage 305224 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 26048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408 # Number of read requests accepted +system.physmem.num_reads::total 406 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 968343476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 385908101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 96477025 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1450728603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 968343476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 968343476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 968343476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 385908101 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 96477025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1450728603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26048 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26112 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26048 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,7 +48,7 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 88 # Per bank write bursts system.physmem.perBankRdBursts::1 45 # Per bank write bursts system.physmem.perBankRdBursts::2 19 # Per bank write bursts -system.physmem.perBankRdBursts::3 45 # Per bank write bursts +system.physmem.perBankRdBursts::3 44 # Per bank write bursts system.physmem.perBankRdBursts::4 18 # Per bank write bursts system.physmem.perBankRdBursts::5 32 # Per bank write bursts system.physmem.perBankRdBursts::6 37 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16473500 # Total gap between requests +system.physmem.totGap 17897500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408 # Read request sizes (log2) +system.physmem.readPktSize::6 407 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,13 +94,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3192729 # Total ticks spent queuing -system.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 57 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 433.403509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 294.791776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.955773 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6 10.53% 10.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 33.33% 43.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 15.79% 59.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 5.26% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.51% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.51% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 7.02% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 5.26% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 15.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57 # Bytes accessed per row activation +system.physmem.totQLat 3190492 # Total ticks spent queuing +system.physmem.totMemAccLat 10821742 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7839.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26589.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1454.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1454.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 12.37 # Data bus utilization in percentage -system.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.36 # Data bus utilization in percentage +system.physmem.busUtilRead 11.36 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 342 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40376.23 # Average gap between requests -system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43974.20 # Average gap between requests +system.physmem.pageHitRate 84.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 279720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 152625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2035800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) -system.physmem_0.averagePower 918.403600 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states +system.physmem_0.totalEnergy 14310600 # Total energy per rank (pJ) +system.physmem_0.averagePower 903.874941 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) -system.physmem_1.averagePower 817.101847 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states +system.physmem_1.actBackEnergy 10067625 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 668250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12747240 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.131217 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1195750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14254250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2361 # Number of BP lookups -system.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 1410 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups -system.cpu.branchPred.BTBHits 473 # Number of BTB hits +system.cpu.branchPred.BTBHits 476 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 54.649828 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 288 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 55 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32975 # number of cpu cycles simulated +system.cpu.numCycles 35823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11322 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6115 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11289 # Number of instructions fetch has processed system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.predictedBranches 764 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8098 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3848 # Number of cache lines fetched +system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3842 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.850771 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.201734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9287 59.94% 59.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2459 15.87% 75.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 519 3.35% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3228 20.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5035 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst +system.cpu.fetch.rateDist::total 15493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065907 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.315133 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5846 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4125 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5024 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 366 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 330 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9854 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1610 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 366 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1543 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1980 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 4080 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.UnblockCycles 608 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8873 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 401 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups +system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 531 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9263 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40182 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9732 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 3769 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 320 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 309 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8340 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7157 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7136 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7753 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.460595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.852056 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11312 73.01% 73.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1923 12.41% 85.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1608 10.38% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 603 3.89% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 47 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15493 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 427 29.53% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.43% 61.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 550 38.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4484 62.84% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1571 22.02% 84.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1073 15.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7157 # Type of FU issued -system.cpu.iq.rate 0.217043 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1432 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7136 # Type of FU issued +system.cpu.iq.rate 0.199202 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1446 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.202635 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31353 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11164 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8554 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 9 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 756 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 315 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 366 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 898 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1783 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1253 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 291 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 6736 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1394 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 400 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2417 # number of memory reference insts executed -system.cpu.iew.exec_branches 1277 # Number of branches executed -system.cpu.iew.exec_stores 1017 # Number of stores executed -system.cpu.iew.exec_rate 0.205034 # Inst execution rate -system.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6587 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2990 # num instructions producing a value -system.cpu.iew.wb_consumers 5391 # num instructions consuming a value +system.cpu.iew.exec_refs 2409 # number of memory reference insts executed +system.cpu.iew.exec_branches 1271 # Number of branches executed +system.cpu.iew.exec_stores 1015 # Number of stores executed +system.cpu.iew.exec_rate 0.188036 # Inst execution rate +system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2981 # num instructions producing a value +system.cpu.iew.wb_consumers 5387 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.199757 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183290 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553369 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2567 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.359593 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.005851 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12307 82.30% 82.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1380 9.23% 91.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 605 4.05% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 296 1.98% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 166 1.11% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.52% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.31% 99.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 31 0.21% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14953 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,122 +654,122 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22003 # The number of ROB reads -system.cpu.rob.rob_writes 16441 # The number of ROB writes -system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22696 # The number of ROB reads +system.cpu.rob.rob_writes 16433 # The number of ROB writes +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20330 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.182531 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139227 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6737 # number of integer regfile reads -system.cpu.int_regfile_writes 3765 # number of integer regfile writes +system.cpu.cpi 7.802875 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.802875 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128158 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128158 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6713 # number of integer regfile reads +system.cpu.int_regfile_writes 3756 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24010 # number of cc regfile reads -system.cpu.cc_regfile_writes 2910 # number of cc regfile writes -system.cpu.misc_regfile_reads 2599 # number of misc regfile reads +system.cpu.cc_regfile_reads 23929 # number of cc regfile reads +system.cpu.cc_regfile_writes 2892 # number of cc regfile writes +system.cpu.misc_regfile_reads 2595 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.129086 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1902 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.394366 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.129086 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164315 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164315 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4676 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4674 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4674 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1160 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1160 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1876 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1876 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1876 # number of overall hits -system.cpu.dcache.overall_hits::total 1876 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 178 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 178 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits +system.cpu.dcache.overall_hits::total 1882 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 369 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses -system.cpu.dcache.overall_misses::total 369 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15700992 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 362 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 362 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 362 # number of overall misses +system.cpu.dcache.overall_misses::total 362 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9785742 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9785742 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7277250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7277250 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17062992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17062992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17062992 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17062992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1331 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133634 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133634 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2244 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.128475 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.128475 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164365 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164365 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164365 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164365 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50483.101124 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42550.113821 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42550.113821 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.161319 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.161319 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.161319 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.161319 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57226.561404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57226.561404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38100.785340 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38100.785340 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47135.337017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47135.337017 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 646 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 717 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 35.888889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39.833333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 226 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 226 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 226 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -778,120 +778,120 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5294755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5294755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7484255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7484255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7484255 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7484255 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076577 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6008755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6008755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2367750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2367750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8376505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8376505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8376505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8376505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076634 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063697 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063697 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51909.362745 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51909.362745 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53402.439024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53402.439024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063725 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063725 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58909.362745 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58909.362745 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 138.060100 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3485 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.773649 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.043653 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3477 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.786441 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 138.060100 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.269649 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.269649 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 254 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.496094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7990 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7990 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3485 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3485 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3485 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3485 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3485 # number of overall hits -system.cpu.icache.overall_hits::total 3485 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses -system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19725741 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19725741 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19725741 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19725741 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19725741 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19725741 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3847 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3847 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3847 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3847 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094099 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094099 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094099 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094099 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094099 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094099 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54490.997238 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54490.997238 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54490.997238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54490.997238 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7642 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 18 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 94 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 136.043653 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.265710 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.265710 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 7977 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7977 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3477 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3477 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3477 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3477 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3477 # number of overall hits +system.cpu.icache.overall_hits::total 3477 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22425741 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22425741 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22425741 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22425741 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22425741 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22425741 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3841 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3841 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3841 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3841 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094767 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094767 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094767 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094767 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094767 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094767 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61609.178571 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61609.178571 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61609.178571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61609.178571 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8359 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 92 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 81.297872 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 90.858696 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -900,28 +900,28 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002767 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011910 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.367812 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 44.986812 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.164899 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008445 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002746 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000559 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011750 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021301 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7446 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7446 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021240 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7429 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7429 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits @@ -933,61 +933,61 @@ system.cpu.l2cache.demand_hits::total 53 # nu system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 30 # number of overall hits system.cpu.l2cache.overall_hits::total 53 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # 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number of overall misses -system.cpu.l2cache.overall_misses::total 387 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16599750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5077250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21677000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2079500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2079500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16599750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7156750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23756500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16599750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7156750 # 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number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922559 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922297 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813725 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.894737 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.894472 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922559 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922297 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.879545 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922559 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.879271 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.879545 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60583.029197 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61171.686747 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 60719.887955 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69316.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69316.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61386.304910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61386.304910 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66739.010989 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69659.638554 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67419.943820 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75125 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75125 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68018.782383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68018.782383 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1005,118 +1005,116 @@ system.cpu.l2cache.demand_mshr_hits::total 6 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 381 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14211250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4185750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18397000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1810701 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14211250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6019250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20230500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14211250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6019250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22041201 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15861750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4830750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20692500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1641917 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2002750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2002750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15861750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6833500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22695250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15861750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6833500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24337167 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879397 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.865909 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58315.257353 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61932.692308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59121.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34206.604167 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66758.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66758.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59724.342105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56862.539720 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 591 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 67 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 64 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.127237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 439 87.28% 87.28% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 64 12.72% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 378 # Transaction distribution -system.membus.trans_dist::ReadResp 376 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 496749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 377 # Transaction distribution +system.membus.trans_dist::ReadResp 375 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 408 # Request fanout histogram +system.membus.snoop_fanout::samples 407 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 407 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 408 # Request fanout histogram -system.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 23.0 # Layer utilization (%) +system.membus.snoop_fanout::total 407 # Request fanout histogram +system.membus.reqLayer0.occupancy 509443 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2140258 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 72322cbec..cdd01be72 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 396323 # Simulator instruction rate (inst/s) -host_op_rate 463654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232084410 # Simulator tick rate (ticks/s) -host_mem_usage 298640 # Number of bytes of host memory used +host_inst_rate 771856 # Simulator instruction rate (inst/s) +host_op_rate 901727 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 450886881 # Simulator tick rate (ticks/s) +host_mem_usage 297796 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -347,18 +347,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index b8c713e42..bd1ca933f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 370272 # Simulator instruction rate (inst/s) -host_op_rate 433210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216878622 # Simulator tick rate (ticks/s) -host_mem_usage 297624 # Number of bytes of host memory used +host_inst_rate 801222 # Simulator instruction rate (inst/s) +host_op_rate 936270 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 468120222 # Simulator tick rate (ticks/s) +host_mem_usage 297024 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -228,18 +228,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 872a056d2..8573f117d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25815000 # Number of ticks simulated -final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25815500 # Number of ticks simulated +final_tick 25815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 376930 # Simulator instruction rate (inst/s) -host_op_rate 439541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2127142386 # Simulator tick rate (ticks/s) -host_mem_usage 307352 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 263675 # Simulator instruction rate (inst/s) +host_op_rate 307555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1488783160 # Simulator tick rate (ticks/s) +host_mem_usage 306760 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557815224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309897347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 867712570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557815224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557815224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 557804420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309891344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 867695764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557804420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557804420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557804420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309891344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 867695764 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51630 # number of cpu cycles simulated +system.cpu.numCycles 51631 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51629.998000 # Number of busy cycles +system.cpu.num_busy_cycles 51630.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.895840 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.895840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.421612 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.428477 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055873 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055873 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.421612 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12588000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12588000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12588000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12588000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12588000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses @@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52232.365145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52232.365145 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,33 +384,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12106000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12106000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.844437 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.835531 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.714938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.129500 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.708552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.126979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy @@ -440,17 +440,17 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11705000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15969000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11705000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18205000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11705000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18205000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,17 +503,17 @@ system.cpu.l2cache.demand_mshr_misses::total 350 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses @@ -525,17 +525,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution @@ -549,19 +549,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) @@ -588,9 +586,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index ca0260a61..f65d4ed09 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21163500 # Number of ticks simulated -final_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 22762000 # Number of ticks simulated +final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81533 # Simulator instruction rate (inst/s) -host_op_rate 81515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 345921870 # Simulator tick rate (ticks/s) -host_mem_usage 292088 # Number of bytes of host memory used +host_inst_rate 85129 # Simulator instruction rate (inst/s) +host_op_rate 85110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 388456550 # Simulator tick rate (ticks/s) +host_mem_usage 291584 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21120 # Nu system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 471 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 997944574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 426394500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1424339074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 997944574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 997944574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 997944574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 426394500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1424339074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 927862227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 396450224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1324312451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 927862227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 927862227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 927862227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 396450224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1324312451 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 471 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21083000 # Total gap between requests +system.physmem.totGap 22674500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.095238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.705030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 253.763121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 34 32.38% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17 16.19% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 9.52% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 0.95% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 1.90% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.90% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation -system.physmem.totQLat 5392000 # Total ticks spent queuing -system.physmem.totMemAccLat 14223250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.184943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 253.583818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28 26.92% 26.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 35 33.65% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 18 17.31% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 9.62% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 2.88% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation +system.physmem.totQLat 5218000 # Total ticks spent queuing +system.physmem.totMemAccLat 14049250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11447.98 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11078.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30197.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1424.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29828.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1324.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1424.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1324.31 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.13 # Data bus utilization in percentage -system.physmem.busUtilRead 11.13 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.35 # Data bus utilization in percentage +system.physmem.busUtilRead 10.35 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44762.21 # Average gap between requests +system.physmem.avgGap 48141.19 # Average gap between requests system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 136080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 74250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 569400 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 491400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9948780 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 772500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12518130 # Total energy per rank (pJ) -system.physmem_0.averagePower 790.660351 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2505250 # Time in different power states +system.physmem_0.actBackEnergy 9465705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1196250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12369120 # Total energy per rank (pJ) +system.physmem_0.averagePower 781.248697 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1950500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14081250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13375750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 536760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 292875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2285400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14949930 # Total energy per rank (pJ) -system.physmem_1.averagePower 944.255803 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 97000 # Time in different power states +system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14812845 # Total energy per rank (pJ) +system.physmem_1.averagePower 935.597347 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 284750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15222250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2146 # Number of BP lookups -system.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1636 # Number of BTB lookups -system.cpu.branchPred.BTBHits 528 # Number of BTB hits +system.cpu.branchPred.lookups 2110 # Number of BP lookups +system.cpu.branchPred.condPredicted 1371 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 423 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1629 # Number of BTB lookups +system.cpu.branchPred.BTBHits 525 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.228361 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -279,236 +279,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 42328 # number of cpu cycles simulated +system.cpu.numCycles 45525 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8967 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13064 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2146 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 812 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4771 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing -system.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2037 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14376 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.207470 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8934 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12895 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2110 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 805 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing +system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.890662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.186824 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11035 76.76% 76.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1473 10.25% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 126 0.88% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 160 1.11% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 283 1.97% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 90 0.63% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 137 0.95% 92.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 121 0.84% 93.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 951 6.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11164 77.11% 77.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1470 10.15% 87.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 124 0.86% 88.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 160 1.11% 89.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 283 1.95% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 94 0.65% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 128 0.88% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 113 0.78% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 942 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14376 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050699 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.308637 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8549 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2515 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2791 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.046348 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.283251 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8487 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2706 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2773 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 391 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12032 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11880 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8711 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 391 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8645 # Number of cycles rename is idle system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 944 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2743 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1081 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11544 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 1002 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2724 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1214 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11398 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 196 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6963 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13345 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 231 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 967 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13412 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13162 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3681 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3597 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 298 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 290 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2474 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1168 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8940 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8280 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3419 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1838 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8204 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1790 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14376 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.575960 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.325471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14478 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.566653 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.310295 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11054 76.89% 76.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1314 9.14% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 739 5.14% 91.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 413 2.87% 94.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 345 2.40% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 315 2.19% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 104 0.72% 99.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 66 0.46% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11167 77.13% 77.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.08% 86.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 734 5.07% 91.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 423 2.92% 94.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 344 2.38% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 310 2.14% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 102 0.70% 99.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 57 0.39% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 27 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14478 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.06% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 131 66.50% 70.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58 29.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 4.59% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 129 65.82% 70.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58 29.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4865 58.76% 58.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2336 28.21% 87.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1072 12.95% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4822 58.78% 58.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2303 28.07% 86.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1072 13.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8280 # Type of FU issued -system.cpu.iq.rate 0.195615 # Inst issue rate -system.cpu.iq.fu_busy_cnt 197 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023792 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31160 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12466 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7466 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8204 # Type of FU issued +system.cpu.iq.rate 0.180209 # Inst issue rate +system.cpu.iq.fu_busy_cnt 196 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023891 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31113 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12267 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7408 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8398 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1342 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 267 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 475 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10593 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 391 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 464 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10483 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2474 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1168 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7957 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2194 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 323 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 348 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 444 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7875 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1553 # number of nop insts executed -system.cpu.iew.exec_refs 3252 # number of memory reference insts executed -system.cpu.iew.exec_branches 1379 # Number of branches executed -system.cpu.iew.exec_stores 1058 # Number of stores executed -system.cpu.iew.exec_rate 0.187984 # Inst execution rate -system.cpu.iew.wb_sent 7571 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7468 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2915 # num instructions producing a value -system.cpu.iew.wb_consumers 4399 # num instructions consuming a value +system.cpu.iew.exec_nop 1532 # number of nop insts executed +system.cpu.iew.exec_refs 3217 # number of memory reference insts executed +system.cpu.iew.exec_branches 1365 # Number of branches executed +system.cpu.iew.exec_stores 1057 # Number of stores executed +system.cpu.iew.exec_rate 0.172982 # Inst execution rate +system.cpu.iew.wb_sent 7509 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7410 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2869 # num instructions producing a value +system.cpu.iew.wb_consumers 4254 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.176432 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.662651 # average fanout of values written-back +system.cpu.iew.wb_rate 0.162768 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674424 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4969 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4860 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 386 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13506 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.416333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.231872 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.412758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.228786 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11333 83.91% 83.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 875 6.48% 90.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 515 3.81% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 250 1.85% 96.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 149 1.10% 97.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 177 1.31% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 64 0.47% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11456 84.09% 84.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 871 6.39% 90.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 510 3.74% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 252 1.85% 96.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.09% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 178 1.31% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.48% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.29% 99.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103 0.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13506 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13623 # Number of insts commited each cycle system.cpu.commit.committedInsts 5623 # Number of instructions committed system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -554,102 +554,102 @@ system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5623 # Class of committed instruction -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23983 # The number of ROB reads -system.cpu.rob.rob_writes 22065 # The number of ROB writes -system.cpu.timesIdled 275 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27952 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23990 # The number of ROB reads +system.cpu.rob.rob_writes 21831 # The number of ROB writes +system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31047 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4986 # Number of Instructions Simulated system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.489370 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.489370 # CPI: Total CPI of All Threads -system.cpu.ipc 0.117794 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.117794 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10767 # number of integer regfile reads -system.cpu.int_regfile_writes 5247 # number of integer regfile writes +system.cpu.cpi 9.130566 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.130566 # CPI: Total CPI of All Threads +system.cpu.ipc 0.109522 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.109522 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10639 # number of integer regfile reads +system.cpu.int_regfile_writes 5201 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 164 # number of misc regfile reads +system.cpu.misc_regfile_reads 165 # number of misc regfile reads system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.212769 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2418 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.148936 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.212769 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022269 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits -system.cpu.dcache.overall_hits::total 2445 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses -system.cpu.dcache.overall_misses::total 515 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 5997 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5997 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1862 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1862 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits +system.cpu.dcache.overall_hits::total 2418 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses +system.cpu.dcache.overall_misses::total 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12038750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12038750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24387249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24387249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36425999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36425999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36425999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36425999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2027 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2027 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081401 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081401 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.174180 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174180 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174180 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174180 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72962.121212 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72962.121212 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70687.678261 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70687.678261 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71423.527451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71423.527451 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -658,82 +658,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7833500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7833500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4084749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4084749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11918249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11918249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11918249 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11918249 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044894 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044894 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048156 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048156 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81694.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81694.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.205778 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.783784 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.735736 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.344728 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077317 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.205778 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077249 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077249 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4407 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4407 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1593 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1593 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1593 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1593 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1593 # number of overall hits -system.cpu.icache.overall_hits::total 1593 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 444 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 444 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 444 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 444 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 444 # number of overall misses -system.cpu.icache.overall_misses::total 444 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30764750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30764750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30764750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30764750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30764750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30764750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2037 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2037 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2037 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2037 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2037 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2037 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217968 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.217968 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.217968 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.217968 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.217968 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.217968 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69289.977477 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69289.977477 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69289.977477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69289.977477 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4385 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4385 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits +system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 449 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 449 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 449 # number of overall misses +system.cpu.icache.overall_misses::total 449 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34003000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34003000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34003000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34003000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34003000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34003000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221619 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.221619 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.221619 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.221619 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.221619 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.221619 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75730.512249 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75730.512249 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75730.512249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75730.512249 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -742,51 +742,51 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 111 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 111 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 111 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 111 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 111 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 333 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 333 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 333 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24043500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24043500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24043500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24043500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24043500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24043500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163476 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.163476 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.163476 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72202.702703 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72202.702703 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26389500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26389500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26389500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26389500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26389500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26389500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164363 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.164363 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.164363 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79247.747748 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79247.747748 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.292920 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 218.150435 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.335208 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.957712 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004893 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.168468 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.981967 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004888 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006662 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006657 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses @@ -807,17 +807,17 @@ system.cpu.l2cache.demand_misses::total 471 # nu system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 471 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23680500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30897000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3981500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3981500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23680500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11198000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34878500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23680500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11198000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34878500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26025000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7738500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 33763500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4034000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4034000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26025000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11772500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37797500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26025000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11772500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37797500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) @@ -840,17 +840,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993671 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71759.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79302.197802 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73389.548694 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79630 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79630 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74052.016985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74052.016985 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78863.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85038.461538 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80198.337292 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80680 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80680 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80249.469214 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80249.469214 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,17 +870,17 @@ system.cpu.l2cache.demand_mshr_misses::total 471 system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19517000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6096000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25613000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3359000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3359000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19517000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9455000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28972000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19517000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9455000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28972000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21894000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6598000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28492000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3411000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3411000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21894000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10009000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31903000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21894000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10009000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31903000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses @@ -892,17 +892,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59142.424242 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66989.010989 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60838.479810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67180 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67180 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66345.454545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72505.494505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67676.959620 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68220 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68220 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution @@ -927,11 +927,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 569000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 233500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 421 # Transaction distribution system.membus.trans_dist::ReadResp 421 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution @@ -951,9 +951,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 598000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2506000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 84d2a731d..4f23a8939 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30902000 # Number of ticks simulated -final_tick 30902000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30902500 # Number of ticks simulated +final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104539 # Simulator instruction rate (inst/s) -host_op_rate 104503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 574021463 # Simulator tick rate (ticks/s) -host_mem_usage 276192 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 544856 # Simulator instruction rate (inst/s) +host_op_rate 544118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2985748792 # Simulator tick rate (ticks/s) +host_mem_usage 288768 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 430 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 606821565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283735681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 890557245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 606821565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 606821565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 606821565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283735681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 890557245 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 380 # Transaction distribution -system.membus.trans_dist::ReadResp 380 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 430 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430 # Request fanout histogram -system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3870000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.5 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -72,7 +49,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 61804 # number of cpu cycles simulated +system.cpu.numCycles 61805 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -91,7 +68,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61804 # Number of busy cycles +system.cpu.num_busy_cycles 61805 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -130,15 +107,119 @@ system.cpu.op_class::MemWrite 902 16.04% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 86.155054 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 86.155054 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits +system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses +system.cpu.dcache.overall_misses::total 137 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2675000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2675000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7329500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 129.108186 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 129.101534 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 129.108186 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063041 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063041 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 129.101534 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id @@ -157,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 295 # n system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses system.cpu.icache.overall_misses::total 295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16141000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16141000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16141000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16141000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16141000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses @@ -175,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54715.254237 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54715.254237 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54715.254237 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54715.254237 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -195,33 +276,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 295 system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15551000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15551000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15551000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15551000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15551000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15551000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15699000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15699000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52715.254237 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52715.254237 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.724070 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 183.714965 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005263 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.264551 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.459518 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.257719 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 53.457246 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005607 # Average percentage of cache occupancy @@ -248,17 +329,17 @@ system.cpu.l2cache.demand_misses::total 430 # nu system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19760000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2600000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2600000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15236000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7124000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22360000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15236000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7124000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22360000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15383000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4567500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19950500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 382 # number of ReadReq accesses(hits+misses) @@ -281,17 +362,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995370 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -311,17 +392,17 @@ system.cpu.l2cache.demand_mshr_misses::total 430 system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17200000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11866500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3523500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15390000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2025000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2025000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11866500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17415000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11866500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17415000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994764 # mshr miss rate for ReadReq accesses @@ -333,122 +414,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.158665 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.158665 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021035 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021035 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses -system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2650000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2650000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7261000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7261000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7261000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7261000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -477,5 +454,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 442500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 380 # Transaction distribution +system.membus.trans_dist::ReadResp 380 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 430 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 430 # Request fanout histogram +system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index e81ca8aaa..c9ca56107 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18857500 # Number of ticks simulated -final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20101000 # Number of ticks simulated +final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101158 # Simulator instruction rate (inst/s) -host_op_rate 101133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 329193143 # Simulator tick rate (ticks/s) -host_mem_usage 288984 # Number of bytes of host memory used +host_inst_rate 103196 # Simulator instruction rate (inst/s) +host_op_rate 103171 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 357968408 # Simulator tick rate (ticks/s) +host_mem_usage 289136 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1092084971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 321576041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1413661012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1092084971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1092084971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1092084971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 321576041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1413661012 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18724000 # Total gap between requests +system.physmem.totGap 19960500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,77 +186,77 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation -system.physmem.totQLat 3635500 # Total ticks spent queuing -system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.606609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.258819 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.28% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 5.13% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation +system.physmem.totQLat 3861750 # Total ticks spent queuing +system.physmem.totMemAccLat 12186750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8697.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27447.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1413.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1413.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.77 # Data bus utilization in percentage -system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.04 # Data bus utilization in percentage +system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 356 # Number of row buffer hits during reads +system.physmem.readRowHits 357 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42171.17 # Average gap between requests -system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 476280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 259875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2644200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 44956.08 # Average gap between requests +system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 15222495 # Total energy per rank (pJ) -system.physmem_0.averagePower 961.471341 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 15068130 # Total energy per rank (pJ) +system.physmem_0.averagePower 951.571203 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15316250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8055810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2433000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 11899695 # Total energy per rank (pJ) -system.physmem_1.averagePower 751.599242 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4725250 # Time in different power states +system.physmem_1.actBackEnergy 7470990 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2946000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11827875 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.063003 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 6720750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 11341250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 10486250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2332 # Number of BP lookups -system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2330 # Number of BP lookups +system.cpu.branchPred.condPredicted 1881 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups -system.cpu.branchPred.BTBHits 661 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1929 # Number of BTB lookups +system.cpu.branchPred.BTBHits 660 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 34.214619 # BTB Hit Percentage system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -279,237 +279,237 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 37716 # number of cpu cycles simulated +system.cpu.numCycles 40203 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 865 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 7819 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13492 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2330 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4287 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.061192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.469867 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10352 81.42% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.49% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 216 1.70% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 152 1.20% 85.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 247 1.94% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 139 1.09% 88.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.99% 90.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 114 0.90% 91.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1052 8.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 12714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.057956 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.335597 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7212 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3139 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1951 # Number of cycles decode is running system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst +system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7370 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 627 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11201 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1508 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9631 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18130 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18104 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4633 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 361 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 9105 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4184 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3348 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.716140 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.547958 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9591 75.44% 75.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 944 7.42% 82.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 633 4.98% 87.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 463 3.64% 91.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 426 3.35% 94.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 301 2.37% 97.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 240 1.89% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 71 0.56% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 45 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12714 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 4.37% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 122 48.41% 52.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 119 47.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5535 60.79% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1910 20.98% 81.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1658 18.21% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9108 # Type of FU issued -system.cpu.iq.rate 0.241489 # Inst issue rate -system.cpu.iq.fu_busy_cnt 251 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9105 # Type of FU issued +system.cpu.iq.rate 0.226476 # Inst issue rate +system.cpu.iq.fu_busy_cnt 252 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.027677 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31189 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14543 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8271 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9323 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 870 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 62 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8701 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3329 # number of memory reference insts executed -system.cpu.iew.exec_branches 1361 # Number of branches executed +system.cpu.iew.exec_refs 3330 # number of memory reference insts executed +system.cpu.iew.exec_branches 1363 # Number of branches executed system.cpu.iew.exec_stores 1554 # Number of stores executed -system.cpu.iew.exec_rate 0.230724 # Inst execution rate -system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8300 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4483 # num instructions producing a value -system.cpu.iew.wb_consumers 7102 # num instructions consuming a value +system.cpu.iew.exec_rate 0.216427 # Inst execution rate +system.cpu.iew.wb_sent 8428 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4465 # num instructions producing a value +system.cpu.iew.wb_consumers 7078 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back +system.cpu.iew.wb_rate 0.206403 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.630828 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11592 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.499655 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.370216 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12003 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.482546 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.346027 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9439 81.43% 81.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 839 7.24% 88.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 524 4.52% 93.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9841 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 848 7.06% 89.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 522 4.35% 93.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 225 1.87% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.40% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 120 1.00% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.92% 98.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 59 0.49% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 110 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11592 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12003 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,61 +555,61 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21860 # The number of ROB reads -system.cpu.rob.rob_writes 21470 # The number of ROB writes -system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22278 # The number of ROB reads +system.cpu.rob.rob_writes 21482 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27489 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads -system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13744 # number of integer regfile reads -system.cpu.int_regfile_writes 7176 # number of integer regfile writes +system.cpu.cpi 6.941126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.941126 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13740 # number of integer regfile reads +system.cpu.int_regfile_writes 7173 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.843132 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.313725 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.843132 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015587 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015587 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits -system.cpu.dcache.overall_hits::total 2261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses -system.cpu.dcache.overall_misses::total 452 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 1556 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1556 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 720 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 720 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits +system.cpu.dcache.overall_hits::total 2276 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 326 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 326 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8814500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8814500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30924496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30924496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39738996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39738996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39738996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39738996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -618,38 +618,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2713 # system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066587 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.066587 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.311663 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.311663 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.161076 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.161076 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.161076 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.161076 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79409.909910 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79409.909910 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94860.417178 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 94860.417178 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 90935.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 90935.917620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.833333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 335 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 335 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -658,14 +658,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4529750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4529750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4417498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4417498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8947248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8947248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8947248 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -674,119 +674,119 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82359.090909 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82359.090909 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93989.319149 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93989.319149 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 169.362964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.362964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082697 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082697 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4007 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits -system.cpu.icache.overall_hits::total 1391 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 438 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1829 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1829 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1829 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239475 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.239475 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.239475 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.239475 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.239475 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.239475 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 404 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4005 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4005 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1389 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1389 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1389 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1389 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1389 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1828 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1828 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1828 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1828 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1828 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1828 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.240153 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.240153 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.240153 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.240153 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.240153 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.240153 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72836.560364 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72836.560364 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72836.560364 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72836.560364 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 80.800000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 97.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 89 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 89 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 89 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 89 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24058750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24058750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24058750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24058750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24058750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24058750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191361 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.191361 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.191361 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68739.285714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26127750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26127750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26127750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26127750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26127750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26127750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191466 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.191466 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.191466 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74650.714286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74650.714286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 201.157905 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.954316 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 169.317933 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.839972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005167 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000972 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.205981 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.748335 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006102 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses @@ -810,17 +810,17 @@ system.cpu.l2cache.demand_misses::total 445 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 445 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23649250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4137750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27787000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3745250 # 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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68747.819767 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76625 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69816.582915 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79686.170213 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79686.170213 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70858.988764 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70858.988764 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74753.633721 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82662.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75826.633166 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92925.531915 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92925.531915 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77632.584270 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77632.584270 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -873,17 +873,17 @@ system.cpu.l2cache.demand_mshr_misses::total 445 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19325250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3474750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19325250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6644000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25969250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19325250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6644000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25969250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21441250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25233500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3785500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3785500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21441250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7577750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29019000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21441250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7577750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29019000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses @@ -895,17 +895,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56178.052326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64347.222222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57286.432161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67430.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67430.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.215116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70226.851852 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63400.753769 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80542.553191 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80542.553191 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution @@ -930,11 +930,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 589250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 165750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 397 # Transaction distribution system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -954,9 +954,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 555000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2341000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 52edf7aee..f6a7e842c 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27800000 # Number of ticks simulated -final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27800500 # Number of ticks simulated +final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 583909 # Simulator instruction rate (inst/s) -host_op_rate 583078 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3038583452 # Simulator tick rate (ticks/s) -host_mem_usage 285748 # Number of bytes of host memory used +host_inst_rate 510787 # Simulator instruction rate (inst/s) +host_op_rate 510102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2658808340 # Simulator tick rate (ticks/s) +host_mem_usage 289420 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,40 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 308 # Transaction distribution -system.membus.trans_dist::ReadResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 389 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 389 # Request fanout histogram -system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.6 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 55600 # number of cpu cycles simulated +system.cpu.numCycles 55601 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 55599.998000 # Number of busy cycles +system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -112,15 +89,119 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.114550 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.114550 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits +system.cpu.dcache.overall_hits::total 1253 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses +system.cpu.dcache.overall_misses::total 135 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4333500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4333500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7180500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7180500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7180500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7180500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 117.036911 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.036911 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057147 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057147 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id @@ -139,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -157,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -177,33 +258,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13666000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13666000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13666000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13666000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13666000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13666000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 142.175920 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.512586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.663334 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy @@ -233,17 +314,17 @@ system.cpu.l2cache.demand_misses::total 389 # nu system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 389 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13388000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) @@ -266,17 +347,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992347 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -296,17 +377,17 @@ system.cpu.l2cache.demand_mshr_misses::total 389 system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10327500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12474000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3280500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3280500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10327500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15754500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10327500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15754500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses @@ -318,122 +399,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits -system.cpu.dcache.overall_hits::total 1253 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -462,5 +439,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 385500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 308 # Transaction distribution +system.membus.trans_dist::ReadResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 389 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 389 # Request fanout histogram +system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 3b4d7b677..8ea066b3b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19678000 # Number of ticks simulated -final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 21143500 # Number of ticks simulated +final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46918 # Simulator instruction rate (inst/s) -host_op_rate 84992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171550123 # Simulator tick rate (ticks/s) -host_mem_usage 309548 # Number of bytes of host memory used +host_inst_rate 49814 # Simulator instruction rate (inst/s) +host_op_rate 90238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 195722405 # Simulator tick rate (ticks/s) +host_mem_usage 309420 # Number of bytes of host memory used host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 832407123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 426797834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1259204957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 832407123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 832407123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 832407123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 426797834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1259204957 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19629500 # Total gap between requests +system.physmem.totGap 21095000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,308 +186,310 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation -system.physmem.totQLat 4347000 # Total ticks spent queuing -system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.440000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.807528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 245.488436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35 35.00% 35.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 31 31.00% 66.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 16.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 6.00% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.00% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.00% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.00% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4 4.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100 # Bytes accessed per row activation +system.physmem.totQLat 5105750 # Total ticks spent queuing +system.physmem.totMemAccLat 12924500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12244.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30994.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1262.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1262.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.60 # Data bus utilization in percentage -system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.86 # Data bus utilization in percentage +system.physmem.busUtilRead 9.86 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 309 # Number of row buffer hits during reads +system.physmem.readRowHits 307 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47073.14 # Average gap between requests -system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1084200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 50587.53 # Average gap between requests +system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 936000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13267770 # Total energy per rank (pJ) -system.physmem_0.averagePower 837.810088 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13058475 # Total energy per rank (pJ) +system.physmem_0.averagePower 824.789199 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15318250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 446040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 243375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 438480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 239250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1513200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10701180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 112500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14088015 # Total energy per rank (pJ) -system.physmem_1.averagePower 889.816201 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 882750 # Time in different power states +system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14021205 # Total energy per rank (pJ) +system.physmem_1.averagePower 885.596400 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 102500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15230750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15223750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 3423 # Number of BP lookups -system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2544 # Number of BTB lookups -system.cpu.branchPred.BTBHits 864 # Number of BTB hits +system.cpu.branchPred.lookups 3414 # Number of BP lookups +system.cpu.branchPred.condPredicted 3414 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 534 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2533 # Number of BTB lookups +system.cpu.branchPred.BTBHits 863 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 34.070272 # BTB Hit Percentage system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39357 # number of cpu cycles simulated +system.cpu.numCycles 42288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15528 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1203 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 12291 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15496 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3414 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1201 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1161 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 2168 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.270406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.764504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2164 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 23838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.164108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.669642 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17618 80.47% 80.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 236 1.08% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 174 0.79% 82.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 259 1.18% 83.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 208 0.95% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 227 1.04% 85.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 339 1.55% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 205 0.94% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2627 12.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19573 82.11% 82.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 236 0.99% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 173 0.73% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 257 1.08% 84.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 208 0.87% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 228 0.96% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 337 1.41% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 205 0.86% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2621 11.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 456 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 601 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25755 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 601 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 10929 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2194 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 719 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3480 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3970 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24219 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 23838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080732 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.366440 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12043 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7408 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3332 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 455 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 600 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25703 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 600 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 12311 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2293 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 795 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3474 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4365 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24179 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 3820 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 27591 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 59364 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 33558 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 4214 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 27545 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 59275 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 33508 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16528 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16482 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1503 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2441 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1612 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 1507 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1611 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21443 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 21419 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17897 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11052 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16525 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17882 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11007 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16508 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21893 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.817476 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.773238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 23838 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.750147 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.712551 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16772 76.61% 76.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1137 5.19% 81.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 886 4.05% 85.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 636 2.91% 88.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 833 3.80% 92.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 590 2.69% 95.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 599 2.74% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 316 1.44% 99.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124 0.57% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18713 78.50% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1142 4.79% 83.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 888 3.73% 87.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 640 2.68% 89.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 832 3.49% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 584 2.45% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 601 2.52% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 314 1.32% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124 0.52% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 23838 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 174 77.68% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 31 13.84% 91.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 8.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 173 77.58% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 31 13.90% 91.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19 8.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14382 80.36% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2122 11.86% 92.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14368 80.35% 80.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2121 11.86% 92.29% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17897 # Type of FU issued -system.cpu.iq.rate 0.454735 # Inst issue rate -system.cpu.iq.fu_busy_cnt 224 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32531 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16370 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17882 # Type of FU issued +system.cpu.iq.rate 0.422862 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012471 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 59896 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32462 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16353 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18114 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18098 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 228 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 235 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1388 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1385 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 677 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 676 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 601 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1862 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21468 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 600 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1925 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 68 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21444 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2441 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1612 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1611 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16926 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1969 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 971 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 694 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16910 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1967 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 972 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3251 # number of memory reference insts executed -system.cpu.iew.exec_branches 1662 # Number of branches executed +system.cpu.iew.exec_refs 3249 # number of memory reference insts executed +system.cpu.iew.exec_branches 1660 # Number of branches executed system.cpu.iew.exec_stores 1282 # Number of stores executed -system.cpu.iew.exec_rate 0.430063 # Inst execution rate -system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16374 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11006 # num instructions producing a value -system.cpu.iew.wb_consumers 17135 # num instructions consuming a value +system.cpu.iew.exec_rate 0.399877 # Inst execution rate +system.cpu.iew.wb_sent 16617 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16357 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10994 # num instructions producing a value +system.cpu.iew.wb_consumers 17115 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back +system.cpu.iew.wb_rate 0.386800 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642361 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11696 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 19924 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.394281 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 587 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 21874 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.445598 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.336765 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16684 83.74% 83.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1003 5.03% 88.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 547 2.75% 91.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 737 3.70% 95.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 365 1.83% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 142 0.71% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 113 0.57% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.37% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 260 1.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18628 85.16% 85.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1010 4.62% 89.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 544 2.49% 92.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 738 3.37% 95.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 369 1.69% 97.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 141 0.64% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 113 0.52% 98.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.33% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 259 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 19924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 21874 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -533,102 +535,102 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 41131 # The number of ROB reads -system.cpu.rob.rob_writes 44929 # The number of ROB writes -system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 43058 # The number of ROB reads +system.cpu.rob.rob_writes 44876 # The number of ROB writes +system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18450 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21341 # number of integer regfile reads -system.cpu.int_regfile_writes 13120 # number of integer regfile writes +system.cpu.cpi 7.860223 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.860223 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127223 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127223 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21328 # number of integer regfile reads +system.cpu.int_regfile_writes 13105 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8069 # number of cc regfile reads +system.cpu.cc_regfile_reads 8064 # number of cc regfile reads system.cpu.cc_regfile_writes 5036 # number of cc regfile writes -system.cpu.misc_regfile_reads 7491 # number of misc regfile reads +system.cpu.misc_regfile_reads 7485 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 82.313704 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.971631 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.313704 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020096 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020096 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5351 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5351 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1536 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits -system.cpu.dcache.overall_hits::total 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits +system.cpu.dcache.overall_hits::total 2393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 134 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 134 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses -system.cpu.dcache.overall_misses::total 214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 212 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 212 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 212 # number of overall misses +system.cpu.dcache.overall_misses::total 212 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11119000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11119000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6761250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6761250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17880250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17880250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17880250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17880250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1670 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2605 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2605 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2605 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2605 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080240 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080240 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.081382 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081382 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081382 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081382 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82977.611940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 82977.611940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86682.692308 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 86682.692308 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84340.801887 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84340.801887 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 70 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 70 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 70 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses @@ -637,82 +639,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5695500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5695500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6612750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6612750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12308250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12308250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12308250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12308250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038323 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038323 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88992.187500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88992.187500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84778.846154 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84778.846154 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 131.513084 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1796 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.507246 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 131.513084 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064215 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064215 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4612 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4612 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits -system.cpu.icache.overall_hits::total 1800 # number of overall hits +system.cpu.icache.tags.tag_accesses 4604 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4604 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1796 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1796 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1796 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1796 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1796 # number of overall hits +system.cpu.icache.overall_hits::total 1796 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2168 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2168 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2168 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169742 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.169742 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.169742 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69449.048913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69449.048913 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28645750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28645750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28645750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28645750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28645750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28645750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2164 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2164 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2164 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2164 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.170055 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.170055 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.170055 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.170055 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.170055 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.170055 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77841.711957 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77841.711957 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77841.711957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77841.711957 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -733,39 +735,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 276 system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20059000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20059000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20059000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20059000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20059000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21933250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21933250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21933250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21933250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21933250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21933250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127542 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.127542 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.127542 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79468.297101 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79468.297101 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.220102 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.168393 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.613484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.606618 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004017 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.574096 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.594298 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000964 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004980 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses @@ -786,17 +788,17 @@ system.cpu.l2cache.demand_misses::total 417 # nu system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19772500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4946500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24719000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5510000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5510000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19772500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10456500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30229000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19772500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10456500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30229000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21646250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5632500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27278750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6534750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6534750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21646250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12167250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33813500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21646250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12167250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33813500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) @@ -819,17 +821,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997608 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71900 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71900 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71900 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78713.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88007.812500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80468.289086 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83778.846154 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83778.846154 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81087.529976 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81087.529976 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -849,17 +851,17 @@ system.cpu.l2cache.demand_mshr_misses::total 417 system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16317000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4156000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20473000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16317000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25012500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16317000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25012500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18201750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23038750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18201750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10392250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28594000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18201750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10392250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28594000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses @@ -871,17 +873,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66188.181818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75578.125000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67960.914454 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71221.153846 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71221.153846 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution @@ -908,11 +910,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 3 # system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 471250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.trans_dist::ReadReq 339 # Transaction distribution system.membus.trans_dist::ReadResp 338 # Transaction distribution system.membus.trans_dist::ReadExReq 78 # Transaction distribution @@ -934,9 +936,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2222500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index b43d6cab2..2ef89d07d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28358000 # Number of ticks simulated -final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 28358500 # Number of ticks simulated +final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 307468 # Simulator instruction rate (inst/s) -host_op_rate 556583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618053178 # Simulator tick rate (ticks/s) -host_mem_usage 302528 # Number of bytes of host memory used +host_inst_rate 312703 # Simulator instruction rate (inst/s) +host_op_rate 566020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1645401799 # Simulator tick rate (ticks/s) +host_mem_usage 307640 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -21,43 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 282 # Transaction distribution -system.membus.trans_dist::ReadResp 282 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 361 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 361 # Request fanout histogram -system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.5 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56716 # number of cpu cycles simulated +system.cpu.numCycles 56717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -78,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56715.998000 # Number of busy cycles +system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -117,15 +92,119 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 80.793450 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 80.793450 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits +system.cpu.dcache.overall_hits::total 1854 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.dcache.overall_misses::total 134 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7169000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.544338 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.544338 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id @@ -144,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -162,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12156500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12156500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12156500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12156500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12156500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12156500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53317.982456 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53317.982456 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 134.026823 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.552484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.474338 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy @@ -235,17 +314,17 @@ system.cpu.l2cache.demand_misses::total 361 # nu system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11918000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14805500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) @@ -268,17 +347,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.773050 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.385042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -298,17 +377,17 @@ system.cpu.l2cache.demand_mshr_misses::total 361 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9193500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11421000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3199500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3199500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9193500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14620500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9193500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14620500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses @@ -320,122 +399,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits -system.cpu.dcache.overall_hits::total 1854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -466,5 +441,30 @@ system.cpu.toL2Bus.respLayer0.occupancy 342000 # La system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 282 # Transaction distribution +system.membus.trans_dist::ReadResp 282 # Transaction distribution +system.membus.trans_dist::ReadExReq 79 # Transaction distribution +system.membus.trans_dist::ReadExResp 79 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 361 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 361 # Request fanout histogram +system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 752a25834..3794759d9 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 23754500 # Number of ticks simulated -final_tick 23754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 25499500 # Number of ticks simulated +final_tick 25499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70868 # Simulator instruction rate (inst/s) -host_op_rate 70863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132078042 # Simulator tick rate (ticks/s) -host_mem_usage 294344 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 83845 # Simulator instruction rate (inst/s) +host_op_rate 83838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167736694 # Simulator tick rate (ticks/s) +host_mem_usage 294000 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 40064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22336 # Number of bytes read from this memory -system.physmem.bytes_read::total 62400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40064 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 626 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 349 # Number of read requests responded to by this memory -system.physmem.num_reads::total 975 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1686585700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 940284999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2626870698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1686585700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1686585700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1686585700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 940284999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2626870698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 975 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 40704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22144 # Number of bytes read from this memory +system.physmem.bytes_read::total 62848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40704 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 346 # Number of read requests responded to by this memory +system.physmem.num_reads::total 982 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1596266593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 868409184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2464675778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1596266593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1596266593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1596266593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 868409184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2464675778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 982 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 982 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 62848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side +system.physmem.bytesReadSys 62848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 83 # Per bank write bursts -system.physmem.perBankRdBursts::1 151 # Per bank write bursts -system.physmem.perBankRdBursts::2 78 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 152 # Per bank write bursts +system.physmem.perBankRdBursts::2 79 # Per bank write bursts +system.physmem.perBankRdBursts::3 59 # Per bank write bursts system.physmem.perBankRdBursts::4 88 # Per bank write bursts system.physmem.perBankRdBursts::5 49 # Per bank write bursts -system.physmem.perBankRdBursts::6 32 # Per bank write bursts -system.physmem.perBankRdBursts::7 49 # Per bank write bursts -system.physmem.perBankRdBursts::8 41 # Per bank write bursts -system.physmem.perBankRdBursts::9 38 # Per bank write bursts +system.physmem.perBankRdBursts::6 33 # Per bank write bursts +system.physmem.perBankRdBursts::7 50 # Per bank write bursts +system.physmem.perBankRdBursts::8 42 # Per bank write bursts +system.physmem.perBankRdBursts::9 39 # Per bank write bursts system.physmem.perBankRdBursts::10 30 # Per bank write bursts system.physmem.perBankRdBursts::11 34 # Per bank write bursts system.physmem.perBankRdBursts::12 15 # Per bank write bursts -system.physmem.perBankRdBursts::13 122 # Per bank write bursts -system.physmem.perBankRdBursts::14 70 # Per bank write bursts +system.physmem.perBankRdBursts::13 120 # Per bank write bursts +system.physmem.perBankRdBursts::14 69 # Per bank write bursts system.physmem.perBankRdBursts::15 37 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23342000 # Total gap between requests +system.physmem.totGap 25359500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 975 # Read request sizes (log2) +system.physmem.readPktSize::6 982 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,13 +90,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.431280 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.087836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.004628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 69 32.70% 32.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 56 26.54% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25 11.85% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 14 6.64% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15 7.11% 84.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9 4.27% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 1.90% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 2.84% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13 6.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation -system.physmem.totQLat 12504500 # Total ticks spent queuing -system.physmem.totMemAccLat 30785750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12825.13 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.836364 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.810990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.156672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 81 36.82% 36.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 62 28.18% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 22 10.00% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 14 6.36% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10 4.55% 85.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 3.18% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 2.73% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 2.73% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 12 5.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 220 # Bytes accessed per row activation +system.physmem.totQLat 12877000 # Total ticks spent queuing +system.physmem.totMemAccLat 31289500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13113.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31575.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2626.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31863.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2464.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2626.87 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2464.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 20.52 # Data bus utilization in percentage -system.physmem.busUtilRead 20.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 19.26 # Data bus utilization in percentage +system.physmem.busUtilRead 19.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 763 # Number of row buffer hits during reads +system.physmem.readRowHits 752 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23940.51 # Average gap between requests -system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4578600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 25824.34 # Average gap between requests +system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 929880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 507375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4547400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16058610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 84750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 23638155 # Total energy per rank (pJ) -system.physmem_0.averagePower 1000.821593 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 44000 # Time in different power states +system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 23657895 # Total energy per rank (pJ) +system.physmem_0.averagePower 1001.657370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 688500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22808500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 695520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 379500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3018600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2652000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15908130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 21744180 # Total energy per rank (pJ) -system.physmem_1.averagePower 920.632125 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 278750 # Time in different power states +system.physmem_1.actBackEnergy 15503715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 591000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21359100 # Total energy per rank (pJ) +system.physmem_1.averagePower 903.085461 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 888000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22573750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21996000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 7608 # Number of BP lookups -system.cpu.branchPred.condPredicted 4258 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5646 # Number of BTB lookups -system.cpu.branchPred.BTBHits 865 # Number of BTB hits +system.cpu.branchPred.lookups 7477 # Number of BP lookups +system.cpu.branchPred.condPredicted 4177 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1616 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5400 # Number of BTB lookups +system.cpu.branchPred.BTBHits 850 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 15.320581 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1051 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 15.740741 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1012 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 5192 # DTB read hits -system.cpu.dtb.read_misses 102 # DTB read misses +system.cpu.dtb.read_hits 4911 # DTB read hits +system.cpu.dtb.read_misses 100 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 5294 # DTB read accesses -system.cpu.dtb.write_hits 2108 # DTB write hits -system.cpu.dtb.write_misses 66 # DTB write misses +system.cpu.dtb.read_accesses 5011 # DTB read accesses +system.cpu.dtb.write_hits 2106 # DTB write hits +system.cpu.dtb.write_misses 69 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2174 # DTB write accesses -system.cpu.dtb.data_hits 7300 # DTB hits -system.cpu.dtb.data_misses 168 # DTB misses +system.cpu.dtb.write_accesses 2175 # DTB write accesses +system.cpu.dtb.data_hits 7017 # DTB hits +system.cpu.dtb.data_misses 169 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 7468 # DTB accesses -system.cpu.itb.fetch_hits 5663 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 7186 # DTB accesses +system.cpu.itb.fetch_hits 5467 # ITB hits +system.cpu.itb.fetch_misses 60 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5720 # ITB accesses +system.cpu.itb.fetch_accesses 5527 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -294,318 +294,318 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 47510 # number of cpu cycles simulated +system.cpu.numCycles 51000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1451 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 41889 # Number of instructions fetch has processed -system.cpu.fetch.Branches 7608 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1916 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 11137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 1416 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 41297 # Number of instructions fetch has processed +system.cpu.fetch.Branches 7477 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1862 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 10878 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1697 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 556 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5663 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 846 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28570 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.466188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.843743 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 471 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5467 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 803 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 27699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.490920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.868697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21551 75.43% 75.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 541 1.89% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 402 1.41% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 607 2.12% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 545 1.91% 82.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 439 1.54% 84.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 542 1.90% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 448 1.57% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3495 12.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20832 75.21% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 522 1.88% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 376 1.36% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 569 2.05% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 524 1.89% 82.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 456 1.65% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 499 1.80% 85.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 422 1.52% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3499 12.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28570 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.160135 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.881688 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37575 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12018 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5449 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 625 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1245 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 719 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 33794 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 947 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1245 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38261 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5449 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1170 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5378 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5409 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 31549 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 73 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 407 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 458 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4425 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 23766 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 39316 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 39298 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 27699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.146608 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.809745 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36892 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11130 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5276 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 643 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1210 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 704 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 509 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 33151 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 887 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1210 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37566 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5376 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1365 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5257 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4377 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30969 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 361 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 477 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3380 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 23374 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 38597 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 38579 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14626 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 56 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2199 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3120 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1520 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 14234 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 57 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2267 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2994 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1466 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2933 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1394 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2948 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1410 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28021 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 23357 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14239 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8472 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28570 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.817536 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.542788 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 27629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 22900 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13893 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8231 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 27699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.826745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.538980 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19963 69.87% 69.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2657 9.30% 79.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1959 6.86% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1384 4.84% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1325 4.64% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 682 2.39% 97.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 348 1.22% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 184 0.64% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 68 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19213 69.36% 69.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2603 9.40% 78.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1960 7.08% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1418 5.12% 90.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1237 4.47% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 696 2.51% 97.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 372 1.34% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 137 0.49% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 63 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28570 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 27699 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 22 6.04% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 263 72.25% 78.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79 21.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 27 8.23% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 211 64.33% 72.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 90 27.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7749 65.04% 65.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2973 24.95% 90.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1188 9.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7493 65.81% 65.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2715 23.85% 89.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1173 10.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11915 # Type of FU issued +system.cpu.iq.FU_type_0::total 11386 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7559 66.06% 66.08% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.09% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2735 23.90% 90.01% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1143 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7630 66.27% 66.28% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.29% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2714 23.57% 89.88% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1165 10.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11442 # Type of FU issued -system.cpu.iq.FU_type::total 23357 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.491623 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 183 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 181 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 364 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.007835 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.007749 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.015584 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75737 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 42325 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 11514 # Type of FU issued +system.cpu.iq.FU_type::total 22900 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.449020 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 160 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 168 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 328 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.006987 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.007336 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.014323 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 73887 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 41585 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20089 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 23695 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 23202 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 87 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1937 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 655 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1811 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 601 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 426 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 281 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 75 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1750 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 529 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1765 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 545 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 346 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 256 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1245 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2860 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 601 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 28216 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 318 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6053 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2914 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 571 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1210 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3002 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 780 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 27815 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2876 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 747 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 148 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1270 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1418 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 21922 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2766 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2537 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 5303 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1435 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 21491 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2518 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2502 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 5020 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1409 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 71 # number of nop insts executed -system.cpu.iew.exec_nop::1 73 # number of nop insts executed -system.cpu.iew.exec_nop::total 144 # number of nop insts executed -system.cpu.iew.exec_refs::0 3883 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3616 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 7499 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1763 # Number of branches executed -system.cpu.iew.exec_branches::1 1733 # Number of branches executed -system.cpu.iew.exec_branches::total 3496 # Number of branches executed -system.cpu.iew.exec_stores::0 1117 # Number of stores executed -system.cpu.iew.exec_stores::1 1079 # Number of stores executed -system.cpu.iew.exec_stores::total 2196 # Number of stores executed -system.cpu.iew.exec_rate 0.461419 # Inst execution rate -system.cpu.iew.wb_sent::0 10477 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 10192 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 20669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 10260 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 10004 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 20264 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5390 # num instructions producing a value -system.cpu.iew.wb_producers::1 5243 # num instructions producing a value -system.cpu.iew.wb_producers::total 10633 # num instructions producing a value -system.cpu.iew.wb_consumers::0 7128 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6992 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 14120 # num instructions consuming a value +system.cpu.iew.exec_nop::0 69 # number of nop insts executed +system.cpu.iew.exec_nop::1 67 # number of nop insts executed +system.cpu.iew.exec_nop::total 136 # number of nop insts executed +system.cpu.iew.exec_refs::0 3616 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3607 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 7223 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1734 # Number of branches executed +system.cpu.iew.exec_branches::1 1745 # Number of branches executed +system.cpu.iew.exec_branches::total 3479 # Number of branches executed +system.cpu.iew.exec_stores::0 1098 # Number of stores executed +system.cpu.iew.exec_stores::1 1105 # Number of stores executed +system.cpu.iew.exec_stores::total 2203 # Number of stores executed +system.cpu.iew.exec_rate 0.421392 # Inst execution rate +system.cpu.iew.wb_sent::0 10180 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 10330 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 20510 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9974 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 10135 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 20109 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5251 # num instructions producing a value +system.cpu.iew.wb_producers::1 5302 # num instructions producing a value +system.cpu.iew.wb_producers::total 10553 # num instructions producing a value +system.cpu.iew.wb_consumers::0 7044 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 7008 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 14052 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.215955 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.210566 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.426521 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.756173 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.749857 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.753045 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.195569 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.198725 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.394294 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.745457 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.756564 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.750996 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 15441 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 15019 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1167 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28457 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.449028 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.318063 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1130 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 27612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462770 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.343029 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23389 82.19% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2450 8.61% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1057 3.71% 94.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 365 1.28% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 316 1.11% 96.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 193 0.68% 97.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 226 0.79% 98.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 154 0.54% 98.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 307 1.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22639 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2318 8.39% 90.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1067 3.86% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 382 1.38% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 325 1.18% 96.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 202 0.73% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 208 0.75% 98.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 146 0.53% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 325 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28457 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 27612 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12778 # Number of instructions committed @@ -707,28 +707,28 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6389 # Class of committed instruction system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 307 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 325 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133653 # The number of ROB reads -system.cpu.rob.rob_writes 59305 # The number of ROB writes -system.cpu.timesIdled 412 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 130940 # The number of ROB reads +system.cpu.rob.rob_writes 58397 # The number of ROB writes +system.cpu.timesIdled 389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23301 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedInsts::total 12744 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 7.456058 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.456058 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.728029 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.134119 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.134119 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.268238 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 27427 # number of integer regfile reads -system.cpu.int_regfile_writes 15512 # number of integer regfile writes +system.cpu.cpi::0 8.003766 # CPI: Cycles Per Instruction +system.cpu.cpi::1 8.003766 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.001883 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.124941 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.124941 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.249882 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 26966 # number of integer regfile reads +system.cpu.int_regfile_writes 15368 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -736,289 +736,289 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 215.485703 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 5082 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.561605 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 213.719872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 5036 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 346 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.554913 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 215.485703 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.085205 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 12575 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 12575 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 4060 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 4060 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 5082 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 5082 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 5082 # number of overall hits -system.cpu.dcache.overall_hits::total 5082 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1031 # number of overall misses -system.cpu.dcache.overall_misses::total 1031 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22902750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22902750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 50997162 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 50997162 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 73899912 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 73899912 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 73899912 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 73899912 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 4383 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 4383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 213.719872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.084473 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 12454 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 12454 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 4006 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 4006 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1030 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 5036 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 5036 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 5036 # number of overall hits +system.cpu.dcache.overall_hits::total 5036 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1018 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1018 # number of overall misses +system.cpu.dcache.overall_misses::total 1018 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26557000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26557000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48843926 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48843926 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75400926 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75400926 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75400926 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75400926 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 4324 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 4324 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 6113 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 6113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 6113 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 6113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073694 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.073694 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.168657 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.168657 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.168657 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.168657 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70906.346749 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70906.346749 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72029.889831 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72029.889831 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71677.897187 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71677.897187 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5816 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 6054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 6054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 6054 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 6054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073543 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.073543 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.168153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.168153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.168153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.168153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83512.578616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83512.578616 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69777.037143 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69777.037143 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74067.707269 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74067.707269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74067.707269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74067.707269 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5713 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 130 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.835616 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.946154 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 682 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 682 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 349 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 349 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16652250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16652250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536240 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28536240 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536240 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28536240 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046543 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046543 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057091 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057091 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81628.676471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81628.676471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81958.551724 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81958.551724 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 556 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 556 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 672 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 672 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 672 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 672 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 346 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18304750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18304750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11840493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11840493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30145243 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30145243 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30145243 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30145243 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046716 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046716 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057152 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057152 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057152 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057152 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90617.574257 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90617.574257 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82225.645833 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82225.645833 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87124.979769 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87124.979769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87124.979769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87124.979769 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements::0 7 # number of replacements +system.cpu.icache.tags.replacements::0 8 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements -system.cpu.icache.tags.replacements::total 7 # number of replacements -system.cpu.icache.tags.tagsinuse 320.653868 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4726 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.525478 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements::total 8 # number of replacements +system.cpu.icache.tags.tagsinuse 322.759154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4537 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.111285 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 320.653868 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.156569 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.156569 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11936 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11936 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4726 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4726 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4726 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4726 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4726 # number of overall hits -system.cpu.icache.overall_hits::total 4726 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5654 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5654 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5654 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5654 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5654 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5654 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.164132 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.164132 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.164132 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.164132 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.164132 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.164132 # 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number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 346 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 984 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 346 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 984 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996865 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997619 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996865 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997967 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996865 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73775.559105 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80584.558824 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75449.096386 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80915.517241 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80915.517241 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73775.559105 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80722.063037 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76262.051282 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73775.559105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80722.063037 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76262.051282 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997967 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80189.858491 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89573.019802 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82451.670644 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81197.916667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81197.916667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80189.858491 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86087.427746 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82267.820774 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80189.858491 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86087.427746 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82267.820774 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1027,101 +1027,101 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38371500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13925750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52297250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9959250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9959250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38371500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23885000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 62256500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38371500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23885000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 62256500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 636 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 636 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 346 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 982 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 636 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 346 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 982 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 43045250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15573250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58618500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9895500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9895500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43045250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25468750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 68514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43045250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25468750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 68514000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997619 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997967 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61296.325879 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68263.480392 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63008.734940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68684.482759 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68684.482759 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61296.325879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68438.395415 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63852.820513 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61296.325879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68438.395415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63852.820513 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997967 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67681.210692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77095.297030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69950.477327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68718.750000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68718.750000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67681.210692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73609.104046 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69769.857434 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67681.210692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73609.104046 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69769.857434 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 144 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 144 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 62976 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 977 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 984 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 977 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 984 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 977 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1032000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 556000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 984 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 492000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1076750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 574250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 830 # Transaction distribution -system.membus.trans_dist::ReadResp 830 # Transaction distribution -system.membus.trans_dist::ReadExReq 145 # Transaction distribution -system.membus.trans_dist::ReadExResp 145 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 838 # Transaction distribution +system.membus.trans_dist::ReadResp 838 # Transaction distribution +system.membus.trans_dist::ReadExReq 144 # Transaction distribution +system.membus.trans_dist::ReadExResp 144 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1964 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 62848 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 975 # Request fanout histogram +system.membus.snoop_fanout::samples 982 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 982 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 975 # Request fanout histogram -system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9051500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 38.1 # Layer utilization (%) +system.membus.snoop_fanout::total 982 # Request fanout histogram +system.membus.reqLayer0.occupancy 1219500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 4.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 5224000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index b851aeb29..fe03e9faf 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25944000 # Number of ticks simulated -final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 27482500 # Number of ticks simulated +final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95549 # Simulator instruction rate (inst/s) -host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171686089 # Simulator tick rate (ticks/s) -host_mem_usage 292480 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 86365 # Simulator instruction rate (inst/s) +host_op_rate 86358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 164391633 # Simulator tick rate (ticks/s) +host_mem_usage 291648 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 22016 # Nu system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory system.physmem.num_reads::total 492 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 848596978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 365094049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1213691027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 848596978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 848596978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 848596978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 365094049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1213691027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 801091604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 344655690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1145747294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 801091604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 801091604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 801091604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 344655690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1145747294 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 492 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 25892500 # Total gap between requests +system.physmem.totGap 27431000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,307 +186,307 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 72 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 404.444444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 264.526762 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 350.678412 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 16.67% 16.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 24 33.33% 50.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 9.72% 59.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.56% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.56% 70.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.17% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation -system.physmem.totQLat 2786000 # Total ticks spent queuing -system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 404.732394 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 270.110571 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.824701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 18.31% 18.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 25.35% 43.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 12.68% 56.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 9.86% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 9.86% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.41% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 5.63% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.82% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 14.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation +system.physmem.totQLat 3613750 # Total ticks spent queuing +system.physmem.totMemAccLat 12838750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7345.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26095.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1145.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1145.75 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.48 # Data bus utilization in percentage -system.physmem.busUtilRead 9.48 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.95 # Data bus utilization in percentage +system.physmem.busUtilRead 8.95 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 411 # Number of row buffer hits during reads +system.physmem.readRowHits 412 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 52627.03 # Average gap between requests -system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 55754.07 # Average gap between requests +system.physmem.pageHitRate 83.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2059200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16044930 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 96750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20252445 # Total energy per rank (pJ) -system.physmem_0.averagePower 857.473194 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 279250 # Time in different power states +system.physmem_0.actBackEnergy 15743115 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20156895 # Total energy per rank (pJ) +system.physmem_0.averagePower 853.427679 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 520250 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22761250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22332250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 14873580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19192260 # Total energy per rank (pJ) -system.physmem_1.averagePower 812.585763 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2246250 # Time in different power states +system.physmem_1.actBackEnergy 15564420 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 518250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19277100 # Total energy per rank (pJ) +system.physmem_1.averagePower 816.177825 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2637000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21062250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22058500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 8578 # Number of BP lookups -system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3046 # Number of BTB hits +system.cpu.branchPred.lookups 8538 # Number of BP lookups +system.cpu.branchPred.condPredicted 5461 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1059 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5976 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3053 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 51.087684 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 609 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 51889 # number of cpu cycles simulated +system.cpu.numCycles 54966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed -system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 16187 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 14246 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 40057 # Number of instructions fetch has processed +system.cpu.fetch.Branches 8538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3662 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 15957 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1000 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 6453 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 567 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.239619 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.385650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 6438 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 32422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.235488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.378208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20972 64.51% 64.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5490 16.89% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 661 2.03% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 508 1.56% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 826 2.54% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 909 2.80% 90.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 334 1.03% 91.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 369 1.14% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2441 7.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20898 64.46% 64.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5494 16.95% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 685 2.11% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 505 1.56% 85.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 819 2.53% 87.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 909 2.80% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 334 1.03% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 371 1.14% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2407 7.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.165314 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.776658 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11331 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12526 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 6844 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 654 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 32422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.155332 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.728760 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11347 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12433 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 6847 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 640 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30561 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 30502 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11931 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1436 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10087 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 6918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 983 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27740 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 585 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 25096 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51799 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 42923 # Number of integer rename lookups +system.cpu.rename.IdleCycles 11955 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1146 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9859 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 6898 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1409 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27684 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 1012 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 25054 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51692 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 42838 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11277 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 768 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 11235 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 767 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 3842 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3673 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23657 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 23655 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21921 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9156 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6522 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21924 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9151 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6501 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32510 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.674285 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.426342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 32422 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.676208 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.425800 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24124 74.20% 74.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3065 9.43% 83.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1561 4.80% 88.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1482 4.56% 92.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 945 2.91% 95.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 726 2.23% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 412 1.27% 99.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 154 0.47% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 41 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24009 74.05% 74.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3087 9.52% 83.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1572 4.85% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1483 4.57% 93.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 954 2.94% 95.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 709 2.19% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 413 1.27% 99.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 155 0.48% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 40 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32422 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112 49.56% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 49 21.68% 71.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 65 28.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111 49.33% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 49 21.78% 71.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 65 28.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16292 74.32% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3506 15.99% 90.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16300 74.35% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3501 15.97% 90.32% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21921 # Type of FU issued -system.cpu.iq.rate 0.422459 # Inst issue rate -system.cpu.iq.fu_busy_cnt 226 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010310 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76635 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 33566 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20237 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21924 # Type of FU issued +system.cpu.iq.rate 0.398865 # Inst issue rate +system.cpu.iq.fu_busy_cnt 225 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010263 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 76549 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22147 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22149 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1122 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 322 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25510 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 1147 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25507 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3673 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 318 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20909 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1194 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20914 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3347 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1127 # number of nop insts executed -system.cpu.iew.exec_refs 5373 # number of memory reference insts executed -system.cpu.iew.exec_branches 4425 # Number of branches executed +system.cpu.iew.exec_nop 1126 # number of nop insts executed +system.cpu.iew.exec_refs 5371 # number of memory reference insts executed +system.cpu.iew.exec_branches 4427 # Number of branches executed system.cpu.iew.exec_stores 2024 # Number of stores executed -system.cpu.iew.exec_rate 0.402956 # Inst execution rate -system.cpu.iew.wb_sent 20494 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 20237 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9846 # num instructions producing a value -system.cpu.iew.wb_consumers 12767 # num instructions consuming a value +system.cpu.iew.exec_rate 0.380490 # Inst execution rate +system.cpu.iew.wb_sent 20501 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 20244 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9848 # num instructions producing a value +system.cpu.iew.wb_consumers 12670 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.390006 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.771207 # average fanout of values written-back +system.cpu.iew.wb_rate 0.368300 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.777269 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10297 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10287 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.497996 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.310786 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1059 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 30361 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.499391 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308685 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23926 78.59% 78.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3430 11.27% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1163 3.82% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 612 2.01% 95.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 344 1.13% 96.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 240 0.79% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 396 1.30% 98.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23816 78.44% 78.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3429 11.29% 89.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1193 3.93% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 637 2.10% 95.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 331 1.09% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 224 0.74% 97.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 397 1.31% 98.90% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 273 0.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 272 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30361 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -532,105 +532,105 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 273 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54809 # The number of ROB reads -system.cpu.rob.rob_writes 52997 # The number of ROB writes -system.cpu.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19379 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54715 # The number of ROB reads +system.cpu.rob.rob_writes 52974 # The number of ROB writes +system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 22544 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads -system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 33401 # number of integer regfile reads -system.cpu.int_regfile_writes 18599 # number of integer regfile writes -system.cpu.misc_regfile_reads 7136 # number of misc regfile reads +system.cpu.cpi 3.807564 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.807564 # CPI: Total CPI of All Threads +system.cpu.ipc 0.262635 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.262635 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 33408 # number of integer regfile reads +system.cpu.int_regfile_writes 18606 # number of integer regfile writes +system.cpu.misc_regfile_reads 7133 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 98.556611 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4125 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.061224 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.556611 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024062 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024062 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 9489 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 9489 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3086 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits -system.cpu.dcache.overall_hits::total 4118 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4119 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4119 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4119 # number of overall hits +system.cpu.dcache.overall_hits::total 4119 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 137 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 137 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses -system.cpu.dcache.overall_misses::total 548 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 546 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 546 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 546 # number of overall misses +system.cpu.dcache.overall_misses::total 546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9397000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9397000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27538481 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27538481 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36935481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36935481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36935481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36935481 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3223 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3223 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4665 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4665 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4665 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4665 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042507 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042507 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.117042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117042 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117042 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68591.240876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68591.240876 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67331.249389 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67331.249389 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67647.401099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67647.401099 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.818182 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 398 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -639,135 +639,135 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5143250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5143250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6389250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6389250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11532500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11532500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11532500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11532500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020168 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020168 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031726 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031726 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79126.923077 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79126.923077 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76978.915663 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76978.915663 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 190.975563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5904 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.063584 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 190.975563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.093250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.093250 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13252 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 5925 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5925 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5925 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5925 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits -system.cpu.icache.overall_hits::total 5925 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses -system.cpu.icache.overall_misses::total 528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081822 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21861250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31412250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses @@ -873,17 +873,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63550.145349 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65734.615385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63897.310513 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63593.373494 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63593.373494 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution @@ -908,10 +908,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 245000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.membus.trans_dist::ReadReq 409 # Transaction distribution system.membus.trans_dist::ReadResp 408 # Transaction distribution @@ -932,9 +932,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 492 # Request fanout histogram -system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2599750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 9.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 5faa1ad2c..56b893c5d 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000041 # Number of seconds simulated -sim_ticks 41368000 # Number of ticks simulated -final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 41368500 # Number of ticks simulated +final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 245276 # Simulator instruction rate (inst/s) -host_op_rate 245221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 668919684 # Simulator tick rate (ticks/s) -host_mem_usage 285672 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 311873 # Simulator instruction rate (inst/s) +host_op_rate 311783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 850451247 # Simulator tick rate (ticks/s) +host_mem_usage 289340 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,40 +21,17 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 331 # Transaction distribution -system.membus.trans_dist::ReadResp 331 # Transaction distribution -system.membus.trans_dist::ReadExReq 85 # Transaction distribution -system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 416 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 416 # Request fanout histogram -system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.1 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 82736 # number of cpu cycles simulated +system.cpu.numCycles 82737 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 82735.998000 # Number of busy cycles +system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 3363 # Number of branches fetched @@ -112,15 +89,123 @@ system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 97.991492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 97.991492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits +system.cpu.dcache.overall_hits::total 3529 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses +system.cpu.dcache.overall_misses::total 138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4547500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4547500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 153.777491 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 153.777491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075087 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id @@ -139,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -157,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -177,36 +262,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14896500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14896500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14896500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14896500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14896500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14896500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53201.785714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53201.785714 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.625818 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.105687 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.520131 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id @@ -230,17 +315,17 @@ system.cpu.l2cache.demand_misses::total 416 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17378000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7245000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7245000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses) @@ -263,17 +348,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995215 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.510574 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.201923 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -293,17 +378,17 @@ system.cpu.l2cache.demand_mshr_misses::total 416 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13405500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5589000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5589000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses @@ -315,126 +400,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits -system.cpu.dcache.overall_hits::total 3529 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -463,5 +440,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 420000 # La system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadReq 331 # Transaction distribution +system.membus.trans_dist::ReadResp 331 # Transaction distribution +system.membus.trans_dist::ReadExReq 85 # Transaction distribution +system.membus.trans_dist::ReadExResp 85 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 416 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 416 # Request fanout histogram +system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2080500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index ffbae61d5..948908ba0 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,88 +1,88 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105542000 # Number of ticks simulated -final_tick 105542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000108 # Number of seconds simulated +sim_ticks 107944000 # Number of ticks simulated +final_tick 107944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163449 # Simulator instruction rate (inst/s) -host_op_rate 163449 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17392605 # Simulator tick rate (ticks/s) -host_mem_usage 309188 # Number of bytes of host memory used -host_seconds 6.07 # Real time elapsed on the host -sim_insts 991839 # Number of instructions simulated -sim_ops 991839 # Number of ops (including micro ops) simulated +host_inst_rate 162812 # Simulator instruction rate (inst/s) +host_op_rate 162812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17679745 # Simulator tick rate (ticks/s) +host_mem_usage 308116 # Number of bytes of host memory used +host_seconds 6.11 # Real time elapsed on the host +sim_insts 994048 # Number of instructions simulated +sim_ops 994048 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 22976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 4864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 22976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 4864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 359 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 76 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 664 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 217695325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101874135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 7276724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7883118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 46085918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 12127873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1819181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7883118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 402645392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 217695325 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 7276724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 46085918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1819181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 272877148 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 217695325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101874135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 7276724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7883118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 46085918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 12127873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1819181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7883118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 402645392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 665 # Number of read requests accepted +system.physmem.num_reads::total 669 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 214629808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100200104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47432002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11858000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 4150300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7707700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2964500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7707700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 396650115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 214629808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47432002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 4150300 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2964500 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269176610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 214629808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100200104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47432002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11858000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 4150300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7707700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2964500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7707700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 396650115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 670 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 665 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 670 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 42560 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 42880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 42560 # Total read bytes from the system interface side +system.physmem.bytesReadSys 42880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 115 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 27 # Per bank write bursts system.physmem.perBankRdBursts::3 60 # Per bank write bursts -system.physmem.perBankRdBursts::4 65 # Per bank write bursts +system.physmem.perBankRdBursts::4 66 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts system.physmem.perBankRdBursts::6 18 # Per bank write bursts system.physmem.perBankRdBursts::7 24 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 22 # Per bank write bursts -system.physmem.perBankRdBursts::11 13 # Per bank write bursts +system.physmem.perBankRdBursts::9 29 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 14 # Per bank write bursts system.physmem.perBankRdBursts::12 65 # Per bank write bursts system.physmem.perBankRdBursts::13 38 # Per bank write bursts system.physmem.perBankRdBursts::14 17 # Per bank write bursts @@ -105,14 +105,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 105514000 # Total gap between requests +system.physmem.totGap 107916000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 665 # Read request sizes (log2) +system.physmem.readPktSize::6 670 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -120,10 +120,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -216,556 +216,556 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.338028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.767584 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.989000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41 28.87% 28.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38 26.76% 55.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 26 18.31% 73.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 8.45% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 4.23% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 4.23% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 4.23% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.41% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 3.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142 # Bytes accessed per row activation -system.physmem.totQLat 6421750 # Total ticks spent queuing -system.physmem.totMemAccLat 18890500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3325000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9656.77 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.702703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.430987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 234.776821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 43 29.05% 29.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39 26.35% 55.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 25 16.89% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19 12.84% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 4.05% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 4.05% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 3.38% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.35% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 2.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation +system.physmem.totQLat 6539750 # Total ticks spent queuing +system.physmem.totMemAccLat 19102250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9760.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28406.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 403.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28510.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 397.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 403.25 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 397.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.15 # Data bus utilization in percentage -system.physmem.busUtilRead 3.15 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.10 # Data bus utilization in percentage +system.physmem.busUtilRead 3.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 512 # Number of row buffer hits during reads +system.physmem.readRowHits 511 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 158667.67 # Average gap between requests -system.physmem.pageHitRate 76.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 687960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 375375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2753400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 161068.66 # Average gap between requests +system.physmem.pageHitRate 76.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2761200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 29877120 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34680750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 74985885 # Total energy per rank (pJ) -system.physmem_0.averagePower 738.913691 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57973250 # Time in different power states +system.physmem_0.actBackEnergy 39247065 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 26461500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 76167750 # Total energy per rank (pJ) +system.physmem_0.averagePower 750.559832 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 46478250 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40577250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 54316750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2043600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 27463455 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36789750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 73457280 # Total energy per rank (pJ) -system.physmem_1.averagePower 723.948851 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 62480000 # Time in different power states +system.physmem_1.actBackEnergy 30855240 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 33814500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 73943955 # Total energy per rank (pJ) +system.physmem_1.averagePower 728.745214 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 59727000 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37046000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 42022000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81296 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78365 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1199 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 77900 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75117 # Number of BTB hits +system.cpu0.branchPred.lookups 81450 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78581 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1205 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 78182 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75500 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.427471 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 763 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 96.569543 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 747 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211085 # number of cpu cycles simulated +system.cpu0.numCycles 215889 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20068 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 480268 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81296 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 75880 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 163785 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 20419 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 481443 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81450 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76247 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165590 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2709 # Number of cycles fetch has spent squashing system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1916 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 7139 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 648 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 187121 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.566617 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.228608 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 2214 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 7225 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 189580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.539524 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.227640 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30271 16.18% 16.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77424 41.38% 57.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 764 0.41% 57.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1076 0.58% 58.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 72740 38.87% 97.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 718 0.38% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 448 0.24% 98.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3056 1.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 32064 16.91% 16.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77818 41.05% 57.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818 0.43% 58.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1146 0.60% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 623 0.33% 59.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 72992 38.50% 97.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 703 0.37% 98.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 447 0.24% 98.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2969 1.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 187121 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.385134 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.275235 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::total 189580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.377277 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.230049 # Number of inst fetches per cycle system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 17868 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 151448 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 678 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1349 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 468198 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1349 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16395 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2033 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 151464 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1264 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 464735 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 318331 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 926755 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 700443 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 304259 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14072 # Number of HB maps that are undone due to squashing +system.cpu0.decode.BlockedCycles 19697 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 152079 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 672 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1354 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 469796 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1354 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16409 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2266 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15970 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 152076 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1505 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 466337 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1001 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 319451 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 929999 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 702902 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 305355 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14096 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4585 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148203 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75025 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72247 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 71998 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 388891 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 968 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 385538 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12303 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11219 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 409 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 187121 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.060367 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.127018 # Number of insts issued each cycle +system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4587 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148758 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75265 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72519 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72258 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 390345 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 386997 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 12329 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11208 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 189580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.041339 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.140292 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33176 17.73% 17.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4313 2.30% 20.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73426 39.24% 59.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 72986 39.00% 98.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1673 0.89% 99.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 893 0.48% 99.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 397 0.21% 99.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 180 0.10% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 35140 18.54% 18.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4258 2.25% 20.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73622 38.83% 59.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73334 38.68% 98.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1646 0.87% 99.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 901 0.48% 99.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 423 0.22% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 182 0.10% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 74 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 187121 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 189580 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 102 35.29% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 84 29.07% 64.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 91 32.73% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 84 30.22% 62.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 37.05% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 163537 42.42% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 147667 38.30% 80.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74334 19.28% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164205 42.43% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 148197 38.29% 80.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74595 19.28% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 385538 # Type of FU issued -system.cpu0.iq.rate 1.826459 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000750 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 958509 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 402215 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 383670 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 386997 # Type of FU issued +system.cpu0.iq.rate 1.792574 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 278 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000718 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 963876 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 403692 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 385100 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 385827 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 387275 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71619 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71895 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2491 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1659 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1995 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 462536 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148203 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75025 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 847 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 324 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.iewSquashCycles 1354 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2232 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 464248 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 148758 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75265 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 333 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1104 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 384525 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147369 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1013 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 385946 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 147890 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1051 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 72677 # number of nop insts executed -system.cpu0.iew.exec_refs 221564 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76264 # Number of branches executed -system.cpu0.iew.exec_stores 74195 # Number of stores executed -system.cpu0.iew.exec_rate 1.821660 # Inst execution rate -system.cpu0.iew.wb_sent 384046 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 383670 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 227520 # num instructions producing a value -system.cpu0.iew.wb_consumers 230755 # num instructions consuming a value +system.cpu0.iew.exec_nop 72936 # number of nop insts executed +system.cpu0.iew.exec_refs 222349 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76534 # Number of branches executed +system.cpu0.iew.exec_stores 74459 # Number of stores executed +system.cpu0.iew.exec_rate 1.787706 # Inst execution rate +system.cpu0.iew.wb_sent 385475 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 385100 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 228400 # num instructions producing a value +system.cpu0.iew.wb_consumers 231722 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.817609 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.985981 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.783787 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.985664 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13745 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13801 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1199 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 184477 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.432498 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.147629 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1205 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 186928 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.409398 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.152220 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33360 18.08% 18.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75359 40.85% 58.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2024 1.10% 60.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 644 0.35% 60.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 522 0.28% 60.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71315 38.66% 99.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 246 0.13% 99.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 487 0.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 35407 18.94% 18.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75555 40.42% 59.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1920 1.03% 60.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 633 0.34% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 494 0.26% 60.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71651 38.33% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 511 0.27% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 494 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 184477 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 448740 # Number of instructions committed -system.cpu0.commit.committedOps 448740 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186928 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 450384 # Number of instructions committed +system.cpu0.commit.committedOps 450384 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219085 # Number of memory references committed -system.cpu0.commit.loads 145719 # Number of loads committed +system.cpu0.commit.refs 219907 # Number of memory references committed +system.cpu0.commit.loads 146267 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75253 # Number of branches committed +system.cpu0.commit.branches 75527 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 302590 # Number of committed integer instructions. +system.cpu0.commit.int_insts 303686 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 71985 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 157586 35.12% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 145803 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73366 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72259 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 158134 35.11% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 146351 32.49% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73640 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 448740 # Class of committed instruction -system.cpu0.commit.bw_lim_events 487 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 450384 # Class of committed instruction +system.cpu0.commit.bw_lim_events 494 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 645314 # The number of ROB reads -system.cpu0.rob.rob_writes 927635 # The number of ROB writes -system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23964 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 376671 # Number of Instructions Simulated -system.cpu0.committedOps 376671 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.560396 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.560396 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.784452 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.784452 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 687652 # number of integer regfile reads -system.cpu0.int_regfile_writes 310240 # number of integer regfile writes +system.cpu0.rob.rob_reads 649458 # The number of ROB reads +system.cpu0.rob.rob_writes 931043 # The number of ROB writes +system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26309 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 378041 # Number of Instructions Simulated +system.cpu0.committedOps 378041 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.571073 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.571073 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.751090 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.751090 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 690199 # number of integer regfile reads +system.cpu0.int_regfile_writes 311415 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 223454 # number of misc regfile reads +system.cpu0.misc_regfile_reads 224240 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.523626 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 147885 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 869.911765 # Average number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 140.939988 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 148370 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 867.660819 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.523626 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276413 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.276413 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 596477 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 596477 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75193 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75193 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72780 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72780 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147973 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 147973 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147973 # number of overall hits -system.cpu0.dcache.overall_hits::total 147973 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 482 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 482 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1026 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1026 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1026 # number of overall misses -system.cpu0.dcache.overall_misses::total 1026 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15529368 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 15529368 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32868763 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32868763 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 428750 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 428750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 48398131 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 48398131 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 48398131 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 48398131 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75675 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75675 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73324 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73324 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.occ_blocks::cpu0.data 140.939988 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275273 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275273 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 598524 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 598524 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75399 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75399 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73059 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73059 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 148458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 148458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148458 # number of overall hits +system.cpu0.dcache.overall_hits::total 148458 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 514 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 514 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 539 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 539 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1053 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1053 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1053 # number of overall misses +system.cpu0.dcache.overall_misses::total 1053 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17626915 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 17626915 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36442515 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36442515 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 680000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 680000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 54069430 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 54069430 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 54069430 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 54069430 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75913 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75913 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73598 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73598 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 148999 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 148999 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 148999 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 148999 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006369 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006369 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007419 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007419 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006886 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006886 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006886 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006886 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32218.605809 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32218.605809 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60420.520221 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 60420.520221 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19488.636364 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19488.636364 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 47171.667641 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 47171.667641 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 149511 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149511 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 149511 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 149511 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006771 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006771 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007324 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007324 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007043 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007043 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34293.608949 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34293.608949 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67611.345083 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67611.345083 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 32380.952381 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 32380.952381 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 51347.986705 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 51347.986705 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1036 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.925926 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 79.692308 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 299 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 664 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 664 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6541511 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6541511 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7390227 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7390227 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 383250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 383250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13931738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13931738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13931738 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13931738 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002418 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002418 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002441 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002441 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002430 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002430 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 35745.961749 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 35745.961749 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41286.184358 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41286.184358 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17420.454545 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17420.454545 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 330 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 330 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 362 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 362 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 692 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 692 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 692 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 184 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6770753 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6770753 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8530978 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8530978 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 646500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 646500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15301731 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15301731 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15301731 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15301731 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002405 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002405 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002415 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002415 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36797.570652 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36797.570652 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48197.615819 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48197.615819 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 30785.714286 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 30785.714286 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 319 # number of replacements -system.cpu0.icache.tags.tagsinuse 239.733862 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6347 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 608 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.439145 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 323 # number of replacements +system.cpu0.icache.tags.tagsinuse 240.188663 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6428 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 614 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.469055 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 239.733862 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.468230 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.468230 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id +system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.188663 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469118 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.469118 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.564453 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7747 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7747 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6347 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6347 # 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number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 36432996 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 36432996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 36432996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7139 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7139 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7139 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7139 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110940 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110940 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110940 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110940 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110940 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110940 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46001.257576 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46001.257576 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46001.257576 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46001.257576 # average overall miss latency +system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.568359 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 7839 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7839 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6428 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6428 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6428 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6428 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6428 # number of overall hits +system.cpu0.icache.overall_hits::total 6428 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses +system.cpu0.icache.overall_misses::total 797 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40514746 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40514746 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40514746 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40514746 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40514746 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40514746 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7225 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7225 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7225 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7225 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7225 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7225 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110311 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110311 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110311 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110311 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110311 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110311 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50834.060226 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 50834.060226 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 50834.060226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 50834.060226 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,410 +774,410 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 183 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 183 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 183 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 183 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 183 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 609 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 609 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 609 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 609 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 609 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27995751 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27995751 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27995751 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27995751 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27995751 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27995751 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085306 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085306 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085306 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45970.034483 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 182 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 182 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 182 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 182 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 615 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 615 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31043001 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31043001 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31043001 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31043001 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31043001 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31043001 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085121 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085121 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085121 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 50476.424390 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 48230 # Number of BP lookups -system.cpu1.branchPred.condPredicted 44811 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1266 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 41091 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 39963 # Number of BTB hits +system.cpu1.branchPred.lookups 52261 # Number of BP lookups +system.cpu1.branchPred.condPredicted 48386 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1341 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 44394 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 43169 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.254873 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 868 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.240618 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 160735 # number of cpu cycles simulated +system.cpu1.numCycles 162232 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 33641 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 261327 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 48230 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 40831 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 122936 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2691 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 31153 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 288417 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52261 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 44075 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 122623 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2833 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1065 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 24854 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 432 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 159000 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.643566 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.124362 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1159 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 21623 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 156364 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.844523 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.218152 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 63867 40.17% 40.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 48973 30.80% 70.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 8266 5.20% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3472 2.18% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1057 0.66% 79.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 27547 17.33% 96.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1174 0.74% 97.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 753 0.47% 97.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3891 2.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 56063 35.85% 35.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 50599 32.36% 68.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6236 3.99% 72.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3531 2.26% 74.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 937 0.60% 75.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 32564 20.83% 95.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1222 0.78% 96.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 843 0.54% 97.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4369 2.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 159000 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.300059 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.625825 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17613 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 67674 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 68228 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4130 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1345 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 247069 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1345 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18292 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33178 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12317 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 69139 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 24719 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 243777 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 21468 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 22 # Number of times rename has blocked due to LQ full -system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 169834 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 458131 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 358650 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 155489 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14345 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 29340 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 66237 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 30368 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 32190 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 25244 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 200152 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7929 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 203048 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12672 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 159000 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.277031 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.370207 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 156364 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.322137 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.777806 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18077 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 54814 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 78767 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3280 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1416 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 271927 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1416 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18807 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 25020 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13667 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 79411 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 18033 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 268621 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 15397 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 31 # Number of times rename has blocked due to LQ full +system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 189765 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 514915 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 401460 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 175087 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14678 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 22640 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 74986 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 35614 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 35483 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 30428 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 223482 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6146 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 225009 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12719 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10743 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 680 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156364 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.439008 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.385420 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 67764 42.62% 42.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 26124 16.43% 59.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 29595 18.61% 77.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 29204 18.37% 96.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3405 2.14% 98.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1592 1.00% 99.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 226 0.14% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 210 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 59519 38.06% 38.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 20894 13.36% 51.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 35016 22.39% 73.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 34585 22.12% 95.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3417 2.19% 98.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1600 1.02% 99.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 882 0.56% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 240 0.15% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 211 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 159000 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156364 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 87 24.30% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 62 17.32% 41.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 58.38% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 92 27.88% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 29 8.79% 36.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 101499 49.99% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 71903 35.41% 85.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 29646 14.60% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 110922 49.30% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 79078 35.14% 84.44% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 35009 15.56% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 203048 # Type of FU issued -system.cpu1.iq.rate 1.263247 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 358 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001763 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 565493 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 220798 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 201375 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 225009 # Type of FU issued +system.cpu1.iq.rate 1.386958 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 330 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001467 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 606728 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 242381 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 223369 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 203406 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 225339 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 24951 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 30296 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2787 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2626 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1552 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1345 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 8539 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 241028 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 239 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 66237 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 30368 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1097 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1416 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7338 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 266019 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 165 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 74986 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 35614 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1009 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1474 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 201951 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 65061 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 34 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1125 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1578 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 223948 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 74035 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 32947 # number of nop insts executed -system.cpu1.iew.exec_refs 94595 # number of memory reference insts executed -system.cpu1.iew.exec_branches 42219 # Number of branches executed -system.cpu1.iew.exec_stores 29534 # Number of stores executed -system.cpu1.iew.exec_rate 1.256422 # Inst execution rate -system.cpu1.iew.wb_sent 201670 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 201375 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 112178 # num instructions producing a value -system.cpu1.iew.wb_consumers 118722 # num instructions consuming a value +system.cpu1.iew.exec_nop 36391 # number of nop insts executed +system.cpu1.iew.exec_refs 108940 # number of memory reference insts executed +system.cpu1.iew.exec_branches 45914 # Number of branches executed +system.cpu1.iew.exec_stores 34905 # Number of stores executed +system.cpu1.iew.exec_rate 1.380418 # Inst execution rate +system.cpu1.iew.wb_sent 223649 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 223369 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 126652 # num instructions producing a value +system.cpu1.iew.wb_consumers 133295 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.252839 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.944880 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.376849 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.950163 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14315 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1266 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 156398 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.449251 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.979774 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14380 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5466 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1341 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 153714 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.636819 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.057713 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 74586 47.69% 47.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 38945 24.90% 72.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5214 3.33% 75.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 8053 5.15% 81.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1537 0.98% 82.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 24957 15.96% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 851 0.54% 98.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 951 0.61% 99.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1304 0.83% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 64759 42.13% 42.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 42554 27.68% 69.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5173 3.37% 73.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6281 4.09% 77.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1529 0.99% 78.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 30355 19.75% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 785 0.51% 98.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 966 0.63% 99.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1312 0.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 156398 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 226660 # Number of instructions committed -system.cpu1.commit.committedOps 226660 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 153714 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 251602 # Number of instructions committed +system.cpu1.commit.committedOps 251602 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 92171 # Number of memory references committed -system.cpu1.commit.loads 63450 # Number of loads committed -system.cpu1.commit.membars 6533 # Number of memory barriers committed -system.cpu1.commit.branches 41215 # Number of branches committed +system.cpu1.commit.refs 106422 # Number of memory references committed +system.cpu1.commit.loads 72360 # Number of loads committed +system.cpu1.commit.membars 4751 # Number of memory barriers committed +system.cpu1.commit.branches 44778 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 155506 # Number of committed integer instructions. +system.cpu1.commit.int_insts 173320 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 32002 14.12% 14.12% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 95954 42.33% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 69983 30.88% 87.33% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 28721 12.67% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 35567 14.14% 14.14% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 104862 41.68% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 77111 30.65% 86.46% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 34062 13.54% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 226660 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 251602 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1312 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 395483 # The number of ROB reads -system.cpu1.rob.rob_writes 484550 # The number of ROB writes -system.cpu1.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1735 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 188125 # Number of Instructions Simulated -system.cpu1.committedOps 188125 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.854405 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.854405 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.170405 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.170405 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 343348 # number of integer regfile reads -system.cpu1.int_regfile_writes 161358 # number of integer regfile writes +system.cpu1.rob.rob_reads 417798 # The number of ROB reads +system.cpu1.rob.rob_writes 534614 # The number of ROB writes +system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 46290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 211284 # Number of Instructions Simulated +system.cpu1.committedOps 211284 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.767839 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.767839 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.302357 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.302357 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 386957 # number of integer regfile reads +system.cpu1.int_regfile_writes 181537 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 96189 # number of misc regfile reads +system.cpu1.misc_regfile_reads 110600 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 23.332143 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 34754 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.579817 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 40184 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1241.214286 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1435.142857 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.332143 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.045571 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.045571 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.579817 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049961 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.049961 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 275515 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 275515 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 39673 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39673 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 28513 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 28513 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 68186 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 68186 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 68186 # number of overall hits -system.cpu1.dcache.overall_hits::total 68186 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 422 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 422 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu1.dcache.tags.tag_accesses 311400 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 311400 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 43257 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 43257 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 33840 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 33840 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 77097 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 77097 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 77097 # number of overall hits +system.cpu1.dcache.overall_hits::total 77097 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 466 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 466 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 153 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 153 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 559 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 559 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 559 # number of overall misses -system.cpu1.dcache.overall_misses::total 559 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5603617 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5603617 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2812761 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2812761 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 492507 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 492507 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8416378 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8416378 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8416378 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8416378 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 40095 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 40095 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 28650 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 28650 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 68745 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 68745 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 68745 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 68745 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010525 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.010525 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004782 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004782 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008132 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.008132 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008132 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.008132 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13278.713270 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13278.713270 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20531.102190 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20531.102190 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8640.473684 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 8640.473684 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15056.132379 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15056.132379 # average overall miss latency +system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses +system.cpu1.dcache.overall_misses::total 619 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9865731 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9865731 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3999011 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3999011 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 673507 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 673507 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13864742 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13864742 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13864742 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13864742 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 43723 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 43723 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 33993 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 33993 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 77716 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 77716 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 77716 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 77716 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010658 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.010658 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004501 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004501 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.826087 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007965 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007965 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007965 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007965 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21171.096567 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 21171.096567 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26137.326797 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26137.326797 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11815.912281 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 11815.912281 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22398.613893 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 22398.613893 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1186,519 +1186,519 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 262 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 296 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 296 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 344 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 344 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 344 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 344 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1125015 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1125015 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1272489 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1272489 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 378493 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 378493 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2397504 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2397504 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2397504 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2397504 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003595 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003595 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7031.343750 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7031.343750 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12354.262136 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12354.262136 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6640.228070 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6640.228070 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_misses::cpu1.data 275 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 275 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1943270 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1943270 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1707489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1707489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 587993 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 587993 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3650759 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3650759 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3650759 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3650759 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003820 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003820 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003177 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003177 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.826087 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003539 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003539 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11636.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11636.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15810.083333 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15810.083333 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10315.666667 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10315.666667 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 388 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.215682 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 24292 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 48.779116 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 385 # number of replacements +system.cpu1.icache.tags.tagsinuse 83.683741 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 21045 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 42.344064 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.215682 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.148859 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.148859 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu1.icache.tags.occ_blocks::cpu1.inst 83.683741 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.163445 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.163445 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 25352 # 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number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7960746 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7960746 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7960746 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7960746 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7960746 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7960746 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 24854 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 24854 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 24854 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 24854 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 24854 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 24854 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022612 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022612 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022612 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022612 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022612 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022612 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.028470 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14165.028470 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14165.028470 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14165.028470 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu1.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 22120 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 22120 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 21045 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 21045 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 21045 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 21045 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 21045 # number of overall hits +system.cpu1.icache.overall_hits::total 21045 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 578 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 578 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 578 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 578 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 578 # number of overall misses +system.cpu1.icache.overall_misses::total 578 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14251747 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14251747 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14251747 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14251747 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14251747 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14251747 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21623 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21623 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21623 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21623 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21623 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21623 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026731 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.026731 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026731 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.026731 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026731 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.026731 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24657.001730 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24657.001730 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24657.001730 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24657.001730 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 64 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 64 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 64 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 64 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6368004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6368004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6368004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6368004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6368004 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6368004 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020037 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.020037 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.020037 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12787.156627 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11245503 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11245503 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11245503 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11245503 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11245503 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11245503 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022985 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022985 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022985 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22626.766600 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 55295 # Number of BP lookups -system.cpu2.branchPred.condPredicted 51520 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1304 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 47890 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 46487 # Number of BTB hits +system.cpu2.branchPred.lookups 51309 # Number of BP lookups +system.cpu2.branchPred.condPredicted 47950 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1280 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 43975 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 43053 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.070370 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.903354 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 160375 # number of cpu cycles simulated +system.cpu2.numCycles 161860 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28879 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 309014 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 55295 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 47386 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 123906 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.icacheStallCycles 31583 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 282068 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51309 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 43939 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 125716 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2717 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 19451 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 461 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 155294 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.989864 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.243889 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1207 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 22884 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 412 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 159877 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.764281 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.167875 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49501 31.88% 31.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 52893 34.06% 65.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 5338 3.44% 69.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3457 2.23% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 949 0.61% 72.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 36899 23.76% 95.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1216 0.78% 96.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 841 0.54% 97.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 4200 2.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 59518 37.23% 37.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51095 31.96% 69.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7306 4.57% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3438 2.15% 75.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 997 0.62% 76.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 31616 19.78% 96.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1254 0.78% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 769 0.48% 97.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3884 2.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 155294 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.344786 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.926822 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17746 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 46456 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 86830 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 2870 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1382 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 293603 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1382 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18442 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 20397 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12871 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 87967 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14225 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 290431 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 12472 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 29 # Number of times rename has blocked due to LQ full -system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 205748 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 562377 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 437048 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 190737 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15011 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1232 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 18731 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 82610 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 39860 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 38981 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34721 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 242796 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 5190 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 242904 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12157 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 155294 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.564156 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.378675 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 159877 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.316996 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.742667 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17468 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 61085 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 76240 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3716 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1358 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 267722 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1358 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18170 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 29188 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12834 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 77782 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 20535 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 264399 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 18336 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 185298 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 503121 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 392507 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 170476 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 14822 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1180 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 25168 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 73362 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 34382 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 35300 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 29228 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 218628 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6983 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 220497 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13020 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 159877 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.379166 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.379581 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 52943 34.09% 34.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 18212 11.73% 45.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39071 25.16% 70.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38654 24.89% 95.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3479 2.24% 98.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1594 1.03% 99.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 891 0.57% 99.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 244 0.16% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 63376 39.64% 39.64% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 23374 14.62% 54.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 33553 20.99% 75.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 33206 20.77% 96.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3423 2.14% 98.16% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1623 1.02% 99.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 877 0.55% 99.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 230 0.14% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 215 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 155294 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 159877 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 90 25.64% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 52 14.81% 40.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 59.54% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 86 23.69% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 68 18.73% 42.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 118122 48.63% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 85639 35.26% 83.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 39143 16.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 108751 49.32% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 78120 35.43% 84.75% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 33626 15.25% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 242904 # Type of FU issued -system.cpu2.iq.rate 1.514600 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 351 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001445 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 641482 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 261162 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 241189 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 220497 # Type of FU issued +system.cpu2.iq.rate 1.362270 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001646 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 601287 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 238674 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 218768 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 243255 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 220860 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 34438 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 28926 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2866 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2863 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1666 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1691 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 6074 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 287692 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 82610 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 39860 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1358 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 8128 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 261616 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 204 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 73362 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 34382 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1074 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1544 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 241779 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 81452 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1125 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1045 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1500 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 219377 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 72164 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1120 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 39706 # number of nop insts executed -system.cpu2.iew.exec_refs 120488 # number of memory reference insts executed -system.cpu2.iew.exec_branches 49059 # Number of branches executed -system.cpu2.iew.exec_stores 39036 # Number of stores executed -system.cpu2.iew.exec_rate 1.507585 # Inst execution rate -system.cpu2.iew.wb_sent 241491 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 241189 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 138145 # num instructions producing a value -system.cpu2.iew.wb_consumers 144798 # num instructions consuming a value +system.cpu2.iew.exec_nop 36005 # number of nop insts executed +system.cpu2.iew.exec_refs 105679 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45327 # Number of branches executed +system.cpu2.iew.exec_stores 33515 # Number of stores executed +system.cpu2.iew.exec_rate 1.355350 # Inst execution rate +system.cpu2.iew.wb_sent 219089 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 218768 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 123331 # num instructions producing a value +system.cpu2.iew.wb_consumers 129941 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.503906 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.954053 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.351588 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.949131 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14779 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 4578 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1304 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152612 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.787933 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.101313 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14642 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6361 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1280 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 157221 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.570534 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.031430 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 57189 37.47% 37.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 45780 30.00% 67.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5178 3.39% 70.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5403 3.54% 74.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1516 0.99% 75.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34396 22.54% 97.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 886 0.58% 98.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 957 0.63% 99.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1307 0.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 69336 44.10% 44.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 41971 26.70% 70.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5151 3.28% 74.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7156 4.55% 78.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1534 0.98% 79.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28975 18.43% 98.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 827 0.53% 98.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1310 0.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152612 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 272860 # Number of instructions committed -system.cpu2.commit.committedOps 272860 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 157221 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 246921 # Number of instructions committed +system.cpu2.commit.committedOps 246921 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 117938 # Number of memory references committed -system.cpu2.commit.loads 79744 # Number of loads committed -system.cpu2.commit.membars 3865 # Number of memory barriers committed -system.cpu2.commit.branches 48024 # Number of branches committed +system.cpu2.commit.refs 103190 # Number of memory references committed +system.cpu2.commit.loads 70499 # Number of loads committed +system.cpu2.commit.membars 5644 # Number of memory barriers committed +system.cpu2.commit.branches 44296 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 188084 # Number of committed integer instructions. +system.cpu2.commit.int_insts 169605 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 38815 14.23% 14.23% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 112242 41.14% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 83609 30.64% 86.00% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 38194 14.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 35083 14.21% 14.21% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 103004 41.72% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 76143 30.84% 86.76% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 32691 13.24% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 272860 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1307 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 246921 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1310 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 438358 # The number of ROB reads -system.cpu2.rob.rob_writes 577962 # The number of ROB writes -system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5081 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 43644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 230180 # Number of Instructions Simulated -system.cpu2.committedOps 230180 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.696737 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.696737 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.435261 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.435261 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 421380 # number of integer regfile reads -system.cpu2.int_regfile_writes 197053 # number of integer regfile writes +system.cpu2.rob.rob_reads 416888 # The number of ROB reads +system.cpu2.rob.rob_writes 525783 # The number of ROB writes +system.cpu2.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1983 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 46662 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 206194 # Number of Instructions Simulated +system.cpu2.committedOps 206194 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.784989 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.784989 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.273903 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.273903 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 376797 # number of integer regfile reads +system.cpu2.int_regfile_writes 176595 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 122100 # number of misc regfile reads +system.cpu2.misc_regfile_reads 107278 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 25.900864 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 44302 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1582.214286 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 24.051885 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 38880 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1340.689655 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.900864 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050588 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.050588 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.051885 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.046976 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.046976 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 341013 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 341013 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 46548 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 46548 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 37978 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 37978 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 84526 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 84526 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 84526 # number of overall hits -system.cpu2.dcache.overall_hits::total 84526 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 448 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 448 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 149 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 149 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 597 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 597 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 597 # number of overall misses -system.cpu2.dcache.overall_misses::total 597 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7705986 # 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number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 38127 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 38127 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 85123 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 85123 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 85123 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 85123 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009533 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009533 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003908 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003908 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.820896 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007013 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007013 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007013 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007013 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17200.861607 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17200.861607 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24624.241611 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 24624.241611 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9191.054545 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9191.054545 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 19053.597990 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 19053.597990 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 303893 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 303893 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 42781 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42781 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 32487 # 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number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 10304545 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 43221 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 32620 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 32620 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 75841 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 75841 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 75841 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 75841 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010180 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010180 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004077 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004077 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.802817 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007555 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007555 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007555 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007555 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16685.870455 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16685.870455 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22276.406015 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22276.406015 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10421.140351 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10421.140351 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17983.499127 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17983.499127 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1707,519 +1707,518 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 289 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 330 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 330 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526276 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526276 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511738 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511738 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 395492 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 395492 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3038014 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3038014 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3038014 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3038014 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003383 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003383 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002833 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002833 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.820896 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003137 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003137 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9599.220126 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9599.220126 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13997.574074 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13997.574074 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7190.763636 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7190.763636 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 285 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 31 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 316 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 316 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 316 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 257 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 257 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1424773 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1424773 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1555988 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1555988 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 508495 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 508495 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2980761 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2980761 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2980761 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2980761 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003586 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003586 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003127 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003127 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003389 # 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Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 19941 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 19941 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 18881 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 18881 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 18881 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 18881 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 18881 # number of overall hits -system.cpu2.icache.overall_hits::total 18881 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 570 # 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number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19451 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19451 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19451 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19451 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029304 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.029304 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029304 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.029304 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029304 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.029304 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23403.935088 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23403.935088 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23403.935088 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23403.935088 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked +system.cpu2.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 23378 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 23378 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 22324 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 22324 # 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miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024471 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024471 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024471 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024471 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15098.196429 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15098.196429 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15098.196429 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15098.196429 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10370006 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10370006 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10370006 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10370006 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10370006 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10370006 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025192 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.025192 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.025192 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21163.277551 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 66 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 66 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 66 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 494 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 494 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 494 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 494 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 494 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 494 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6668508 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6668508 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6668508 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6668508 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6668508 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6668508 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021587 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021587 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021587 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13499.004049 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 49708 # Number of BP lookups -system.cpu3.branchPred.condPredicted 46346 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 42456 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 41477 # Number of BTB hits +system.cpu3.branchPred.lookups 49957 # Number of BP lookups +system.cpu3.branchPred.condPredicted 46526 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1263 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 42773 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 41661 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.694083 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 887 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.400229 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 160031 # number of cpu cycles simulated +system.cpu3.numCycles 161075 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 32677 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 271496 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 49708 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 42364 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 123781 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2713 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 32422 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 272949 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49957 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 42547 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 124988 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2685 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1129 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 23830 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 414 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 158956 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.707995 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.148637 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1170 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 23669 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 411 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 159935 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.706625 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.149562 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 61281 38.55% 38.55% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 50034 31.48% 70.03% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7755 4.88% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3467 2.18% 77.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1003 0.63% 77.72% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 29472 18.54% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1313 0.83% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 747 0.47% 97.56% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3884 2.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 61940 38.73% 38.73% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 50129 31.34% 70.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7684 4.80% 74.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3433 2.15% 77.02% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1026 0.64% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 29810 18.64% 96.30% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1265 0.79% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 775 0.48% 97.58% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3873 2.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 158956 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.310615 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.696521 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17592 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 63734 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 72321 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 3943 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1356 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 257189 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1356 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18288 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 30790 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12415 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 73229 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 22868 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 253914 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 19808 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 26 # Number of times rename has blocked due to LQ full -system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 177532 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 480099 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 375267 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 162743 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14789 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1176 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 27539 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 69653 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 32298 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 33633 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 27116 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 209239 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7471 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 211679 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 13005 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11959 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 663 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 158956 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.331683 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.377458 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 159935 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.310147 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.694546 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17524 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 64435 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 72722 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3902 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1342 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 258692 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1342 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18198 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 31170 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12771 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 73832 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 22612 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 255419 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 23 # Number of times rename has blocked due to LQ full +system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 178600 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 483471 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 377749 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 164114 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14486 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1167 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 27248 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 70256 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 32624 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33902 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 27488 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 210626 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7365 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 213102 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12659 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11687 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 617 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 159935 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.332429 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.375890 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 65156 40.99% 40.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 24774 15.59% 56.58% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 31508 19.82% 76.40% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 31138 19.59% 95.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3432 2.16% 98.15% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1609 1.01% 99.16% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 879 0.55% 99.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 252 0.16% 99.87% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 65625 41.03% 41.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24603 15.38% 56.42% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31869 19.93% 76.34% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 31495 19.69% 96.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3384 2.12% 98.15% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1646 1.03% 99.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 234 0.15% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 158956 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 159935 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 91 25.07% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 63 17.36% 42.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 83 23.71% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 58 16.57% 40.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 59.71% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 105163 49.68% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 74926 35.40% 85.08% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 31590 14.92% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 105687 49.59% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 75490 35.42% 85.02% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31925 14.98% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 211679 # Type of FU issued -system.cpu3.iq.rate 1.322737 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 363 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001715 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 582726 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 229757 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 209929 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 213102 # Type of FU issued +system.cpu3.iq.rate 1.322999 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 350 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001642 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 586529 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 230693 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 211399 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 212042 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 213452 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 26876 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 27230 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2797 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2740 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1652 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1356 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8047 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 251105 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 69653 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 32298 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1093 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewSquashCycles 1342 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8471 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 252649 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 70256 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 32624 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1081 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 42 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1042 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 210537 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 68521 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1012 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1478 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 211973 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 69143 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1129 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 34395 # number of nop insts executed -system.cpu3.iew.exec_refs 99995 # number of memory reference insts executed -system.cpu3.iew.exec_branches 43728 # Number of branches executed -system.cpu3.iew.exec_stores 31474 # Number of stores executed -system.cpu3.iew.exec_rate 1.315601 # Inst execution rate -system.cpu3.iew.wb_sent 210248 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 209929 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 117676 # num instructions producing a value -system.cpu3.iew.wb_consumers 124324 # num instructions consuming a value +system.cpu3.iew.exec_nop 34658 # number of nop insts executed +system.cpu3.iew.exec_refs 100953 # number of memory reference insts executed +system.cpu3.iew.exec_branches 44015 # Number of branches executed +system.cpu3.iew.exec_stores 31810 # Number of stores executed +system.cpu3.iew.exec_rate 1.315989 # Inst execution rate +system.cpu3.iew.wb_sent 211700 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 211399 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 118601 # num instructions producing a value +system.cpu3.iew.wb_consumers 125234 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.311802 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.946527 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.312426 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.947035 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14613 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6808 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 156309 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.512638 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.007092 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14249 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6748 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1263 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 157342 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.514834 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.009338 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 71539 45.77% 45.77% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 40455 25.88% 71.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5161 3.30% 74.95% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7618 4.87% 79.82% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1540 0.99% 80.81% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 26903 17.21% 98.02% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 829 0.53% 98.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 953 0.61% 99.16% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1311 0.84% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 72048 45.79% 45.79% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 40652 25.84% 71.63% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5170 3.29% 74.91% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7572 4.81% 79.73% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1532 0.97% 80.70% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 27266 17.33% 98.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 833 0.53% 98.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 969 0.62% 99.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1300 0.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 156309 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 236439 # Number of instructions committed -system.cpu3.commit.committedOps 236439 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 157342 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 238347 # Number of instructions committed +system.cpu3.commit.committedOps 238347 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 97502 # Number of memory references committed -system.cpu3.commit.loads 66856 # Number of loads committed -system.cpu3.commit.membars 6091 # Number of memory barriers committed -system.cpu3.commit.branches 42698 # Number of branches committed +system.cpu3.commit.refs 98515 # Number of memory references committed +system.cpu3.commit.loads 67516 # Number of loads committed +system.cpu3.commit.membars 6034 # Number of memory barriers committed +system.cpu3.commit.branches 42994 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 162319 # Number of committed integer instructions. +system.cpu3.commit.int_insts 163632 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 33485 14.16% 14.16% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 99361 42.02% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 72947 30.85% 87.04% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 30646 12.96% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 33784 14.17% 14.17% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 100014 41.96% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 73550 30.86% 86.99% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 30999 13.01% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 236439 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1311 # number cycles where commit BW limit reached +system.cpu3.commit.op_class_0::total 238347 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1300 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 405464 # The number of ROB reads -system.cpu3.rob.rob_writes 504751 # The number of ROB writes -system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1075 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 43988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 196863 # Number of Instructions Simulated -system.cpu3.committedOps 196863 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.812905 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.812905 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.230155 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.230155 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 359772 # number of integer regfile reads -system.cpu3.int_regfile_writes 168916 # number of integer regfile writes +system.cpu3.rob.rob_reads 408052 # The number of ROB reads +system.cpu3.rob.rob_writes 507784 # The number of ROB writes +system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1140 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 47445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 198529 # Number of Instructions Simulated +system.cpu3.committedOps 198529 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.811342 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.811342 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.232525 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.232525 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 362535 # number of integer regfile reads +system.cpu3.int_regfile_writes 170128 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 101608 # number of misc regfile reads +system.cpu3.misc_regfile_reads 102551 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.432858 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 36837 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1270.241379 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 23.026048 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 37058 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1323.500000 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.432858 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047720 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047720 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.026048 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.044973 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.044973 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 289352 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 289352 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 41209 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41209 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 30434 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 30434 # number of WriteReq hits +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 291822 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 291822 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 41456 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41456 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 30794 # 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number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010065 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010065 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004612 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004612 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007756 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007756 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007756 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007756 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12879.563246 # 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miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004429 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007923 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007923 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007923 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007923 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17093.486364 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 17093.486364 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22043.883212 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 22043.883212 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10916.796296 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 10916.796296 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18268.883882 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18268.883882 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2228,106 +2227,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 259 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 259 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 288 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 293 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 293 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 293 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 293 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1078521 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1078521 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1312238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1312238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 366995 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 366995 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2390759 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2390759 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2390759 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2390759 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003844 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003844 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003500 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003500 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003698 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003698 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.756250 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.756250 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12263.906542 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12263.906542 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6438.508772 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6438.508772 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency +system.cpu3.dcache.demand_mshr_hits::cpu3.data 322 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 322 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 322 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 255 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 255 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1429011 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1429011 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1527238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1527238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 508493 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 508493 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2956249 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2956249 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2956249 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2956249 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003628 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003628 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003330 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003330 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003501 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003501 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9401.388158 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9401.388158 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14827.553398 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14827.553398 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9416.537037 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9416.537037 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.tags.replacements 386 # number of replacements -system.cpu3.icache.tags.tagsinuse 78.630086 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 23274 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 495 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 47.018182 # Average number of references to valid blocks. +system.cpu3.icache.tags.replacements 387 # number of replacements +system.cpu3.icache.tags.tagsinuse 75.442206 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 23109 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 46.403614 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 78.630086 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.153574 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.153574 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id +system.cpu3.icache.tags.occ_blocks::cpu3.inst 75.442206 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.147348 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.147348 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 24325 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 24325 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 23274 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23274 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23274 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23274 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23274 # number of overall hits -system.cpu3.icache.overall_hits::total 23274 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 556 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 556 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 556 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 556 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 556 # number of overall misses -system.cpu3.icache.overall_misses::total 556 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7666496 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7666496 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7666496 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7666496 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7666496 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7666496 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 23830 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 23830 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 23830 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 23830 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 23830 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 23830 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023332 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.023332 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023332 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.023332 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023332 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.023332 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13788.661871 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13788.661871 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13788.661871 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13788.661871 # average overall miss latency +system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 24167 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 24167 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 23109 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 23109 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 23109 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 23109 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 23109 # number of overall hits +system.cpu3.icache.overall_hits::total 23109 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 560 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 560 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 560 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 560 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 560 # number of overall misses +system.cpu3.icache.overall_misses::total 560 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7349496 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7349496 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7349496 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7349496 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7349496 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7349496 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 23669 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 23669 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 23669 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 23669 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 23669 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 23669 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023660 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023660 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023660 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023660 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023660 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023660 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13124.100000 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13124.100000 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13124.100000 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13124.100000 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2336,277 +2335,277 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 61 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 61 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 61 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 61 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 495 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 495 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 495 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 495 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 495 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 495 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5988753 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5988753 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5988753 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5988753 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5988753 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5988753 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020772 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.020772 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.020772 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12098.490909 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6152504 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6152504 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6152504 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6152504 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6152504 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6152504 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021040 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.021040 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.021040 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12354.425703 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 421.782597 # Cycle average of tags in use -system.l2c.tags.total_refs 1661 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 531 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.128060 # Average number of references to valid blocks. +system.l2c.tags.tagsinuse 421.791819 # Cycle average of tags in use +system.l2c.tags.total_refs 1669 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 536 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.113806 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.793367 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 288.136506 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.239710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.908939 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.685353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 57.810668 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.358893 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.126194 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.722968 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.783957 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 289.037601 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 57.982294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 60.100309 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.287110 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 5.207527 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.713016 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.004391 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.675614 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004397 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000882 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004410 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000885 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000917 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000079 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.006436 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 531 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008102 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 20025 # Number of tag accesses -system.l2c.tags.data_accesses 20025 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 248 # number of ReadReq hits +system.l2c.tags.occ_task_id_blocks::1024 536 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008179 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 20118 # Number of tag accesses +system.l2c.tags.data_accesses 20118 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 251 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 483 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 409 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 489 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 414 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 481 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 491 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1661 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1669 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 248 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 251 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 483 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 409 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 414 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 481 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1661 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 248 # number of overall hits +system.l2c.demand_hits::total 1669 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 251 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 483 # number of overall hits -system.l2c.overall_hits::cpu1.data 11 # number of overall hits -system.l2c.overall_hits::cpu2.inst 409 # number of overall hits -system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 489 # number of overall hits +system.l2c.overall_hits::cpu1.inst 414 # number of overall hits +system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu2.inst 481 # number of overall hits +system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu3.inst 491 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1661 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 81 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 6 # number of ReadReq misses +system.l2c.overall_hits::total 1669 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 364 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 546 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses +system.l2c.ReadReq_misses::total 551 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 81 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 6 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 364 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64739.332096 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17796.454545 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.777778 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17853.941176 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 17737.842105 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.473684 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74090.425532 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74115.384615 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67166.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 64729.166667 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 534 # Transaction distribution -system.membus.trans_dist::ReadResp 533 # Transaction distribution -system.membus.trans_dist::UpgradeReq 274 # Transaction distribution -system.membus.trans_dist::UpgradeResp 78 # Transaction distribution -system.membus.trans_dist::ReadExReq 179 # Transaction distribution +system.membus.trans_dist::ReadReq 539 # Transaction distribution +system.membus.trans_dist::ReadResp 538 # Transaction distribution +system.membus.trans_dist::UpgradeReq 276 # Transaction distribution +system.membus.trans_dist::UpgradeResp 76 # Transaction distribution +system.membus.trans_dist::ReadExReq 171 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1729 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 42496 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 244 # Total snoops (count) -system.membus.snoop_fanout::samples 987 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1731 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1731 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 42816 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 240 # Total snoops (count) +system.membus.snoop_fanout::samples 986 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 986 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 987 # Request fanout histogram -system.membus.reqLayer0.occupancy 933500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 986 # Request fanout histogram +system.membus.reqLayer0.occupancy 941000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 6348672 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2754 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2753 # Transaction distribution +system.membus.respLayer1.occupancy 3702674 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2762 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2761 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 411 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 411 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1217 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5861 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 401 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 401 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1229 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 988 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5872 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 149632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1023 # Total snoops (count) +system.toL2Bus.pkt_size::total 150464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1012 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram @@ -2847,23 +2846,23 @@ system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1734981 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 1736971 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2800749 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1466512 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2243496 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1172003 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2220994 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1183494 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2229247 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1196246 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 994999 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 532769 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 762997 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 438748 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 744992 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 415244 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 747996 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 406758 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 564228327..67fefac90 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,115 +1,1160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 262793500 # Number of ticks simulated -final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000260 # Number of seconds simulated +sim_ticks 260037500 # Number of ticks simulated +final_tick 260037500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1021127 # Simulator instruction rate (inst/s) -host_op_rate 1021105 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 404381057 # Simulator tick rate (ticks/s) -host_mem_usage 299844 # Number of bytes of host memory used -host_seconds 0.65 # Real time elapsed on the host -sim_insts 663567 # Number of instructions simulated -sim_ops 663567 # Number of ops (including micro ops) simulated +host_inst_rate 961598 # Simulator instruction rate (inst/s) +host_op_rate 961579 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379344878 # Simulator tick rate (ticks/s) +host_mem_usage 302744 # Number of bytes of host memory used +host_seconds 0.69 # Real time elapsed on the host +sim_insts 659142 # Number of instructions simulated +sim_ops 659142 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 61 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 430 # Transaction distribution -system.membus.trans_dist::ReadResp 430 # Transaction distribution -system.membus.trans_dist::UpgradeReq 272 # Transaction distribution -system.membus.trans_dist::UpgradeResp 77 # Transaction distribution -system.membus.trans_dist::ReadExReq 208 # Transaction distribution -system.membus.trans_dist::ReadExResp 142 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 261 # Total snoops (count) -system.membus.snoop_fanout::samples 915 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 915 # Request fanout histogram -system.membus.reqLayer0.occupancy 852796 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.physmem.bw_read::cpu0.inst 70143729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40609527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 1722828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3691775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 15013219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5660722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 246118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3691775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140779695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 70143729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 1722828 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 15013219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 246118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 87125895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 70143729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40609527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1722828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3691775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 15013219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5660722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 246118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3691775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 140779695 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.workload.num_syscalls 89 # Number of system calls +system.cpu0.numCycles 520075 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 157392 # Number of instructions committed +system.cpu0.committedOps 157392 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108420 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_func_calls 390 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 25835 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108420 # number of integer instructions +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_int_register_reads 313418 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110026 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_mem_refs 73430 # number of memory refs +system.cpu0.num_load_insts 48613 # Number of load instructions +system.cpu0.num_store_insts 24817 # Number of store instructions +system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu0.num_busy_cycles 520074.998000 # Number of busy cycles +system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu0.Branches 26700 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23427 14.88% 14.88% # Class of executed instruction +system.cpu0.op_class::IntAlu 60513 38.43% 53.31% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::MemRead 48697 30.93% 84.24% # Class of executed instruction +system.cpu0.op_class::MemWrite 24817 15.76% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 157454 # Class of executed instruction +system.cpu0.dcache.tags.replacements 2 # number of replacements +system.cpu0.dcache.tags.tagsinuse 145.649829 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 72898 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 436.514970 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.649829 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284472 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284472 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 293953 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 293953 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48433 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48433 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24583 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24583 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 73016 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73016 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73016 # number of overall hits +system.cpu0.dcache.overall_hits::total 73016 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses +system.cpu0.dcache.overall_misses::total 353 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4637996 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4637996 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6976000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11613996 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11613996 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11613996 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11613996 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48603 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48603 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24766 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24766 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 73369 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73369 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73369 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73369 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003498 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003498 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007389 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007389 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004811 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004811 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004811 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004811 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27282.329412 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27282.329412 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38120.218579 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38120.218579 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32900.838527 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32900.838527 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4372004 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4372004 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6701500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6701500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11073504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11073504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11073504 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11073504 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003498 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003498 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007389 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007389 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004811 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004811 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25717.670588 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25717.670588 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36620.218579 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36620.218579 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12307.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12307.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 212.581030 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 156988 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 336.162741 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.581030 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415197 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.415197 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 157922 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 157922 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 156988 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 156988 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 156988 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 156988 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 156988 # number of overall hits +system.cpu0.icache.overall_hits::total 156988 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18041500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18041500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18041500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18041500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18041500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18041500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 157455 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 157455 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 157455 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 157455 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 157455 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 157455 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002966 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002966 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002966 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002966 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002966 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002966 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38632.762313 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38632.762313 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38632.762313 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38632.762313 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17341000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17341000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17341000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17341000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17341000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17341000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002966 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002966 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002966 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37132.762313 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.numCycles 520075 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 168980 # Number of instructions committed +system.cpu1.committedOps 168980 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 110320 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 637 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 33339 # number of instructions that are conditional controls +system.cpu1.num_int_insts 110320 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 270098 # number of times the integer registers were read +system.cpu1.num_int_register_writes 102062 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_mem_refs 53149 # number of memory refs +system.cpu1.num_load_insts 40825 # Number of load instructions +system.cpu1.num_store_insts 12324 # Number of store instructions +system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles +system.cpu1.num_busy_cycles 452347.998260 # Number of busy cycles +system.cpu1.not_idle_fraction 0.869775 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.130225 # Percentage of idle cycles +system.cpu1.Branches 34992 # Number of branches fetched +system.cpu1.op_class::No_OpClass 25772 15.25% 15.25% # Class of executed instruction +system.cpu1.op_class::IntAlu 74368 44.00% 59.25% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::MemRead 56548 33.46% 92.71% # Class of executed instruction +system.cpu1.op_class::MemWrite 12324 7.29% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 169012 # Class of executed instruction +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 25.995164 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 26990 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 899.666667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.995164 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050772 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050772 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 212815 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 212815 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 40655 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40655 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 12144 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 12144 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 52799 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 52799 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 52799 # number of overall hits +system.cpu1.dcache.overall_hits::total 52799 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 162 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 162 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses +system.cpu1.dcache.overall_misses::total 270 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2619475 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2619475 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1982498 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1982498 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 237000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4601973 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4601973 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4601973 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4601973 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 40817 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 40817 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 12252 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 12252 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 53069 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 53069 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 53069 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 53069 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003969 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003969 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008815 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008815 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005088 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005088 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005088 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005088 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16169.598765 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16169.598765 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18356.462963 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18356.462963 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4232.142857 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17044.344444 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17044.344444 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 162 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2358525 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2358525 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1818502 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1818502 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 153000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4177027 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4177027 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4177027 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4177027 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003969 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003969 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008815 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008815 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005088 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005088 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14558.796296 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14558.796296 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16837.981481 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16837.981481 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2732.142857 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 280 # number of replacements +system.cpu1.icache.tags.tagsinuse 65.697365 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 168647 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 460.784153 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.697365 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128315 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.128315 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 169379 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 169379 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 168647 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 168647 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 168647 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 168647 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 168647 # number of overall hits +system.cpu1.icache.overall_hits::total 168647 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses +system.cpu1.icache.overall_misses::total 366 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5333988 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5333988 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5333988 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5333988 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5333988 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5333988 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 169013 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 169013 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 169013 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 169013 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 169013 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 169013 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002166 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002166 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002166 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002166 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14573.737705 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14573.737705 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14573.737705 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14573.737705 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4778012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4778012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4778012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4778012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4778012 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4778012 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13054.677596 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.numCycles 520075 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.committedInsts 164869 # Number of instructions committed +system.cpu2.committedOps 164869 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 110069 # Number of integer alu accesses +system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu2.num_func_calls 637 # number of times a function call or return occured +system.cpu2.num_conditional_control_insts 31409 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110069 # number of integer instructions +system.cpu2.num_fp_insts 0 # number of float instructions +system.cpu2.num_int_register_reads 276820 # number of times the integer registers were read +system.cpu2.num_int_register_writes 105549 # number of times the integer registers were written +system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu2.num_mem_refs 54829 # number of memory refs +system.cpu2.num_load_insts 40701 # Number of load instructions +system.cpu2.num_store_insts 14128 # Number of store instructions +system.cpu2.num_idle_cycles 67985.001739 # Number of idle cycles +system.cpu2.num_busy_cycles 452089.998261 # Number of busy cycles +system.cpu2.not_idle_fraction 0.869278 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.130722 # Percentage of idle cycles +system.cpu2.Branches 33062 # Number of branches fetched +system.cpu2.op_class::No_OpClass 23842 14.46% 14.46% # Class of executed instruction +system.cpu2.op_class::IntAlu 74244 45.02% 59.48% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::MemRead 52687 31.95% 91.43% # Class of executed instruction +system.cpu2.op_class::MemWrite 14128 8.57% 100.00% # Class of executed instruction +system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu2.op_class::total 164901 # Class of executed instruction +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 27.767003 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 30481 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1051.068966 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.767003 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054232 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.054232 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 219531 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 219531 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40534 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40534 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 13949 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 13949 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 54483 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 54483 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 54483 # number of overall hits +system.cpu2.dcache.overall_hits::total 54483 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 159 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses +system.cpu2.dcache.overall_misses::total 267 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2767480 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2767480 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2022500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2022500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 237000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4789980 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4789980 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4789980 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4789980 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40693 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40693 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 14057 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 14057 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 54750 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 54750 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 54750 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 54750 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003907 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003907 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007683 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.007683 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004877 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004877 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004877 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004877 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17405.534591 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17405.534591 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18726.851852 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18726.851852 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4232.142857 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17940 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17940 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17940 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17940 # average overall miss latency +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2514020 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2514020 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1860500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1860500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 153000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4374520 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 4374520 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4374520 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4374520 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003907 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003907 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007683 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007683 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004877 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004877 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15811.446541 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15811.446541 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17226.851852 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17226.851852 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2732.142857 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.icache.tags.replacements 280 # number of replacements +system.cpu2.icache.tags.tagsinuse 70.145256 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 164536 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 449.551913 # Average number of references to valid blocks. +system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.145256 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137002 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.137002 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 165268 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 165268 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 164536 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 164536 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 164536 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 164536 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 164536 # number of overall hits +system.cpu2.icache.overall_hits::total 164536 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses +system.cpu2.icache.overall_misses::total 366 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7445997 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7445997 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7445997 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7445997 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7445997 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7445997 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 164902 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 164902 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 164902 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 164902 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 164902 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 164902 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20344.254098 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 20344.254098 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 20344.254098 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 20344.254098 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6894003 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6894003 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6894003 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6894003 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6894003 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6894003 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 18836.073770 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.numCycles 520075 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.committedInsts 167901 # Number of instructions committed +system.cpu3.committedOps 167901 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 110672 # Number of integer alu accesses +system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu3.num_func_calls 637 # number of times a function call or return occured +system.cpu3.num_conditional_control_insts 32621 # number of instructions that are conditional controls +system.cpu3.num_int_insts 110672 # number of integer instructions +system.cpu3.num_fp_insts 0 # number of float instructions +system.cpu3.num_int_register_reads 274378 # number of times the integer registers were read +system.cpu3.num_int_register_writes 104026 # number of times the integer registers were written +system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu3.num_mem_refs 54219 # number of memory refs +system.cpu3.num_load_insts 41000 # Number of load instructions +system.cpu3.num_store_insts 13219 # Number of store instructions +system.cpu3.num_idle_cycles 68239.001738 # Number of idle cycles +system.cpu3.num_busy_cycles 451835.998262 # Number of busy cycles +system.cpu3.not_idle_fraction 0.868790 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.131210 # Percentage of idle cycles +system.cpu3.Branches 34277 # Number of branches fetched +system.cpu3.op_class::No_OpClass 25056 14.92% 14.92% # Class of executed instruction +system.cpu3.op_class::IntAlu 74547 44.39% 59.31% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::MemRead 55111 32.82% 92.13% # Class of executed instruction +system.cpu3.op_class::MemWrite 13219 7.87% 100.00% # Class of executed instruction +system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu3.op_class::total 167933 # Class of executed instruction +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 26.810589 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 28657 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 988.172414 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.810589 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052364 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.052364 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 217093 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 217093 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40832 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40832 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 13038 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 13038 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 53870 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 53870 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 53870 # number of overall hits +system.cpu3.dcache.overall_hits::total 53870 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 160 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 160 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses +system.cpu3.dcache.overall_misses::total 268 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2513476 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2513476 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2024000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2024000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 244500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 244500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 4537476 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4537476 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4537476 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4537476 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 40992 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 40992 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 13146 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 13146 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 54138 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 54138 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 54138 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 54138 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003903 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003903 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008215 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.008215 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.816901 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004950 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004950 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004950 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004950 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15709.225000 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15709.225000 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18740.740741 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 18740.740741 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4215.517241 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4215.517241 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16930.880597 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16930.880597 # average overall miss latency +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2256524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2256524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1862000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1862000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 157500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 157500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4118524 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4118524 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4118524 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4118524 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003903 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003903 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008215 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008215 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004950 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004950 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14103.275000 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14103.275000 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17240.740741 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17240.740741 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2715.517241 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2715.517241 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 15367.626866 # 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Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 168301 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 168301 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 167567 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 167567 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 167567 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 167567 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 167567 # number of overall hits +system.cpu3.icache.overall_hits::total 167567 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 367 # 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Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id @@ -118,10 +1163,10 @@ system.l2c.tags.tag_accesses 15709 # Nu system.l2c.tags.data_accesses 15709 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 302 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 3 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits @@ -131,91 +1176,91 @@ system.l2c.UpgradeReq_hits::cpu0.data 2 # nu system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 302 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 3 # 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average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40624.750000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40525.922078 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41107.142857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40766.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40785.714286 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40616.197183 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution +system.membus.trans_dist::ReadReq 430 # Transaction distribution +system.membus.trans_dist::ReadResp 430 # Transaction distribution +system.membus.trans_dist::UpgradeReq 272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 77 # Transaction distribution +system.membus.trans_dist::ReadExReq 208 # Transaction distribution +system.membus.trans_dist::ReadExResp 142 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 261 # Total snoops (count) +system.membus.snoop_fanout::samples 914 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 914 # Request fanout histogram +system.membus.reqLayer0.occupancy 679142 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2961502 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2217 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2217 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution @@ -509,23 +1579,23 @@ system.toL2Bus.trans_dist::ReadExResp 429 # Tr system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4812 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1037 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2929 # Request fanout histogram +system.toL2Bus.snoops 1029 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2921 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -536,1099 +1606,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 2929 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 2921 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2929 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2921 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1466989 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) -system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 525587 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158574 # Number of instructions committed -system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls -system.cpu0.num_int_insts 109208 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 74021 # number of memory refs -system.cpu0.num_load_insts 49007 # Number of load instructions -system.cpu0.num_store_insts 25014 # Number of store instructions -system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 525586.998000 # Number of busy cycles -system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26897 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23624 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60907 38.39% 53.29% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 49091 30.95% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 25014 15.77% 100.00% # Class of executed instruction -system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158636 # Class of executed instruction -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.401858 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401858 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 159104 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 159104 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits -system.cpu0.icache.overall_hits::total 158170 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.571907 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571907 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 296317 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 296317 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits -system.cpu0.dcache.overall_hits::total 73607 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 353 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses -system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6973000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6973000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11559981 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11559981 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11559981 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11559981 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38103.825137 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38103.825137 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32747.821530 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32747.821530 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 170 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6607000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6607000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10844019 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10844019 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10844019 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10844019 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36103.825137 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36103.825137 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 525586 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 163471 # Number of instructions committed -system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111731 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read -system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 58020 # number of memory refs -system.cpu1.num_load_insts 41540 # Number of load instructions -system.cpu1.num_store_insts 16480 # Number of store instructions -system.cpu1.num_idle_cycles 69346.869794 # Number of idle cycles -system.cpu1.num_busy_cycles 456239.130206 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles -system.cpu1.Branches 31528 # Number of branches fetched -system.cpu1.op_class::No_OpClass 22316 13.65% 13.65% # Class of executed instruction -system.cpu1.op_class::IntAlu 75095 45.93% 59.58% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::MemRead 49612 30.34% 89.92% # Class of executed instruction -system.cpu1.op_class::MemWrite 16480 10.08% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 163503 # Class of executed instruction -system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 70.017769 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017769 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 163870 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 163870 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits -system.cpu1.icache.overall_hits::total 163138 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses -system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544488 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7544488 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7544488 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7544488 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7544488 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7544488 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20613.355191 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20613.355191 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20613.355191 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20613.355191 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6805512 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6805512 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6805512 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6805512 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6805512 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6805512 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18594.295082 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 27.720301 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720301 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 232288 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 232288 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits -system.cpu1.dcache.overall_hits::total 57685 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses -system.cpu1.dcache.overall_misses::total 263 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 525586 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 164866 # Number of instructions committed -system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112988 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read -system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59208 # number of memory refs -system.cpu2.num_load_insts 42171 # Number of load instructions -system.cpu2.num_store_insts 17037 # Number of store instructions -system.cpu2.num_idle_cycles 69603.869304 # Number of idle cycles -system.cpu2.num_busy_cycles 455982.130696 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867569 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132431 # Percentage of idle cycles -system.cpu2.Branches 31596 # Number of branches fetched -system.cpu2.op_class::No_OpClass 22386 13.58% 13.58% # Class of executed instruction -system.cpu2.op_class::IntAlu 75723 45.92% 59.50% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::MemRead 49752 30.17% 89.67% # Class of executed instruction -system.cpu2.op_class::MemWrite 17037 10.33% 100.00% # Class of executed instruction -system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 164898 # Class of executed instruction -system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 67.625211 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. -system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.625211 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 165265 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 165265 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits -system.cpu2.icache.overall_hits::total 164533 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses -system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251988 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5251988 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5251988 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5251988 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5251988 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5251988 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14349.693989 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14349.693989 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14349.693989 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14349.693989 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510012 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510012 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510012 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4510012 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510012 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4510012 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12322.437158 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.763988 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763988 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 237038 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 237038 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 16865 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 58876 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 58876 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 58876 # number of overall hits -system.cpu2.dcache.overall_hits::total 58876 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 50 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 50 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses -system.cpu2.dcache.overall_misses::total 262 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 16975 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 60 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 60 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 59138 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 59138 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 59138 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 59138 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003605 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003605 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006480 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006480 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 525586 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 176656 # Number of instructions committed -system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls -system.cpu3.num_int_insts 108218 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read -system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 46164 # number of memory refs -system.cpu3.num_load_insts 39753 # Number of load instructions -system.cpu3.num_store_insts 6411 # Number of store instructions -system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles -system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles -system.cpu3.Branches 39890 # Number of branches fetched -system.cpu3.op_class::No_OpClass 30652 17.35% 17.35% # Class of executed instruction -system.cpu3.op_class::IntAlu 73353 41.52% 58.86% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::MemRead 66272 37.51% 96.37% # Class of executed instruction -system.cpu3.op_class::MemWrite 6411 3.63% 100.00% # Class of executed instruction -system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 176688 # Class of executed instruction -system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 65.598702 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. -system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598702 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 177056 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 177056 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 176322 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 176322 # number of overall hits -system.cpu3.icache.overall_hits::total 176322 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses -system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5147499 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5147499 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5147499 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5147499 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5147499 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 176689 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 176689 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 176689 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 176689 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 176689 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 176689 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002077 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002077 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002077 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002077 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002077 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002077 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14025.882834 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14025.882834 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14025.882834 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14025.882834 # average overall miss latency -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # 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number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002077 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.915188 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915188 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050616 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 184905 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 184905 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 45779 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 45779 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 45779 # number of overall hits -system.cpu3.dcache.overall_hits::total 45779 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 183 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 183 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses -system.cpu3.dcache.overall_misses::total 288 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2099000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2099000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 5255473 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 5255473 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 5255473 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 5255473 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 46067 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 46067 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.004604 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19990.476190 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19990.476190 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18248.170139 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18248.170139 # average overall miss latency -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1889000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1889000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661527 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4661527 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661527 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4661527 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17990.476190 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17990.476190 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 503996 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 552488 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 431973 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 550497 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 423980 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 554490 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 428476 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index a27123aa4..4a7304d33 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,195 +1,195 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.001493 # Number of seconds simulated -sim_ticks 1493307500 # Number of ticks simulated -final_tick 1493307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000729 # Number of seconds simulated +sim_ticks 728722500 # Number of ticks simulated +final_tick 728722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 295462472 # Simulator tick rate (ticks/s) -host_mem_usage 222068 # Number of bytes of host memory used -host_seconds 5.05 # Real time elapsed on the host +host_tick_rate 162031375 # Simulator tick rate (ticks/s) +host_mem_usage 277108 # Number of bytes of host memory used +host_seconds 4.50 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 74794 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 78736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 78807 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 78188 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 77250 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 74477 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78325 # Number of bytes read from this memory -system.physmem.bytes_read::total 619989 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 384000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5518 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5402 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5514 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5530 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5340 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5402 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5377 # Number of bytes written to this memory -system.physmem.bytes_written::total 427483 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10974 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10915 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6000 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5518 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5402 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5400 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5514 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5530 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5340 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5402 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49483 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 50086134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 52725912 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 52773458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 52358941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 51730806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 49873854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 53178599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 52450684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 415178388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 257147306 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 3695153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 3617473 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 3616134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 3692475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 3703189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 3575955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 3617473 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 3600732 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 286265890 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 257147306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 53781288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 56343385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 56389592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 56051416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 55433995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 53449809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 56796072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 56051416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 701444277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 79470 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 78418 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 80729 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80022 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 80096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 78976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 78470 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 78262 # Number of bytes read from this memory +system.physmem.bytes_read::total 634443 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 400000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5381 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5473 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5390 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5494 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5433 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5395 # Number of bytes written to this memory +system.physmem.bytes_written::total 443379 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10733 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10873 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10934 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11041 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87540 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5381 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5473 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5390 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5494 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5433 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5395 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49629 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 109053858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 107610236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 110781539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 109811348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 109912896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 108375959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 107681593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 107396162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 870623591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 548905791 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7384155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 7470608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7510403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 7396506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 7367688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7539221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7455513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7403367 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 608433251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 548905791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 116438013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 115080844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 118291942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 117207853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 117280583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 115915180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 115137106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 114799529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479056843 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99767 # number of read accesses completed -system.cpu0.num_writes 55259 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22696 # number of replacements -system.cpu0.l1c.tags.tagsinuse 395.365301 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13357 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 23083 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.578651 # Average number of references to valid blocks. +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 54791 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22240 # number of replacements +system.cpu0.l1c.tags.tagsinuse 394.087405 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13441 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.593789 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 395.365301 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.772198 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.772198 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 272 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 339665 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 339665 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8708 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8708 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1150 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1150 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9858 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9858 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9858 # number of overall hits -system.cpu0.l1c.overall_hits::total 9858 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36982 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36982 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23775 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23775 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60757 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60757 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60757 # number of overall misses -system.cpu0.l1c.overall_misses::total 60757 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 2501825237 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 2501825237 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1853114266 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1853114266 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 4354939503 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 4354939503 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 4354939503 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 4354939503 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45690 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45690 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24925 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24925 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70615 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70615 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70615 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70615 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809411 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.809411 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953862 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953862 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860398 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860398 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860398 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860398 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67649.809015 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 67649.809015 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 77943.817708 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 77943.817708 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 71677.987771 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 71677.987771 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 71677.987771 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 71677.987771 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 2197094 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 394.087405 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.769702 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.769702 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337290 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337290 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8682 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8682 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1111 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1111 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9793 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9793 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9793 # number of overall hits +system.cpu0.l1c.overall_hits::total 9793 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36727 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36727 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23639 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23639 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60366 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60366 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60366 # number of overall misses +system.cpu0.l1c.overall_misses::total 60366 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1016702315 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1016702315 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 918792240 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 918792240 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1935494555 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1935494555 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1935494555 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1935494555 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45409 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45409 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24750 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24750 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70159 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70159 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70159 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70159 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808804 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.808804 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955111 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955111 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860417 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860417 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860417 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860417 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27682.694339 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 27682.694339 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38867.644147 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 38867.644147 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 32062.660355 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 32062.660355 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 32062.660355 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 32062.660355 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1074391 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 60506 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61970 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.312002 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.337276 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9747 # number of writebacks -system.cpu0.l1c.writebacks::total 9747 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36982 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36982 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23775 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23775 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60757 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60757 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60757 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60757 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 2423727133 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2423727133 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1803343082 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1803343082 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 4227070215 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 4227070215 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 4227070215 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 4227070215 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1077807594 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1077807594 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 4091615147 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 4091615147 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5169422741 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5169422741 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953862 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953862 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860398 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860398 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860398 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860398 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65538.022092 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65538.022092 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 75850.392513 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 75850.392513 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9656 # number of writebacks +system.cpu0.l1c.writebacks::total 9656 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36727 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36727 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23639 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23639 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60366 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60366 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60366 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60366 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 960514497 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 960514497 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 882874166 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 882874166 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1843388663 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1843388663 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1843388663 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1843388663 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 755586835 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 755586835 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1939842714 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1939842714 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2695429549 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2695429549 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808804 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808804 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955111 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955111 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860417 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860417 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26152.816647 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26152.816647 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37348.202800 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37348.202800 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 54988 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22397 # number of replacements -system.cpu1.l1c.tags.tagsinuse 395.796271 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13630 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22804 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.597702 # Average number of references to valid blocks. +system.cpu1.num_reads 99410 # number of read accesses completed +system.cpu1.num_writes 55132 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22295 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.820804 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13496 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22679 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.595088 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 395.796271 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.773040 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.773040 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 269 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338465 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338465 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8882 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8882 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1141 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1141 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 10023 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 10023 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 10023 # number of overall hits -system.cpu1.l1c.overall_hits::total 10023 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36639 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36639 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23767 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23767 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60406 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60406 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60406 # number of overall misses -system.cpu1.l1c.overall_misses::total 60406 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 2485954076 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 2485954076 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1862028208 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1862028208 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 4347982284 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 4347982284 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 4347982284 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 4347982284 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24908 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70429 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70429 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70429 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70429 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804881 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.804881 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954191 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954191 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857686 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857686 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857686 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857686 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67849.943394 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 67849.943394 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78345.109101 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 78345.109101 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 71979.311393 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 71979.311393 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 71979.311393 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 71979.311393 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 2202198 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 393.820804 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.769181 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.769181 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338268 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338268 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8726 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8726 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1171 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1171 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9897 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9897 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9897 # number of overall hits +system.cpu1.l1c.overall_hits::total 9897 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36573 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36573 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23897 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23897 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60470 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60470 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60470 # number of overall misses +system.cpu1.l1c.overall_misses::total 60470 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1020722242 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1020722242 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 921634198 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 921634198 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1942356440 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1942356440 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1942356440 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1942356440 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45299 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25068 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25068 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70367 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70367 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70367 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70367 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807369 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.807369 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953287 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953287 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859352 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859352 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859352 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859352 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27909.174582 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 27909.174582 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38566.941373 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 38566.941373 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 32120.992889 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 32120.992889 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 32120.992889 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 32120.992889 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1066797 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 60277 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61607 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.534632 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.316165 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks -system.cpu1.l1c.writebacks::total 9809 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36639 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36639 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23767 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23767 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60406 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60406 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60406 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60406 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2408616840 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2408616840 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1812196150 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1812196150 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 4220812990 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 4220812990 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4220812990 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 4220812990 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1084723149 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1084723149 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 4036922188 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 4036922188 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5121645337 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5121645337 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804881 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804881 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954191 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954191 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857686 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857686 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857686 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857686 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65739.153361 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65739.153361 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76248.417975 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76248.417975 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9694 # number of writebacks +system.cpu1.l1c.writebacks::total 9694 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36573 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36573 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23897 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23897 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60470 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60470 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60470 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60470 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 964784026 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 964784026 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 885327122 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 885327122 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1850111148 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1850111148 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1850111148 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1850111148 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 740106955 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 740106955 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1954561172 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1954561172 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2694668127 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2694668127 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807369 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807369 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953287 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953287 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859352 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859352 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26379.679709 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26379.679709 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37047.626146 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37047.626146 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99645 # number of read accesses completed -system.cpu2.num_writes 55347 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22638 # number of replacements -system.cpu2.l1c.tags.tagsinuse 395.541236 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13666 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 23033 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.593323 # Average number of references to valid blocks. +system.cpu2.num_reads 99274 # number of read accesses completed +system.cpu2.num_writes 54884 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22456 # number of replacements +system.cpu2.l1c.tags.tagsinuse 393.843880 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13581 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22857 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.594172 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 395.541236 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.772541 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.772541 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 271 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 339287 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 339287 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8844 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8844 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1130 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1130 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9974 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9974 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9974 # number of overall hits -system.cpu2.l1c.overall_hits::total 9974 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36761 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36761 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23865 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23865 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60626 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60626 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60626 # number of overall misses -system.cpu2.l1c.overall_misses::total 60626 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 2497854261 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 2497854261 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1869962350 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1869962350 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 4367816611 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 4367816611 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 4367816611 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 4367816611 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45605 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45605 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70600 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70600 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70600 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70600 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806074 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806074 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954791 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954791 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858725 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858725 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858725 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858725 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67948.485106 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 67948.485106 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78355.849571 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 78355.849571 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 72045.271187 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 72045.271187 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 72045.271187 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 72045.271187 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 2198319 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 393.843880 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.769226 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.769226 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 373 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337451 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337451 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8813 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8813 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1134 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1134 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9947 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9947 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9947 # number of overall hits +system.cpu2.l1c.overall_hits::total 9947 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36457 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36457 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23816 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23816 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60273 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60273 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60273 # number of overall misses +system.cpu2.l1c.overall_misses::total 60273 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1014308258 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1014308258 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 924910230 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 924910230 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1939218488 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1939218488 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1939218488 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1939218488 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45270 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45270 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24950 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70220 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70220 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70220 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70220 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805324 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805324 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954549 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954549 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858345 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858345 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858345 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858345 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27822.043997 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 27822.043997 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38835.666359 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 38835.666359 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 32173.916812 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 32173.916812 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 32173.916812 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 32173.916812 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1061117 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 60200 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 61178 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.516927 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.344748 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9871 # number of writebacks -system.cpu2.l1c.writebacks::total 9871 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36761 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36761 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23865 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23865 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60626 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60626 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60626 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60626 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2420242117 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2420242117 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1819999216 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1819999216 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4240241333 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 4240241333 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4240241333 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 4240241333 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1065167222 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1065167222 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3984850744 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3984850744 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 5050017966 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 5050017966 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806074 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806074 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954791 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954791 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858725 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858725 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65837.221974 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65837.221974 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76262.275969 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76262.275969 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 69940.971415 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9940 # number of writebacks +system.cpu2.l1c.writebacks::total 9940 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36457 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36457 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23816 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23816 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60273 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60273 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60273 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60273 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 958559384 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 958559384 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 888663772 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 888663772 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1847223156 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1847223156 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1847223156 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1847223156 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 735013046 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 735013046 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1939097223 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1939097223 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2674110269 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2674110269 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805324 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805324 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954549 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954549 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858345 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858345 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858345 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858345 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26292.876101 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26292.876101 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37313.729090 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37313.729090 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98252 # number of read accesses completed -system.cpu3.num_writes 55235 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22381 # number of replacements -system.cpu3.l1c.tags.tagsinuse 396.107709 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13213 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22778 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.580077 # Average number of references to valid blocks. +system.cpu3.num_reads 99869 # number of read accesses completed +system.cpu3.num_writes 54874 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22370 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.431339 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13240 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22771 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.581441 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 396.107709 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.773648 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.773648 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 335638 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 335638 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8470 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8470 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1156 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1156 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9626 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9626 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9626 # number of overall hits -system.cpu3.l1c.overall_hits::total 9626 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36183 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36183 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23969 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23969 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60152 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60152 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60152 # number of overall misses -system.cpu3.l1c.overall_misses::total 60152 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 2454128819 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 2454128819 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1887224651 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1887224651 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 4341353470 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 4341353470 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 4341353470 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 4341353470 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44653 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44653 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25125 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25125 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 69778 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 69778 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 69778 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 69778 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.810315 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.810315 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953990 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953990 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.862048 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.862048 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.862048 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.862048 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67825.465522 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 67825.465522 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78736.061204 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 78736.061204 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 72173.052766 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 72173.052766 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 72173.052766 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 72173.052766 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 2184377 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.431339 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.768421 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.768421 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 336829 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 336829 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8648 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8648 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1128 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1128 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9776 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9776 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9776 # number of overall hits +system.cpu3.l1c.overall_hits::total 9776 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36458 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36458 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23788 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23788 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60246 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60246 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60246 # number of overall misses +system.cpu3.l1c.overall_misses::total 60246 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1012578921 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1012578921 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 920459168 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 920459168 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1933038089 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1933038089 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1933038089 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1933038089 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45106 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45106 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24916 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24916 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70022 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70022 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70022 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70022 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808274 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808274 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954728 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954728 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860387 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860387 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860387 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860387 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27773.847194 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 27773.847194 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38694.264671 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 38694.264671 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 32085.749909 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 32085.749909 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 32085.749909 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 32085.749909 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1072737 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 59819 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61848 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.516441 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.344732 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9931 # number of writebacks -system.cpu3.l1c.writebacks::total 9931 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36183 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36183 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23969 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60152 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60152 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60152 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60152 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 2377731501 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2377731501 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1837004571 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1837004571 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 4214736072 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 4214736072 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4214736072 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 4214736072 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1072192160 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1072192160 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 4016794612 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 4016794612 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 5088986772 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 5088986772 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.810315 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.810315 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953990 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953990 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.862048 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.862048 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.862048 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.862048 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65714.050825 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.050825 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76640.851558 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76640.851558 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 70068.095358 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9757 # number of writebacks +system.cpu3.l1c.writebacks::total 9757 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36458 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36458 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23788 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23788 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60246 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60246 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60246 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60246 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 956791627 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 956791627 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 884289164 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 884289164 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1841080791 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1841080791 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1841080791 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1841080791 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 756050699 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 756050699 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1926314708 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1926314708 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2682365407 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2682365407 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808274 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808274 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954728 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954728 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860387 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860387 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860387 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860387 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26243.667426 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26243.667426 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37173.749958 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37173.749958 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30559.386366 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99562 # number of read accesses completed -system.cpu4.num_writes 54813 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22626 # number of replacements -system.cpu4.l1c.tags.tagsinuse 395.713168 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13359 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 23019 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.580347 # Average number of references to valid blocks. +system.cpu4.num_reads 98774 # number of read accesses completed +system.cpu4.num_writes 54829 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22505 # number of replacements +system.cpu4.l1c.tags.tagsinuse 395.050000 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13373 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22916 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.583566 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 395.713168 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.772877 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.772877 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337886 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337886 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8660 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8660 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1130 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1130 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9790 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9790 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9790 # number of overall hits -system.cpu4.l1c.overall_hits::total 9790 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36748 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36748 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23725 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23725 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60473 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60473 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60473 # number of overall misses -system.cpu4.l1c.overall_misses::total 60473 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 2479360793 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 2479360793 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1851125976 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1851125976 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 4330486769 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 4330486769 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 4330486769 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 4330486769 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45408 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45408 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24855 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24855 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70263 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70263 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70263 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70263 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809285 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.809285 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954536 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954536 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.860666 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.860666 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.860666 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.860666 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67469.271607 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 67469.271607 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 78024.277176 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 78024.277176 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 71610.251997 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 71610.251997 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 71610.251997 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 71610.251997 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 2193235 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 395.050000 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.771582 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.771582 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337873 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337873 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8531 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8531 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1209 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1209 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9740 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9740 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9740 # number of overall hits +system.cpu4.l1c.overall_hits::total 9740 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36518 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36518 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24001 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24001 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60519 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60519 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60519 # number of overall misses +system.cpu4.l1c.overall_misses::total 60519 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1017641988 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1017641988 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 934552595 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 934552595 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1952194583 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1952194583 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1952194583 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1952194583 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25210 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25210 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70259 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70259 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70259 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70259 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.810628 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.810628 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952043 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952043 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.861370 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.861370 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.861370 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.861370 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27866.859850 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 27866.859850 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38938.069039 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 38938.069039 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 32257.548588 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 32257.548588 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 32257.548588 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 32257.548588 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1063629 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 60223 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61473 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.418561 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 17.302377 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9708 # number of writebacks -system.cpu4.l1c.writebacks::total 9708 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36748 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36748 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23725 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23725 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60473 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60473 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60473 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60473 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 2401684855 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 2401684855 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1801504708 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1801504708 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 4203189563 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 4203189563 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 4203189563 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 4203189563 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1091799507 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1091799507 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 4121360584 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 4121360584 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 5213160091 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5213160091 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809285 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809285 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954536 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954536 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860666 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.860666 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860666 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.860666 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65355.525607 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65355.525607 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 75932.759031 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 75932.759031 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69505.226514 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9914 # number of writebacks +system.cpu4.l1c.writebacks::total 9914 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36518 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36518 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24001 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24001 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60519 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60519 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60519 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60519 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 961775196 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 961775196 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 898026173 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 898026173 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1859801369 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1859801369 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1859801369 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1859801369 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 728267014 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 728267014 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1921671690 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1921671690 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2649938704 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2649938704 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.810628 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.810628 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952043 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952043 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861370 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.861370 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861370 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.861370 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26337.017252 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26337.017252 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37416.198200 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37416.198200 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30730.867480 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98672 # number of read accesses completed -system.cpu5.num_writes 54809 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22472 # number of replacements -system.cpu5.l1c.tags.tagsinuse 396.252013 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13351 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22867 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.583854 # Average number of references to valid blocks. +system.cpu5.num_reads 99305 # number of read accesses completed +system.cpu5.num_writes 54996 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22529 # number of replacements +system.cpu5.l1c.tags.tagsinuse 394.380527 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13364 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.582792 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 396.252013 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.773930 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.773930 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 336301 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 336301 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8563 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8563 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1084 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1084 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9647 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9647 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9647 # number of overall hits -system.cpu5.l1c.overall_hits::total 9647 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36411 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36411 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23882 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23882 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60293 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60293 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60293 # number of overall misses -system.cpu5.l1c.overall_misses::total 60293 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 2486246489 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 2486246489 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1881159650 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1881159650 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 4367406139 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 4367406139 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 4367406139 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 4367406139 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44974 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44974 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24966 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24966 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69940 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69940 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69940 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69940 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.809601 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.809601 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956581 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.956581 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.862067 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.862067 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.862067 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.862067 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 68282.840048 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 68282.840048 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78768.932669 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 78768.932669 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 72436.371370 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 72436.371370 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 72436.371370 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 72436.371370 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 2200429 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 394.380527 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.770274 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.770274 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337468 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337468 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8640 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8640 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1161 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1161 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9801 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9801 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9801 # number of overall hits +system.cpu5.l1c.overall_hits::total 9801 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36580 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36580 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23798 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23798 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60378 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60378 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60378 # number of overall misses +system.cpu5.l1c.overall_misses::total 60378 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1015127570 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1015127570 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 927119253 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 927119253 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1942246823 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1942246823 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1942246823 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1942246823 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45220 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45220 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24959 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70179 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70179 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70179 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70179 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808934 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808934 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953484 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953484 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860343 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860343 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860343 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860343 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27750.890377 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 27750.890377 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38957.864232 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 38957.864232 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 32168.121220 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 32168.121220 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 32168.121220 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 32168.121220 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1066593 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 60083 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61522 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.623155 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 17.336774 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9941 # number of writebacks -system.cpu5.l1c.writebacks::total 9941 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36411 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36411 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23882 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23882 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60293 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60293 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60293 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60293 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 2409268523 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 2409268523 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1831238342 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1831238342 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 4240506865 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 4240506865 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 4240506865 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 4240506865 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1068031665 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1068031665 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 3938248323 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 3938248323 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 5006279988 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 5006279988 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.809601 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.809601 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956581 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956581 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.862067 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.862067 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.862067 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.862067 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 66168.699651 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 66168.699651 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76678.600703 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76678.600703 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 70331.661470 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9775 # number of writebacks +system.cpu5.l1c.writebacks::total 9775 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36580 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36580 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23798 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23798 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60378 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60378 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60378 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60378 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 959195658 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 959195658 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 890981649 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 890981649 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1850177307 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1850177307 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1850177307 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1850177307 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 738489342 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 738489342 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1963680665 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1963680665 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2702170007 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2702170007 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808934 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808934 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953484 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953484 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860343 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860343 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860343 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860343 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26221.860525 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26221.860525 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37439.349903 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37439.349903 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30643.236063 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99484 # number of read accesses completed -system.cpu6.num_writes 54995 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22115 # number of replacements -system.cpu6.l1c.tags.tagsinuse 396.164371 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13666 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22491 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.607621 # Average number of references to valid blocks. +system.cpu6.num_reads 99342 # number of read accesses completed +system.cpu6.num_writes 54737 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22276 # number of replacements +system.cpu6.l1c.tags.tagsinuse 393.125800 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13636 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22683 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.601155 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 396.164371 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.773759 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.773759 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 376 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338129 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338129 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8797 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8797 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1207 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1207 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 10004 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 10004 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 10004 # number of overall hits -system.cpu6.l1c.overall_hits::total 10004 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36456 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36456 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23912 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23912 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60368 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60368 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60368 # number of overall misses -system.cpu6.l1c.overall_misses::total 60368 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 2466938162 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 2466938162 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1877191258 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1877191258 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 4344129420 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 4344129420 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 4344129420 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 4344129420 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45253 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45253 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25119 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25119 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70372 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70372 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805604 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805604 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951949 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.951949 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.857841 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.857841 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.857841 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.857841 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 67668.920397 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 67668.920397 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78504.150970 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 78504.150970 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 71960.797442 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 71960.797442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 71960.797442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 71960.797442 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 2202006 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 393.125800 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.767824 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.767824 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337855 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337855 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8799 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8799 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1154 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1154 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9953 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9953 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9953 # number of overall hits +system.cpu6.l1c.overall_hits::total 9953 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36552 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36552 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23805 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23805 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60357 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60357 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60357 # number of overall misses +system.cpu6.l1c.overall_misses::total 60357 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1017275565 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1017275565 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 923819144 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 923819144 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1941094709 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1941094709 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1941094709 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1941094709 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45351 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45351 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24959 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70310 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70310 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805980 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805980 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953764 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953764 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858441 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858441 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858441 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858441 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27830.913903 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 27830.913903 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38807.777526 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 38807.777526 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 32160.225144 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 32160.225144 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 32160.225144 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 32160.225144 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1069531 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 60316 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61695 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 36.507825 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 17.335781 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9723 # number of writebacks -system.cpu6.l1c.writebacks::total 9723 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36456 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36456 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23912 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23912 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60368 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60368 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 2389944958 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 2389944958 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1827130108 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1827130108 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 4217075066 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 4217075066 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 4217075066 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 4217075066 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1090860454 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1090860454 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 4034817264 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 4034817264 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 5125677718 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 5125677718 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805604 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805604 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951949 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951949 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857841 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.857841 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857841 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.857841 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 65556.971637 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 65556.971637 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76410.593342 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76410.593342 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 69856.133481 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9809 # number of writebacks +system.cpu6.l1c.writebacks::total 9809 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36552 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36552 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23805 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23805 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60357 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60357 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60357 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60357 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 961362717 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 961362717 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 887609672 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 887609672 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1848972389 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1848972389 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1848972389 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1848972389 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 744037855 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 744037855 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1951627727 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1951627727 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2695665582 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2695665582 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805980 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805980 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953764 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953764 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858441 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858441 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858441 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858441 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26301.234324 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26301.234324 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37286.690695 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37286.690695 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30633.934573 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98571 # number of read accesses completed -system.cpu7.num_writes 54904 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22064 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.954913 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13425 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22470 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.597463 # Average number of references to valid blocks. +system.cpu7.num_reads 99062 # number of read accesses completed +system.cpu7.num_writes 54686 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22200 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.753023 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13454 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22591 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.595547 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.954913 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.771396 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.771396 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 274 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 334895 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 334895 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8604 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8604 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1157 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1157 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9761 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9761 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9761 # number of overall hits -system.cpu7.l1c.overall_hits::total 9761 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35973 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35973 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23939 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23939 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59912 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59912 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59912 # number of overall misses -system.cpu7.l1c.overall_misses::total 59912 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 2452832630 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 2452832630 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1890055104 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1890055104 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 4342887734 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 4342887734 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 4342887734 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 4342887734 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44577 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44577 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25096 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25096 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69673 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69673 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69673 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69673 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806986 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806986 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953897 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953897 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859903 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859903 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859903 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859903 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 68185.378756 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 68185.378756 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 78952.968127 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 78952.968127 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 72487.777641 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 72487.777641 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 72487.777641 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 72487.777641 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 2195658 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 394.753023 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.771002 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.771002 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337139 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337139 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8690 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8690 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1182 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1182 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9872 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9872 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9872 # number of overall hits +system.cpu7.l1c.overall_hits::total 9872 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36466 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36466 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60256 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60256 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60256 # number of overall misses +system.cpu7.l1c.overall_misses::total 60256 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1009807130 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1009807130 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 916976125 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 916976125 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1926783255 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1926783255 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1926783255 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1926783255 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24972 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24972 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70128 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70128 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70128 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70128 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807556 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807556 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.952667 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.952667 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859229 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859229 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859229 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859229 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27691.743816 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 27691.743816 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38544.603825 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 38544.603825 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 31976.620668 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 31976.620668 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 31976.620668 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 31976.620668 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1063264 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 59807 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61445 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 36.712392 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 17.304321 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9796 # number of writebacks -system.cpu7.l1c.writebacks::total 9796 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35973 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35973 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23939 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23939 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59912 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59912 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59912 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59912 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 2376889288 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 2376889288 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1839857154 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1839857154 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 4216746442 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 4216746442 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 4216746442 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 4216746442 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1084884512 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1084884512 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 4029557689 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 4029557689 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 5114442201 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 5114442201 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806986 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806986 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953897 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953897 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859903 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859903 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859903 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859903 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 66074.258138 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 66074.258138 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76856.057229 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76856.057229 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 70382.334791 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9819 # number of writebacks +system.cpu7.l1c.writebacks::total 9819 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36466 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36466 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60256 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60256 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60256 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60256 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 953998318 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 953998318 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 880753723 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 880753723 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1834752041 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1834752041 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1834752041 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1834752041 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 752742732 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 752742732 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1947143716 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1947143716 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2699886448 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2699886448 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807556 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807556 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952667 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952667 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859229 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859229 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859229 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859229 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26161.309658 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26161.309658 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 37022.014418 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37022.014418 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30449.283739 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency @@ -1037,566 +1037,565 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 12730 # number of replacements -system.l2c.tags.tagsinuse 780.951688 # Cycle average of tags in use -system.l2c.tags.total_refs 149721 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 13527 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.068308 # Average number of references to valid blocks. +system.l2c.tags.replacements 13121 # number of replacements +system.l2c.tags.tagsinuse 779.163229 # Cycle average of tags in use +system.l2c.tags.total_refs 150276 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 13897 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.813557 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 730.352338 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 5.728717 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.680211 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.211499 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 5.648633 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.142733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 5.860524 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.858945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.468088 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.713235 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.005594 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006524 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.005516 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.005999 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.005723 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006698 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.762648 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 424 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.778320 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1954074 # Number of tag accesses -system.l2c.tags.data_accesses 1954074 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10705 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10659 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10665 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10689 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10679 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10651 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10616 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85337 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 75478 # number of Writeback hits -system.l2c.Writeback_hits::total 75478 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 365 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 341 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 363 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 349 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 333 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 340 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 338 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2772 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1956 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1860 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1936 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1874 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1916 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1840 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1899 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1911 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15192 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12601 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12589 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12550 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12527 # number of demand (read+write) hits -system.l2c.demand_hits::total 100529 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12661 # number of overall hits -system.l2c.overall_hits::cpu1 12519 # number of overall hits -system.l2c.overall_hits::cpu2 12601 # number of overall hits -system.l2c.overall_hits::cpu3 12563 # number of overall hits -system.l2c.overall_hits::cpu4 12589 # number of overall hits -system.l2c.overall_hits::cpu5 12519 # number of overall hits -system.l2c.overall_hits::cpu6 12550 # number of overall hits -system.l2c.overall_hits::cpu7 12527 # number of overall hits -system.l2c.overall_hits::total 100529 # number of overall hits -system.l2c.ReadReq_misses::cpu0 637 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 698 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 718 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 649 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 657 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 655 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 700 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 686 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5400 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1869 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1879 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1945 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1927 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1931 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2008 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1996 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1999 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15554 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4360 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4327 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4376 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4482 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4415 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4364 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4427 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4401 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35152 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 4997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5025 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5094 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5131 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5072 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5019 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5127 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5087 # number of demand (read+write) misses -system.l2c.demand_misses::total 40552 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 4997 # number of overall misses -system.l2c.overall_misses::cpu1 5025 # number of overall misses -system.l2c.overall_misses::cpu2 5094 # number of overall misses -system.l2c.overall_misses::cpu3 5131 # number of overall misses -system.l2c.overall_misses::cpu4 5072 # number of overall misses -system.l2c.overall_misses::cpu5 5019 # number of overall misses -system.l2c.overall_misses::cpu6 5127 # number of overall misses -system.l2c.overall_misses::cpu7 5087 # number of overall misses -system.l2c.overall_misses::total 40552 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 37351962 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 41387952 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 42368449 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 38023954 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 38587461 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 38640955 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 40955466 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 40550959 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 317867158 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 53532000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 54034500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 55090000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 53743000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 53806000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 57327000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 56366500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 57375499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 441274499 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 232668482 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 231079974 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 233454479 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 239997471 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 235674978 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 232806977 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 236584974 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 235413970 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1877681305 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 270020444 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 272467926 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 275822928 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 278021425 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 274262439 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 271447932 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 277540440 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 275964929 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2195548463 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 270020444 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 272467926 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 275822928 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 278021425 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 274262439 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 271447932 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 277540440 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 275964929 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2195548463 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11357 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11383 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11338 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11330 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11334 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11351 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11302 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 90737 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 75478 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 75478 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2234 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2220 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2308 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2276 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2264 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2348 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2334 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2342 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18326 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6316 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6187 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6356 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6331 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6204 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6326 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50344 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17658 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17544 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17695 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17694 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17661 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17538 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17677 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17614 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 141081 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17658 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17544 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17695 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17694 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17661 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17538 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17677 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17614 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 141081 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.056163 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.061460 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.063077 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.057241 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.057988 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.057791 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.061669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.060697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.059513 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.836616 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.846396 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.842721 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.846661 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.852915 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.855196 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.855184 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.853544 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.848739 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.690310 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.699370 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.693283 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.705160 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.697362 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.703417 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.699810 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.697243 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.698236 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.282988 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.286423 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.287878 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.289985 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.287186 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.286179 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.290038 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.288804 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.287438 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.282988 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.286423 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.287878 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.289985 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.287186 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.286179 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.290038 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.288804 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.287438 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 58637.302983 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 59295.060172 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 59008.981894 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 58588.526965 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 58732.817352 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 58993.824427 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 58507.808571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 59112.185131 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 58864.288519 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28642.054575 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28757.051623 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28323.907455 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 27889.465490 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 27864.319006 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28549.302789 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28239.729459 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28702.100550 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28370.483413 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53364.330734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53404.200139 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53348.829753 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53546.959170 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53380.515968 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53347.153300 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53441.376553 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53491.017950 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53416.058972 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54036.510706 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54222.472836 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54146.628975 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54184.647242 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54073.824724 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54084.066946 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54133.107080 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54249.052290 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54141.558074 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54036.510706 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54222.472836 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54146.628975 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54184.647242 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54073.824724 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54084.066946 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54133.107080 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54249.052290 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54141.558074 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 6543 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 725.457797 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.718013 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.568954 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.219418 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.731947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.474998 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.998802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.991847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.001453 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.708455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006561 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006074 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006323 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006835 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006837 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.760902 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 566 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1961425 # Number of tag accesses +system.l2c.tags.data_accesses 1961425 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10794 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10766 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10683 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10671 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10889 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10673 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85829 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 75598 # number of Writeback hits +system.l2c.Writeback_hits::total 75598 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 323 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 342 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 334 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 356 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 330 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2745 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1821 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1892 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1893 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1922 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1886 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1863 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15171 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12615 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12658 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12630 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12554 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12639 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12593 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12775 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12536 # number of demand (read+write) hits +system.l2c.demand_hits::total 101000 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12615 # number of overall hits +system.l2c.overall_hits::cpu1 12658 # number of overall hits +system.l2c.overall_hits::cpu2 12630 # number of overall hits +system.l2c.overall_hits::cpu3 12554 # number of overall hits +system.l2c.overall_hits::cpu4 12639 # number of overall hits +system.l2c.overall_hits::cpu5 12593 # number of overall hits +system.l2c.overall_hits::cpu6 12775 # number of overall hits +system.l2c.overall_hits::cpu7 12536 # number of overall hits +system.l2c.overall_hits::total 101000 # number of overall hits +system.l2c.ReadReq_misses::cpu0 705 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 721 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 716 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 685 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 694 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 690 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 691 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 715 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5617 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1952 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1935 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1970 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1832 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1968 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1954 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1963 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1919 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15493 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4418 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4338 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4348 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4457 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4447 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4501 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4407 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 35289 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5059 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5064 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5142 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5141 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5191 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5098 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5088 # number of demand (read+write) misses +system.l2c.demand_misses::total 40906 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5123 # number of overall misses +system.l2c.overall_misses::cpu1 5059 # number of overall misses +system.l2c.overall_misses::cpu2 5064 # number of overall misses +system.l2c.overall_misses::cpu3 5142 # number of overall misses +system.l2c.overall_misses::cpu4 5141 # number of overall misses +system.l2c.overall_misses::cpu5 5191 # number of overall misses +system.l2c.overall_misses::cpu6 5098 # number of overall misses +system.l2c.overall_misses::cpu7 5088 # number of overall misses +system.l2c.overall_misses::total 40906 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 42571447 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 44584934 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 43709432 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 42098938 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 42802932 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 42467936 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 42434429 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 44394419 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 345064467 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 57799000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 58024000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 57179999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 53990500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 56201500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 57084499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 56659000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 56222499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 453160997 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 241579958 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 237098460 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 238347956 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 243950461 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 243322462 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 246152957 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 241076464 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 238492966 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1930021684 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 284151405 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 281683394 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 282057388 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 286049399 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 286125394 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 288620893 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 283510893 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 282887385 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2275086151 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 284151405 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 281683394 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 282057388 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 286049399 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 286125394 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 288620893 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 283510893 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 282887385 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2275086151 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11499 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11487 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11346 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11386 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11361 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11580 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11388 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91446 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 75598 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 75598 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2305 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2258 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2312 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2166 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2324 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2284 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2324 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2265 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18238 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6239 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6230 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6295 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6350 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6394 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6423 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6293 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6236 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50460 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17738 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17717 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17694 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17780 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17784 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17873 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17624 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 141906 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17738 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17717 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17694 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17780 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17784 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17873 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17624 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 141906 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.061310 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.062767 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.062813 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.060374 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.060952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.060734 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.059672 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.062785 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.061424 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.846855 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.856953 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.852076 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.845799 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.846816 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.855517 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.844664 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.847241 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.849490 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.708126 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.696308 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.690707 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.701890 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.695496 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.700763 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.700302 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.701251 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.699346 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.288815 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.285545 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.286199 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.290574 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.289145 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.291892 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.285235 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.288697 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.288261 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.288815 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.285545 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.286199 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.290574 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.289145 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.291892 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.285235 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.288697 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.288261 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 60385.031206 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61837.633842 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 61046.692737 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61458.303650 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61675.694524 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61547.733333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61410.172214 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 62090.096503 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61432.164323 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29610.143443 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29986.563307 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29025.380203 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29470.796943 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28557.672764 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29214.175537 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28863.474274 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29297.810839 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29249.402763 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 54680.841557 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 54656.168741 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54817.837167 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 54734.229527 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 54716.092197 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54688.504110 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54703.077831 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54537.609421 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54691.878036 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55465.821784 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55679.658826 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55698.536335 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55629.988137 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55655.591130 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55600.249085 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55612.179874 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55598.935731 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55617.419229 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55465.821784 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55679.658826 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55698.536335 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55629.988137 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55655.591130 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55600.249085 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55612.179874 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55598.935731 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55617.419229 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 10446 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 914 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1464 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.158643 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.135246 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6000 # number of writebacks -system.l2c.writebacks::total 6000 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 14 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 1 # number of demand (read+write) MSHR hits +system.l2c.writebacks::writebacks 6250 # number of writebacks +system.l2c.writebacks::total 6250 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 1 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 15 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 6 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu5 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 35 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 6 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu5 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 35 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 635 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 695 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 716 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 643 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 657 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 651 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 698 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 684 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5379 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1869 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1879 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1943 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1926 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1931 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2008 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1995 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1999 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15550 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4360 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4323 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4372 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4482 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4414 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4363 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4425 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4399 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 35138 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 4995 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5018 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5088 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5125 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5071 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5014 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5123 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5083 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40517 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 4995 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5018 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5088 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5125 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5071 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5014 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5123 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5083 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40517 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 29596962 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 32869452 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 33629449 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 29976455 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 30615961 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 30583955 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 32395466 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 32146959 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 251814659 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76123000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76358500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 79146000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 78403000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 78530000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81677500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 81182000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 81450499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 632870499 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 179654482 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 178405975 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 180144979 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 185516471 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 181991978 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 179667478 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 182702975 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 181859470 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1449943808 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 209251444 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 211275427 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 213774428 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 215492926 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 212607939 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 210251433 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 215098441 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 214006429 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1701758467 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 209251444 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 211275427 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 213774428 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 215492926 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 212607939 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 210251433 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 215098441 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 214006429 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1701758467 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 401930986 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 402911994 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 395709487 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 399023483 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 405620989 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 396449489 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 404605985 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 402179993 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3208432406 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 228006492 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 223295497 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 223196996 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 228513495 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 229209992 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 220676995 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 224532992 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 222245997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1799678456 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 629937478 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 626207491 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 618906483 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 627536978 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 634830981 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 617126484 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 629138977 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 624425990 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5008110862 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.055987 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.061196 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062901 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.056712 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.057988 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.057438 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.061492 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060520 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.059281 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.836616 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.846396 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.841854 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.846221 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.852915 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.855196 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.854756 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853544 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.848521 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690310 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.698723 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.692649 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.705160 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.697204 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.703256 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.699494 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696926 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.697958 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.282875 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.286024 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.287539 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.289646 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287130 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.285893 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.289812 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.288577 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.287190 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.282875 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.286024 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.287539 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.289646 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287130 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.285893 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.289812 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.288577 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.287190 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46609.388976 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 47294.175540 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46968.504190 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 46619.681182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46599.636225 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46979.961598 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46411.842407 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46998.478070 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46814.400260 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40729.266988 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40637.839276 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40733.916624 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40707.684320 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40668.047644 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40676.045817 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40692.731830 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40745.622311 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40699.067460 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41205.156422 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41269.020356 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41204.249543 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41391.448237 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41230.624830 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41179.802430 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41288.807910 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41341.093430 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41264.266834 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 41892.180981 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42103.512754 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42015.414308 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42047.400195 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 41926.235259 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 41932.874551 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 41986.812610 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42102.386189 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42001.097490 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 41892.180981 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42103.512754 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42015.414308 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42047.400195 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 41926.235259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 41932.874551 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 41986.812610 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42102.386189 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42001.097490 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 64 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 698 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 714 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 712 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 688 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 687 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 684 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 709 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5568 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1951 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1935 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1970 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1832 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1968 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1954 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1963 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1919 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15492 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4416 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4335 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4345 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4456 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4447 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4499 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4406 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4370 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 35274 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5114 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5049 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5057 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5132 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5135 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5186 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5090 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5079 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40842 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5114 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5049 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5057 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5132 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5135 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5186 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5090 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5079 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40842 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 33845945 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 35679430 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 34970423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 33623934 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 34265930 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 34048934 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 33977929 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 35572914 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 275985439 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81779494 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81207491 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 82576991 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 76840996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 82448987 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81922493 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82161995 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80384488 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 649322935 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 187970446 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 184467447 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 185588937 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189921941 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 189397436 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 191605943 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 187621956 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 185423942 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1501998048 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 221816391 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 220146877 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 220559360 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 223545875 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 223663366 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 225654877 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 221599885 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 220996856 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1777983487 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 221816391 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 220146877 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 220559360 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 223545875 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 223663366 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 225654877 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 221599885 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 220996856 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1777983487 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 420548415 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 410318426 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 408411942 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 419559934 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 403725937 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 410458428 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413026934 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 417703437 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3303753453 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 230815972 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 233216955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 233429960 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229986451 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230895448 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 235553969 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233378955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230983963 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1858261673 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 651364387 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 643535381 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 641841902 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 649546385 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 634621385 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 646012397 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 646405889 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 648687400 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5162015126 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.060701 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.062157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059580 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060425 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.060470 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059067 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.062259 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.060888 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.846421 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.856953 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.852076 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.845799 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.846816 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.855517 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.844664 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.847241 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.849435 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.707806 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.695827 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.690230 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.701732 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695496 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.700452 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.700143 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.700770 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.699049 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.288308 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.284981 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.285803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.290009 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.288808 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.291610 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.284787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.288187 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.287810 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.288308 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.284981 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.285803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.290009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.288808 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.291610 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.284787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.288187 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.287810 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48489.892550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49971.190476 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49115.762640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49739.547337 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49805.130814 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49561.767103 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49675.334795 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50173.362482 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49566.350395 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41916.706304 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41967.695607 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41917.254315 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.775109 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41894.810467 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41925.533777 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41855.320937 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41888.737884 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41913.434999 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42565.771286 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42553.044291 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42713.219102 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42621.620512 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42589.933888 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42588.562569 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42583.285520 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42431.108009 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42580.882463 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 43374.343176 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 43602.075064 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43614.664821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43559.211808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43556.643817 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43512.317200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 43536.323183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43511.883442 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43533.213040 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 43374.343176 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 43602.075064 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43614.664821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43559.211808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43556.643817 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43512.317200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 43536.323183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43511.883442 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43533.213040 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -1625,109 +1624,108 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 122833 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 120785 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 123722 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 121674 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 83923 # Transaction distribution -system.membus.trans_dist::ReadResp 83923 # Transaction distribution -system.membus.trans_dist::WriteReq 43483 # Transaction distribution -system.membus.trans_dist::WriteResp 43481 # Transaction distribution -system.membus.trans_dist::Writeback 6000 # Transaction distribution +system.membus.trans_dist::ReadReq 84424 # Transaction distribution +system.membus.trans_dist::ReadResp 84420 # Transaction distribution +system.membus.trans_dist::WriteReq 43379 # Transaction distribution +system.membus.trans_dist::WriteResp 43377 # Transaction distribution +system.membus.trans_dist::Writeback 6250 # Transaction distribution system.membus.trans_dist::UpgradeReq 58661 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47607 # Transaction distribution -system.membus.trans_dist::ReadExReq 50527 # Transaction distribution -system.membus.trans_dist::ReadExResp 3086 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 420691 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1047472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1047472 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 58495 # Total snoops (count) -system.membus.snoop_fanout::samples 122833 # Request fanout histogram +system.membus.trans_dist::UpgradeResp 47649 # Transaction distribution +system.membus.trans_dist::ReadExReq 50299 # Transaction distribution +system.membus.trans_dist::ReadExResp 3116 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421575 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 421575 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1077818 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1077818 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 58193 # Total snoops (count) +system.membus.snoop_fanout::samples 123722 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 122833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 123722 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 122833 # Request fanout histogram -system.membus.reqLayer0.occupancy 472878500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 31.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 318922500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 21.4 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 559080 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 259825 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 297207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 123722 # Request fanout histogram +system.membus.reqLayer0.occupancy 350831336 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 48.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 312389376 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 42.9 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 560254 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 259972 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 298234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 370692 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370683 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43483 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43481 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 75478 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29380 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29380 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161449 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161449 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120296 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120254 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120627 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119815 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119764 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 961915 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1743799 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1739946 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1755311 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1759542 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1748105 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1744654 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1747573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 13981678 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 323561 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 559080 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.688315 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.176863 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 371185 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371180 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43379 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43375 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 75598 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29248 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29247 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161278 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161272 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120544 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120292 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120322 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120320 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120179 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120443 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120589 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 963055 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1746802 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1746902 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1761658 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751012 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1764505 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756981 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1763838 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1750408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14042106 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 322707 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 560254 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.690126 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.177666 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 52722 9.43% 9.43% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 250233 44.76% 54.19% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141253 25.27% 79.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 69107 12.36% 91.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 29981 5.36% 97.18% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 11505 2.06% 99.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 3559 0.64% 99.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 720 0.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 52995 9.46% 9.46% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 250263 44.67% 54.13% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141259 25.21% 79.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 69446 12.40% 91.74% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 30460 5.44% 97.17% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 11695 2.09% 99.26% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 3486 0.62% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 650 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 559080 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1490758741 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 99.8 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 160617515 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 10.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 159518006 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 159700003 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 158882050 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 10.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 159826982 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 158824012 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 10.6 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 159298538 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 158114013 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 10.6 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 560254 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 719277462 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100586935 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100589620 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 100255865 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100593415 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100466351 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100465013 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 100397923 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100485866 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index f348549bd..b29e580fa 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,195 +1,195 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000667 # Number of seconds simulated -sim_ticks 667077000 # Number of ticks simulated -final_tick 667077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000476 # Number of seconds simulated +sim_ticks 475552000 # Number of ticks simulated +final_tick 475552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 152389795 # Simulator tick rate (ticks/s) -host_mem_usage 222064 # Number of bytes of host memory used -host_seconds 4.38 # Real time elapsed on the host +host_tick_rate 102852654 # Simulator tick rate (ticks/s) +host_mem_usage 276856 # Number of bytes of host memory used +host_seconds 4.62 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 82891 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 81142 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 81431 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 77551 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 82816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77581 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 78240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78400 # Number of bytes read from this memory -system.physmem.bytes_read::total 640052 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 398656 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5632 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5599 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5418 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5436 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5426 # Number of bytes written to this memory -system.physmem.bytes_written::total 442654 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11008 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10834 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10927 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87353 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6229 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5632 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5599 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5418 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5496 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5436 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5426 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 124260018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 121638132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 122071365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 116254945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 124147587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 116299917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 117287809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 117527662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 959487435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 597616167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 8184962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 8442803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 8393334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 8122001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 8238929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 8148984 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 8291397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 8133994 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 663572571 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 597616167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 132444980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 130080935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 130464699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 124376946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 132386516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 124448902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 125579206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 125661655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1623060007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 82626 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 79372 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 82635 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 78892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79911 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 82560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 82806 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 80499 # Number of bytes read from this memory +system.physmem.bytes_read::total 649301 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 411072 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5529 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5498 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5527 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5416 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5415 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5350 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5500 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5539 # Number of bytes written to this memory +system.physmem.bytes_written::total 454846 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10995 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11118 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10947 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88160 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6423 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5529 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5527 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5416 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5415 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5350 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5500 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5539 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50197 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 173747561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 166904986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 173766486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 165895633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 168038406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 173608775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 174126068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 169274864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1365362778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 864410201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 11626489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 11561301 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 11622283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 11388870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 11386767 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 11250084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 11565507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 11647517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 956459020 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 864410201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 185374050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 178466288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 185388769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 177284503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 179425173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 184858859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 185691575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 180922381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2321821799 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 55151 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22523 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.206747 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13668 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22921 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.596309 # Average number of references to valid blocks. +system.cpu0.num_writes 55373 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22370 # number of replacements +system.cpu0.l1c.tags.tagsinuse 390.859535 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13365 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.587292 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.206747 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.767982 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.767982 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338453 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338453 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8785 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8785 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1208 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1208 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9993 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9993 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9993 # number of overall hits -system.cpu0.l1c.overall_hits::total 9993 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36702 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36702 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23741 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23741 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60443 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60443 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60443 # number of overall misses -system.cpu0.l1c.overall_misses::total 60443 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 964033198 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 964033198 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 878854454 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 878854454 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1842887652 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1842887652 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1842887652 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1842887652 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45487 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45487 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24949 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24949 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70436 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70436 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70436 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70436 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806868 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.806868 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.951581 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.951581 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858127 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858127 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858127 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858127 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26266.503133 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 26266.503133 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37018.426098 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 37018.426098 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 30489.678739 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 30489.678739 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 30489.678739 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 30489.678739 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1018774 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 390.859535 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.763398 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.763398 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338979 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338979 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8642 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8642 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1137 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1137 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9779 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9779 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9779 # number of overall hits +system.cpu0.l1c.overall_hits::total 9779 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36791 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36791 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23910 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23910 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60701 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60701 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60701 # number of overall misses +system.cpu0.l1c.overall_misses::total 60701 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 598271123 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 598271123 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 653921249 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 653921249 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1252192372 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1252192372 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1252192372 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1252192372 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45433 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45433 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25047 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25047 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70480 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70480 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70480 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70480 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809786 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.809786 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954605 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954605 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861251 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861251 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861251 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861251 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16261.344432 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16261.344432 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27349.278503 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 27349.278503 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 20628.859030 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 20628.859030 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 20628.859030 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 20628.859030 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 775639 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 63007 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66482 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.169219 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.666902 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9806 # number of writebacks -system.cpu0.l1c.writebacks::total 9806 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36702 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36702 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23741 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23741 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60443 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60443 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60443 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60443 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 885636434 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 885636434 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 828679478 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 828679478 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1714315912 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1714315912 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1714315912 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1714315912 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 700887059 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 700887059 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1711925608 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1711925608 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2412812667 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2412812667 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806868 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806868 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.951581 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.951581 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858127 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858127 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24130.467931 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24130.467931 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34904.994651 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34904.994651 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28362.521913 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9788 # number of writebacks +system.cpu0.l1c.writebacks::total 9788 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36791 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36791 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23910 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23910 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60701 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60701 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60701 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60701 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 540766367 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 540766367 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 617095733 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 617095733 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1157862100 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1157862100 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1157862100 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1157862100 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 641214054 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 641214054 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 990476120 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 990476120 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1631690174 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1631690174 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809786 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809786 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954605 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954605 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861251 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861251 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14698.332935 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14698.332935 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25809.106357 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25809.106357 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99761 # number of read accesses completed -system.cpu1.num_writes 55328 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22642 # number of replacements -system.cpu1.l1c.tags.tagsinuse 394.589952 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13581 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 23033 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.589632 # Average number of references to valid blocks. +system.cpu1.num_reads 99552 # number of read accesses completed +system.cpu1.num_writes 55312 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22247 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.170580 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13534 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22643 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.597712 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 394.589952 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.770684 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.770684 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 339246 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 339246 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8788 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8788 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1121 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1121 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9909 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9909 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9909 # number of overall hits -system.cpu1.l1c.overall_hits::total 9909 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36866 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36866 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23806 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23806 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60672 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60672 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60672 # number of overall misses -system.cpu1.l1c.overall_misses::total 60672 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 969094954 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 969094954 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 879252966 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 879252966 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1848347920 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1848347920 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1848347920 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1848347920 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45654 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45654 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24927 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24927 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70581 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70581 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70581 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70581 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807509 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807509 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955029 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955029 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859608 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859608 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859608 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859608 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26286.956925 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 26286.956925 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 36934.090817 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 36934.090817 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 30464.595200 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 30464.595200 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 30464.595200 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 30464.595200 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1015089 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 391.170580 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.764005 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.764005 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338702 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338702 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8670 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8670 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1145 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1145 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9815 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9815 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9815 # number of overall hits +system.cpu1.l1c.overall_hits::total 9815 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36464 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36464 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 24184 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 24184 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60648 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60648 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60648 # number of overall misses +system.cpu1.l1c.overall_misses::total 60648 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 591998971 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 591998971 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 660686123 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 660686123 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1252685094 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1252685094 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1252685094 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1252685094 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45134 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45134 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25329 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25329 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70463 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70463 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70463 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70463 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807905 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.807905 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954795 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954795 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860707 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860707 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860707 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860707 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16235.162654 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16235.162654 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27319.141705 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 27319.141705 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 20655.010784 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 20655.010784 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 20655.010784 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 20655.010784 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 776857 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62996 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66458 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.113547 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.689443 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9956 # number of writebacks -system.cpu1.l1c.writebacks::total 9956 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36866 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36866 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23806 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23806 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60672 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60672 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60672 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60672 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 890415084 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 890415084 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 828850208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 828850208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1719265292 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1719265292 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1719265292 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1719265292 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 690509167 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 690509167 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1720529946 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1720529946 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2411039113 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2411039113 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807509 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807509 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955029 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955029 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859608 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859608 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24152.744643 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24152.744643 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34816.861632 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34816.861632 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9776 # number of writebacks +system.cpu1.l1c.writebacks::total 9776 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36464 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36464 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24184 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 24184 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60648 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60648 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 534984781 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 534984781 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 623377675 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 623377675 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1158362456 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1158362456 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1158362456 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1158362456 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 640712682 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 640712682 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 989782156 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 989782156 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1630494838 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1630494838 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807905 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807905 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954795 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954795 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860707 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860707 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14671.587895 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14671.587895 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25776.450339 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25776.450339 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99243 # number of read accesses completed -system.cpu2.num_writes 55132 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22573 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.676253 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13694 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22978 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.595961 # Average number of references to valid blocks. +system.cpu2.num_reads 99606 # number of read accesses completed +system.cpu2.num_writes 55482 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22450 # number of replacements +system.cpu2.l1c.tags.tagsinuse 391.646892 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13596 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22843 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.595193 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.676253 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.770852 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.770852 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338823 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338823 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8940 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8940 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1180 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1180 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 10120 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 10120 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 10120 # number of overall hits -system.cpu2.l1c.overall_hits::total 10120 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36529 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36529 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23864 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23864 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60393 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60393 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60393 # number of overall misses -system.cpu2.l1c.overall_misses::total 60393 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 963156898 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 963156898 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 890183991 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 890183991 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1853340889 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1853340889 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1853340889 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1853340889 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45469 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45469 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25044 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25044 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70513 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70513 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70513 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70513 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.803383 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.803383 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952883 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.952883 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.856480 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.856480 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.856480 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.856480 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26366.911166 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 26366.911166 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37302.379777 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 37302.379777 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 30688.008362 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 30688.008362 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 30688.008362 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 30688.008362 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1016015 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 391.646892 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.764935 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.764935 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338700 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338700 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8761 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8761 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1179 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1179 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9940 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9940 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9940 # number of overall hits +system.cpu2.l1c.overall_hits::total 9940 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36421 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36421 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24109 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24109 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60530 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60530 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60530 # number of overall misses +system.cpu2.l1c.overall_misses::total 60530 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 592390101 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 592390101 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 664239589 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 664239589 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1256629690 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1256629690 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1256629690 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1256629690 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45182 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45182 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25288 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25288 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70470 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70470 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70470 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70470 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806095 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.806095 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953377 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953377 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858947 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858947 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858947 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858947 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16265.069630 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16265.069630 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27551.519723 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 27551.519723 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 20760.444243 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 20760.444243 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 20760.444243 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 20760.444243 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 773028 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 62631 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66120 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.222238 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.691289 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9915 # number of writebacks -system.cpu2.l1c.writebacks::total 9915 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36529 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36529 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23864 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23864 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60393 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60393 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60393 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60393 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 885079158 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 885079158 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 839760037 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 839760037 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1724839195 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1724839195 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1724839195 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1724839195 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 685753748 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 685753748 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1712116464 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1712116464 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2397870212 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2397870212 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803383 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803383 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952883 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952883 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.856480 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.856480 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24229.493225 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24229.493225 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35189.408188 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35189.408188 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9975 # number of writebacks +system.cpu2.l1c.writebacks::total 9975 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36421 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36421 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24109 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24109 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60530 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60530 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60530 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60530 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 535479769 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 535479769 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 627082203 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 627082203 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1162561972 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1162561972 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1162561972 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1162561972 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 634925616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 634925616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 991782664 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 991782664 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1626708280 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1626708280 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806095 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806095 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953377 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953377 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858947 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858947 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14702.500453 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14702.500453 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26010.295035 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26010.295035 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99256 # number of read accesses completed -system.cpu3.num_writes 54955 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22662 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.489449 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13390 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 23054 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.580810 # Average number of references to valid blocks. +system.cpu3.num_reads 99549 # number of read accesses completed +system.cpu3.num_writes 55104 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22310 # number of replacements +system.cpu3.l1c.tags.tagsinuse 391.032656 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13513 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22709 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.595050 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.489449 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770487 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770487 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337690 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337690 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8629 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8629 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1137 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1137 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9766 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9766 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9766 # number of overall hits -system.cpu3.l1c.overall_hits::total 9766 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36563 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36563 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23903 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23903 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60466 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60466 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60466 # number of overall misses -system.cpu3.l1c.overall_misses::total 60466 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 960736157 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 960736157 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 887839747 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 887839747 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1848575904 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1848575904 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1848575904 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1848575904 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45192 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45192 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25040 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25040 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70232 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70232 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70232 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70232 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809059 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.809059 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954593 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954593 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860947 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860947 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860947 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860947 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26276.185133 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 26276.185133 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 37143.444212 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 37143.444212 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 30572.154665 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 30572.154665 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 30572.154665 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 30572.154665 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1022448 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 391.032656 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.763736 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.763736 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 338332 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 338332 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8654 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8654 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1182 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1182 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9836 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9836 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9836 # number of overall hits +system.cpu3.l1c.overall_hits::total 9836 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36530 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36530 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 24013 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 24013 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60543 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60543 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60543 # number of overall misses +system.cpu3.l1c.overall_misses::total 60543 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 590001438 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 590001438 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 660132360 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 660132360 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1250133798 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1250133798 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1250133798 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1250133798 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45184 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45184 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25195 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25195 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70379 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70379 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70379 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70379 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808472 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808472 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953086 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953086 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860242 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860242 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860242 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860242 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16151.148043 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16151.148043 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27490.624245 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 27490.624245 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 20648.692632 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 20648.692632 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 20648.692632 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 20648.692632 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 774871 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 63227 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66332 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.171066 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.681707 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9928 # number of writebacks -system.cpu3.l1c.writebacks::total 9928 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36563 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36563 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23903 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23903 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60466 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60466 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60466 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60466 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 882571457 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 882571457 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 837312821 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 837312821 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1719884278 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1719884278 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1719884278 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1719884278 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 700068981 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 700068981 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1667398980 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1667398980 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2367467961 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2367467961 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809059 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809059 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954593 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954593 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860947 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860947 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860947 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860947 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24138.376419 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24138.376419 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 35029.612224 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 35029.612224 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9907 # number of writebacks +system.cpu3.l1c.writebacks::total 9907 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36530 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36530 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24013 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 24013 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60543 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60543 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60543 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60543 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 532881722 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 532881722 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 623079094 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 623079094 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1155960816 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1155960816 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1155960816 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1155960816 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 642783574 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 642783574 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 972713175 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 972713175 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1615496749 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1615496749 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808472 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808472 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953086 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953086 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860242 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860242 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14587.509499 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14587.509499 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25947.573981 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25947.573981 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99292 # number of read accesses completed -system.cpu4.num_writes 54781 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22192 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.392100 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13471 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22589 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.596352 # Average number of references to valid blocks. +system.cpu4.num_reads 99755 # number of read accesses completed +system.cpu4.num_writes 55257 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22302 # number of replacements +system.cpu4.l1c.tags.tagsinuse 391.084224 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13540 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.596660 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.392100 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.768344 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.768344 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 369 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 336466 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 336466 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8698 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8698 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1159 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1159 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9857 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9857 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9857 # number of overall hits -system.cpu4.l1c.overall_hits::total 9857 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36438 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36438 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23701 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23701 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60139 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60139 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60139 # number of overall misses -system.cpu4.l1c.overall_misses::total 60139 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 959750489 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 959750489 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 883613878 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 883613878 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1843364367 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1843364367 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1843364367 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1843364367 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45136 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45136 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24860 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24860 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69996 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69996 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69996 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69996 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807294 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807294 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953379 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953379 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859178 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859178 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859178 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859178 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26339.274631 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 26339.274631 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37281.712924 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 37281.712924 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 30651.729610 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 30651.729610 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 30651.729610 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 30651.729610 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1023771 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 391.084224 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.763836 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.763836 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338305 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338305 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8852 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8852 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1084 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1084 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9936 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9936 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9936 # number of overall hits +system.cpu4.l1c.overall_hits::total 9936 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36600 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36600 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23847 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23847 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60447 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60447 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60447 # number of overall misses +system.cpu4.l1c.overall_misses::total 60447 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 590829220 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 590829220 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 656323200 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 656323200 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1247152420 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1247152420 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1247152420 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1247152420 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45452 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45452 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24931 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24931 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70383 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70383 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70383 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70383 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805245 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805245 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956520 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.956520 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858830 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858830 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858830 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858830 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16142.874863 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16142.874863 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27522.254372 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 27522.254372 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 20632.164045 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 20632.164045 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 20632.164045 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 20632.164045 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 780817 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 62867 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66569 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.284712 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.729439 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9698 # number of writebacks -system.cpu4.l1c.writebacks::total 9698 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36438 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36438 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23701 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23701 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60139 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60139 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60139 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60139 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 881959493 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 881959493 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 833428166 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 833428166 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1715387659 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1715387659 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1715387659 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1715387659 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 703007482 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 703007482 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1705988496 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1705988496 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2408995978 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2408995978 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807294 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807294 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953379 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953379 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859178 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859178 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859178 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859178 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24204.388084 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24204.388084 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35164.261677 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35164.261677 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28523.714378 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9856 # number of writebacks +system.cpu4.l1c.writebacks::total 9856 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36600 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36600 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23847 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23847 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60447 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60447 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 533635904 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 533635904 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 619552810 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 619552810 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1153188714 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1153188714 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1153188714 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1153188714 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 651255905 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 651255905 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 973411350 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 973411350 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1624667255 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1624667255 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805245 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805245 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956520 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956520 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858830 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858830 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858830 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858830 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14580.215956 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14580.215956 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25980.324988 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25980.324988 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99672 # number of read accesses completed -system.cpu5.num_writes 54824 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22459 # number of replacements -system.cpu5.l1c.tags.tagsinuse 393.671106 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13533 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22853 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.592176 # Average number of references to valid blocks. +system.cpu5.num_reads 99495 # number of read accesses completed +system.cpu5.num_writes 54912 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22132 # number of replacements +system.cpu5.l1c.tags.tagsinuse 389.508075 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13369 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22545 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.592992 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 393.671106 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.768889 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.768889 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337969 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337969 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8696 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8696 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1170 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9866 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9866 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9866 # number of overall hits -system.cpu5.l1c.overall_hits::total 9866 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36658 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36658 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23786 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23786 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60444 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60444 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60444 # number of overall misses -system.cpu5.l1c.overall_misses::total 60444 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 958216057 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 958216057 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 885896912 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 885896912 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1844112969 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1844112969 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1844112969 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1844112969 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45354 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45354 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24956 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24956 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70310 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70310 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808264 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808264 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953117 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.953117 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859679 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859679 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859679 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859679 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26139.343581 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 26139.343581 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37244.467838 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 37244.467838 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 30509.446248 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 30509.446248 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 30509.446248 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 30509.446248 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1026604 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 389.508075 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.760758 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.760758 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 409 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.806641 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337023 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337023 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8615 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8615 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1193 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1193 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9808 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9808 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9808 # number of overall hits +system.cpu5.l1c.overall_hits::total 9808 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36426 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36426 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23853 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23853 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60279 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60279 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60279 # number of overall misses +system.cpu5.l1c.overall_misses::total 60279 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 593740716 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 593740716 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 656837719 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 656837719 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1250578435 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1250578435 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1250578435 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1250578435 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45041 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45041 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25046 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25046 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70087 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70087 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70087 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70087 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808730 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808730 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952368 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952368 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860060 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860060 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860060 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860060 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16299.915335 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16299.915335 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27536.901815 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 27536.901815 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 20746.502679 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 20746.502679 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 20746.502679 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 20746.502679 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 781949 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 63359 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66475 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.202970 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.763054 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9812 # number of writebacks -system.cpu5.l1c.writebacks::total 9812 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36658 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36658 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23786 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23786 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60444 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60444 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60444 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60444 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 879872261 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 879872261 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 835586106 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 835586106 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1715458367 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1715458367 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1715458367 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1715458367 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 707107291 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 707107291 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1680181552 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1680181552 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2387288843 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2387288843 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808264 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808264 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953117 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953117 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859679 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859679 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24002.189454 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24002.189454 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35129.324224 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35129.324224 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9742 # number of writebacks +system.cpu5.l1c.writebacks::total 9742 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36426 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36426 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23853 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23853 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60279 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60279 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60279 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60279 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 536794980 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 536794980 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 620108209 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 620108209 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1156903189 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1156903189 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1156903189 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1156903189 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648821919 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648821919 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 955346733 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 955346733 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1604168652 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1604168652 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808730 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808730 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952368 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952368 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860060 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860060 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860060 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860060 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14736.588700 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14736.588700 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 25997.074121 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 25997.074121 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19192.474809 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99511 # number of read accesses completed -system.cpu6.num_writes 54977 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22541 # number of replacements -system.cpu6.l1c.tags.tagsinuse 393.448229 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13464 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.586948 # Average number of references to valid blocks. +system.cpu6.num_reads 99492 # number of read accesses completed +system.cpu6.num_writes 55188 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22041 # number of replacements +system.cpu6.l1c.tags.tagsinuse 390.749630 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13460 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22445 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.599688 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 393.448229 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.768454 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.768454 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337704 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337704 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8641 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8641 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1220 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1220 # number of WriteReq hits +system.cpu6.l1c.tags.occ_blocks::cpu6 390.749630 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.763183 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.763183 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337459 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337459 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8703 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8703 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1158 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1158 # number of WriteReq hits system.cpu6.l1c.demand_hits::cpu6 9861 # number of demand (read+write) hits system.cpu6.l1c.demand_hits::total 9861 # number of demand (read+write) hits system.cpu6.l1c.overall_hits::cpu6 9861 # number of overall hits system.cpu6.l1c.overall_hits::total 9861 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36671 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36671 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23713 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23713 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60384 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60384 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60384 # number of overall misses -system.cpu6.l1c.overall_misses::total 60384 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 960694665 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 960694665 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 879536054 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 879536054 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1840230719 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1840230719 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1840230719 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1840230719 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45312 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45312 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24933 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24933 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70245 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70245 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70245 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70245 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.809300 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.809300 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951069 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.951069 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859620 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859620 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26197.667503 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 26197.667503 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 37090.880698 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 37090.880698 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 30475.468982 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 30475.468982 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 30475.468982 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 30475.468982 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1019991 # number of cycles access was blocked +system.cpu6.l1c.ReadReq_misses::cpu6 36430 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36430 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23907 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23907 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60337 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60337 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60337 # number of overall misses +system.cpu6.l1c.overall_misses::total 60337 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 592106528 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 592106528 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 650271582 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 650271582 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1242378110 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1242378110 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1242378110 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1242378110 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45133 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45133 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25065 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25065 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70198 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70198 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70198 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70198 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807170 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807170 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953800 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953800 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859526 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859526 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859526 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859526 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16253.267307 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16253.267307 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27200.049442 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 27200.049442 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 20590.651010 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 20590.651010 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 20590.651010 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 20590.651010 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 773385 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62969 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66167 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.198304 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.688379 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9771 # number of writebacks -system.cpu6.l1c.writebacks::total 9771 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36671 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36671 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23713 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23713 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60384 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60384 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60384 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60384 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 882425777 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 882425777 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 829351266 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 829351266 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1711777043 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1711777043 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1711777043 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1711777043 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702299487 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702299487 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1717296024 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1717296024 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2419595511 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2419595511 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.809300 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.809300 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951069 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951069 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859620 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859620 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859620 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24063.313708 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24063.313708 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34974.539957 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34974.539957 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9775 # number of writebacks +system.cpu6.l1c.writebacks::total 9775 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36430 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36430 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23907 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23907 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60337 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60337 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60337 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60337 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 535158836 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 535158836 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 613445646 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 613445646 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1148604482 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1148604482 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1148604482 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1148604482 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 648116847 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 648116847 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 997038722 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 997038722 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1645155569 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1645155569 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807170 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807170 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953800 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953800 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859526 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859526 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859526 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859526 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14690.058633 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14690.058633 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25659.666458 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25659.666458 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19036.486435 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98836 # number of read accesses completed -system.cpu7.num_writes 54806 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22352 # number of replacements -system.cpu7.l1c.tags.tagsinuse 393.572142 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13400 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22745 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.589140 # Average number of references to valid blocks. +system.cpu7.num_reads 99953 # number of read accesses completed +system.cpu7.num_writes 55743 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22636 # number of replacements +system.cpu7.l1c.tags.tagsinuse 393.668569 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13591 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 23039 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.589913 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 393.572142 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.768696 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.768696 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 363 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 336509 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 336509 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8699 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8699 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1106 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1106 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9805 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9805 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9805 # number of overall hits -system.cpu7.l1c.overall_hits::total 9805 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36228 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36228 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23958 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23958 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60186 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60186 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60186 # number of overall misses -system.cpu7.l1c.overall_misses::total 60186 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 952764751 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 952764751 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 890612165 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 890612165 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1843376916 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1843376916 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1843376916 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1843376916 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44927 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44927 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25064 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25064 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69991 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69991 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69991 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69991 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806375 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806375 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955873 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955873 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859911 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859911 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859911 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859911 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26299.126394 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 26299.126394 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37173.894524 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 37173.894524 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 30628.001794 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 30628.001794 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 30628.001794 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 30628.001794 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1021665 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 393.668569 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.768884 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.768884 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 340053 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 340053 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8802 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8802 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1188 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1188 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9990 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9990 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9990 # number of overall hits +system.cpu7.l1c.overall_hits::total 9990 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36601 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36601 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24152 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24152 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60753 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60753 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60753 # number of overall misses +system.cpu7.l1c.overall_misses::total 60753 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 595212008 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 595212008 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 656742976 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 656742976 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1251954984 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1251954984 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1251954984 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1251954984 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45403 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45403 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25340 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25340 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70743 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70743 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70743 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70743 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806136 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.806136 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953118 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953118 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858785 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858785 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858785 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858785 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16262.178848 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16262.178848 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27192.074197 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 27192.074197 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 20607.294850 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 20607.294850 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 20607.294850 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 20607.294850 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 772653 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 62785 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66243 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.272438 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.663919 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9931 # number of writebacks -system.cpu7.l1c.writebacks::total 9931 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36228 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36228 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23958 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23958 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60186 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60186 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60186 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60186 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 875407713 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 875407713 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 839967251 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 839967251 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1715374964 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1715374964 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1715374964 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1715374964 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 702238586 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 702238586 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1694350083 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1694350083 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2396588669 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2396588669 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806375 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806375 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955873 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955873 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859911 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859911 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859911 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859911 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24163.843243 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24163.843243 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35059.990442 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35059.990442 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28501.228924 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9979 # number of writebacks +system.cpu7.l1c.writebacks::total 9979 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36601 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36601 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24152 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24152 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60753 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60753 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60753 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60753 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 538040158 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 538040158 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 619565494 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 619565494 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1157605652 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1157605652 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1157605652 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1157605652 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 639132078 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639132078 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 986824111 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 986824111 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1625956189 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1625956189 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806136 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806136 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953118 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953118 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858785 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858785 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858785 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858785 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14700.149122 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14700.149122 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25652.761428 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25652.761428 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency @@ -1037,567 +1037,566 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13277 # number of replacements -system.l2c.tags.tagsinuse 783.059977 # Cycle average of tags in use -system.l2c.tags.total_refs 151520 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14056 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.779738 # Average number of references to valid blocks. +system.l2c.tags.replacements 13510 # number of replacements +system.l2c.tags.tagsinuse 783.849989 # Cycle average of tags in use +system.l2c.tags.total_refs 151949 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14294 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.630264 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 729.095705 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.040995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.066153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.783419 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.143521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.879919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.083313 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.867349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.099602 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.712008 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006901 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006624 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006976 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006719 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.005941 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006706 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.005957 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.764707 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 779 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 598 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.760742 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1976800 # Number of tag accesses -system.l2c.tags.data_accesses 1976800 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10861 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10871 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10670 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10859 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10920 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10735 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86470 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76237 # number of Writeback hits -system.l2c.Writeback_hits::total 76237 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 344 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 346 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 369 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 358 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 342 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 326 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 336 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 356 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2777 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1915 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1982 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1977 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1958 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1937 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1931 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15500 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12853 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12710 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12857 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12666 # number of demand (read+write) hits -system.l2c.demand_hits::total 101970 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12644 # number of overall hits -system.l2c.overall_hits::cpu1 12776 # number of overall hits -system.l2c.overall_hits::cpu2 12853 # number of overall hits -system.l2c.overall_hits::cpu3 12647 # number of overall hits -system.l2c.overall_hits::cpu4 12710 # number of overall hits -system.l2c.overall_hits::cpu5 12817 # number of overall hits -system.l2c.overall_hits::cpu6 12857 # number of overall hits -system.l2c.overall_hits::cpu7 12666 # number of overall hits -system.l2c.overall_hits::total 101970 # number of overall hits -system.l2c.ReadReq_misses::cpu0 765 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 729 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 729 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 708 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 735 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 684 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 695 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 674 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5719 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1992 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1980 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1951 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2012 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1975 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1990 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2015 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1970 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15885 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4350 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4268 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4371 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4368 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4431 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4387 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4359 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4476 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35010 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5115 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 4997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5100 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5076 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5166 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5071 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5054 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5150 # number of demand (read+write) misses -system.l2c.demand_misses::total 40729 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5115 # number of overall misses -system.l2c.overall_misses::cpu1 4997 # number of overall misses -system.l2c.overall_misses::cpu2 5100 # number of overall misses -system.l2c.overall_misses::cpu3 5076 # number of overall misses -system.l2c.overall_misses::cpu4 5166 # number of overall misses -system.l2c.overall_misses::cpu5 5071 # number of overall misses -system.l2c.overall_misses::cpu6 5054 # number of overall misses -system.l2c.overall_misses::cpu7 5150 # number of overall misses -system.l2c.overall_misses::total 40729 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 46620930 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 44960918 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 44432427 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 43382432 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 44487433 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 41294425 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 42419930 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 41189936 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 348788431 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 57711996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 58106496 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 57659498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 57666495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 55433497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 57841495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 59041000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 57235498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 460695975 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 234061451 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 229252453 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 235963436 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 234901447 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 238651447 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 236178452 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 234894949 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 241135947 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1885039582 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 280682381 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 274213371 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 280395863 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 278283879 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 283138880 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 277472877 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 277314879 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 282325883 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2233828013 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 280682381 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 274213371 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 280395863 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 278283879 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 283138880 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 277472877 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 277314879 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 282325883 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2233828013 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11509 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11590 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11600 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11378 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11545 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11543 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11615 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11409 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 92189 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 76237 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 76237 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2336 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2326 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2320 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2370 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2326 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18662 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6250 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6183 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6353 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6345 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6331 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6345 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6407 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50510 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17773 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17953 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17723 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17876 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17888 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17911 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17816 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 142699 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17953 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17723 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17876 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17888 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17911 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17816 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 142699 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.066470 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.062899 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.062845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.062225 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.063664 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.059257 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.059836 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.059076 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.062036 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.852740 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.851247 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.840948 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.848945 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.852395 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.859240 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.857082 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.846948 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.851195 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.696000 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.690280 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.688021 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.688416 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.699889 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.691411 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.692344 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.698611 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.693130 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.288023 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.281157 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.284075 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.286407 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.288991 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.283486 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.282173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.289066 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.285419 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.288023 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.281157 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.284075 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.286407 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.288991 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.283486 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.282173 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.289066 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.285419 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 60942.392157 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61674.784636 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 60949.831276 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61274.621469 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 60527.119728 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 60371.966374 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61035.870504 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 61112.664688 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 60987.660605 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28971.885542 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 29346.715152 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29553.817529 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 28661.279821 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28067.593418 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29066.077889 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29300.744417 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29053.552284 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29001.949953 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53807.230115 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53714.257966 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53983.856326 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53777.803800 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53859.500564 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53835.981764 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53887.347786 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53873.089142 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53842.890089 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54874.365787 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54875.599560 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54979.580980 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54823.459220 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54808.145567 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54717.585683 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54870.375742 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54820.559806 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54846.129613 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54874.365787 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54875.599560 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54979.580980 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54823.459220 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54808.145567 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54717.585683 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54870.375742 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54820.559806 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54846.129613 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 11130 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 725.717756 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.606207 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.042760 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.314362 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.280142 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.903512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.337678 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.211948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.435623 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.708709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007428 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006878 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007143 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006742 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007261 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765479 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 680 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1986932 # Number of tag accesses +system.l2c.tags.data_accesses 1986932 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10772 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10720 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10796 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10828 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10876 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10784 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10741 # number of ReadReq hits +system.l2c.ReadReq_hits::total 86242 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 77037 # number of Writeback hits +system.l2c.Writeback_hits::total 77037 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 331 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 373 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 321 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 366 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2816 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 2031 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1999 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1974 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2000 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1993 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1980 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1967 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1970 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15914 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12803 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12770 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12828 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12869 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12764 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12711 # 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number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 722 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 727 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5742 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1949 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2075 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2001 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2024 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1976 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1982 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1991 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1901 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15899 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4324 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4508 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4412 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4451 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4429 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4229 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4405 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 35131 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5104 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 4998 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5254 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5106 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5153 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5175 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 4951 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5132 # 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number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 45919927 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 44260438 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 44979437 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 354430430 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 56379995 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 59258495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 58685995 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 56511495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 59771492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 56753497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 61514994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 54850495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 463726458 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 240858936 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 238452262 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 247966448 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 242840437 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 244973443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 243557270 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 233129438 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 242077945 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1933856179 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 285954862 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 280001684 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 294416377 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 285763365 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 288225866 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 289477197 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 277389876 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 287057382 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2288286609 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 285954862 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 280001684 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 294416377 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 285763365 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 288225866 # 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number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77037 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77037 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2280 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2448 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2364 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2377 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2297 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2345 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2337 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2267 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18715 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6404 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6323 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6482 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6444 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6409 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6196 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6375 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51045 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17907 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17717 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18024 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17934 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17939 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17643 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17843 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143029 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17907 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17717 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18024 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17934 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17939 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17643 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17843 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143029 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.063549 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.059154 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.064634 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.060233 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.060632 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.064701 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.063073 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.063394 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.062424 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.854825 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.847631 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.846447 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.851493 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.860253 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.845203 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.851947 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.838553 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.849532 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.682854 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.683853 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.695464 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.688085 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.690720 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.691059 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.682537 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.690980 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.688236 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.285028 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.282102 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.291500 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.284711 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.285928 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.288478 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.280621 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.287620 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.285767 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.285028 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.282102 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.291500 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.284711 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.285928 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.288478 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.280621 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.287620 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.285767 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 61690.733242 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61646.026706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 62265.320375 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61848.599424 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61613.138177 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61554.861930 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61302.545706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 61869.927098 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61725.954371 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28927.652642 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28558.310843 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29328.333333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27920.699111 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 30248.730769 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28634.458628 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 30896.531391 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 28853.495529 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29167.020442 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55078.649897 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55146.221554 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55005.866903 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55040.896872 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55037.843855 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54991.481147 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 55126.374557 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54955.265607 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55047.000626 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56025.639107 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56022.745898 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56036.615341 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55966.189777 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55933.604890 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55937.622609 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56027.040194 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55934.797740 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55985.286350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56025.639107 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56022.745898 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56036.615341 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55966.189777 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55933.604890 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55937.622609 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56027.040194 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55934.797740 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55985.286350 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 17581 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1567 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3250 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.102744 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.409538 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6229 # number of writebacks -system.l2c.writebacks::total 6229 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 11 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6423 # number of writebacks +system.l2c.writebacks::total 6423 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 21 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 39 # number of ReadExReq MSHR hits system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 758 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 722 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 718 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 704 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 730 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 673 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 692 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 669 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5666 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1992 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1980 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1951 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2012 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1974 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1990 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2015 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1969 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15883 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4346 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4265 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4369 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4364 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4430 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4383 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4358 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4474 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34989 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5104 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 4987 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5087 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5068 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5160 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5056 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5050 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5143 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40655 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5104 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 4987 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5087 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5068 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5160 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5056 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5050 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5143 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40655 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 37179930 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 35966920 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 35314428 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 34763932 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 35492434 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 32731425 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 33928930 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 32969437 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 278347436 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81798995 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81126494 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80135996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 82599489 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 81068996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81609993 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82618495 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80871496 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 651829954 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 181281952 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 177509453 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 183001436 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 181913947 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 184978447 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 182997452 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 182077949 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 186899447 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1460660083 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 218461882 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 213476373 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 218315864 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 216677879 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 220470881 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 215728877 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 216006879 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 219868884 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1739007519 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 218461882 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 213476373 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 218315864 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 216677879 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 220470881 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 215728877 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 216006879 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 219868884 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1739007519 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 407707447 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 401123946 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 397019445 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 405812955 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407128948 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 410535950 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 408564954 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406637950 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3244531595 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 230392811 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 237768794 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 237208468 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229246463 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 232269476 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230268468 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 234242974 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 227836970 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1859234424 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 638100258 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 638892740 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 634227913 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 635059418 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 639398424 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 640804418 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 642807928 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 634474920 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5103766019 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.065861 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.062295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.061897 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061874 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063231 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058304 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059578 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.058638 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.061461 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852740 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.851247 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.840948 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.848945 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.851964 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.859240 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.857082 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.846518 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.851088 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.695360 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689795 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.687707 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687786 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.699731 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690780 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.692186 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.698299 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.692714 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.287404 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.280594 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.283351 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.285956 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.288655 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.282648 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.281950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.288673 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284900 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.287404 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.280594 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.283351 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.285956 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.288655 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.282648 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.281950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.288673 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284900 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49050.039578 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49815.678670 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49184.440111 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49380.585227 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48619.772603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48635.104012 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49030.245665 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49281.669656 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49125.915284 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41063.752510 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40972.976768 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41074.318811 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41053.423956 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41068.387031 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41010.046734 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41001.734491 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41072.369731 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41039.473273 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41712.368155 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41620.035873 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41886.343786 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41685.139093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41755.857111 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41751.643167 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41780.162689 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41774.574654 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41746.265483 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42802.092868 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42806.571686 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42916.426971 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42754.119771 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42726.914922 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42667.894976 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42773.639406 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42751.095470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42774.751420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42802.092868 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42806.571686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42916.426971 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42754.119771 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42726.914922 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42667.894976 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42773.639406 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42751.095470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42774.751420 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 100 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 725 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 661 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 738 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 690 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 692 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 741 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 711 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 723 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5681 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1949 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2074 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2001 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2023 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1976 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1982 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1991 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1901 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15897 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4368 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4317 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4505 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4406 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4442 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4423 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4229 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4402 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 35092 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5093 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 4978 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5243 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5096 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5134 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5164 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 4940 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5125 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40773 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5093 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 4978 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5243 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5096 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5134 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5164 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 4940 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5125 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40773 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 36140918 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 33131910 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 37333917 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 34463914 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 34507911 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 36862423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 35293427 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 36098935 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 283833355 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 82188451 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 87682473 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 84603955 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 85652462 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 83560954 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83969963 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 84367474 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80329284 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 672355016 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 188025870 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 186115345 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 193429372 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189404867 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 191140359 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 189945201 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 182082372 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 188836863 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1508980249 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 224166788 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 219247255 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 230763289 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 223868781 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 225648270 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 226807624 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 217375799 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 224935798 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1792813604 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 224166788 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 219247255 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 230763289 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 223868781 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 225648270 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 226807624 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 217375799 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 224935798 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1792813604 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 419997297 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 420394389 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 416554764 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 421667758 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 426680271 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 424776767 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 425015068 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 419160275 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3374246589 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 245735705 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 245037892 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 243130891 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 240328902 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 241689545 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 236933897 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 244635896 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 245230718 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1942723446 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 665733002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 665432281 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 659685655 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 661996660 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 668369816 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 661710664 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 669650964 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 664390993 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5316970035 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.063027 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.058013 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.063940 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059885 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.059769 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.064267 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.062112 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063045 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.061761 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.854825 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.847222 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.846447 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851073 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.860253 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.845203 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.851947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.838553 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.849426 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.682074 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682746 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.695002 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687149 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.689323 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690123 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.682537 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.690510 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.687472 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285068 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285068 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49849.542069 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50123.918306 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50587.963415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49947.701449 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49866.923410 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49746.859649 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49639.137834 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49929.370678 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49961.864989 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42169.548999 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42276.987946 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42280.837081 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42339.328720 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42287.932186 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42366.278002 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42374.421899 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42256.330352 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42294.459080 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43046.215659 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43112.194811 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42936.597558 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42987.940763 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43030.247411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42944.879267 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43055.656656 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42897.969786 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43000.691012 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -1626,64 +1625,64 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 84242 # Transaction distribution -system.membus.trans_dist::ReadResp 84239 # Transaction distribution -system.membus.trans_dist::WriteReq 43998 # Transaction distribution -system.membus.trans_dist::WriteResp 43998 # Transaction distribution -system.membus.trans_dist::Writeback 6229 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58563 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47765 # Transaction distribution -system.membus.trans_dist::ReadExReq 50044 # Transaction distribution -system.membus.trans_dist::ReadExResp 3111 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 422189 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 422189 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1082703 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1082703 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57731 # Total snoops (count) -system.membus.snoop_fanout::samples 123701 # Request fanout histogram +system.membus.trans_dist::ReadReq 84922 # Transaction distribution +system.membus.trans_dist::ReadResp 84916 # Transaction distribution +system.membus.trans_dist::WriteReq 43774 # Transaction distribution +system.membus.trans_dist::WriteResp 43771 # Transaction distribution +system.membus.trans_dist::Writeback 6423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58524 # Transaction distribution +system.membus.trans_dist::UpgradeResp 47755 # Transaction distribution +system.membus.trans_dist::ReadExReq 50059 # Transaction distribution +system.membus.trans_dist::ReadExResp 3238 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 423382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 423382 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1104141 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1104141 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57586 # Total snoops (count) +system.membus.snoop_fanout::samples 124108 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123701 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 124108 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123701 # Request fanout histogram -system.membus.reqLayer0.occupancy 290076020 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 43.5 # Layer utilization (%) -system.membus.respLayer0.occupancy 312416500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 46.8 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 371224 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371216 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43998 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43997 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 76237 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29460 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29459 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161009 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161004 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120675 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121112 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120676 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120671 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120387 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120891 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120940 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120505 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 965857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1759071 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1770038 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776630 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1763929 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1758071 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1768584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1767034 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1770802 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14134159 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 321748 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 561380 # Request fanout histogram +system.membus.snoop_fanout::total 124108 # Request fanout histogram +system.membus.reqLayer0.occupancy 285888056 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 60.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 306910429 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 64.5 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 371514 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371497 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43774 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43771 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 77037 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29480 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29478 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162492 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162484 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121222 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121108 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 121316 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 121170 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 121269 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120825 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 121366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 969045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1773466 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1761542 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1792162 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785037 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1774053 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1756466 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1780883 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14206666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 322486 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 565861 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1694,29 +1693,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 561380 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 565861 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 561380 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 655414034 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 160915376 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 161401861 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 160885313 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 160977419 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 160313901 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 24.0 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 161018393 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 160998320 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 160391036 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 24.0 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 565861 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 447470354 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 94.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102002382 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101806870 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101634818 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101702738 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101696707 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101422885 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101516818 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101999422 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 0808c4e4e..5b3332128 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 8581932612 # Simulator tick rate (ticks/s) -host_mem_usage 264172 # Number of bytes of host memory used -host_seconds 11.65 # Real time elapsed on the host +host_tick_rate 8616438631 # Simulator tick rate (ticks/s) +host_mem_usage 263800 # Number of bytes of host memory used +host_seconds 11.61 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory @@ -278,15 +278,15 @@ system.cpu.retryTicks 0 # Ti system.membus.trans_dist::ReadReq 1666397 # Transaction distribution system.membus.trans_dist::ReadResp 1666397 # Transaction distribution system.membus.trans_dist::WriteReq 1666879 # Transaction distribution -system.membus.trans_dist::WriteResp 1666879 # Transaction distribution -system.membus.pkt_count_system.monitor-master::system.physmem.port 6666552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6666552 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::WriteResp 1666878 # Transaction distribution +system.membus.pkt_count_system.monitor-master::system.physmem.port 6666551 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6666551 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11428907481 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 11.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 11028299087 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 11.0 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets @@ -339,8 +339,8 @@ system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # system.monitor.writeBurstLengthHist::total 1666879 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 1066494080 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 1063154535.263763 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 107915844.091091 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 1063154851.723305 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 107909478.113936 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -392,55 +392,55 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 106680256 # Number of bytes written system.monitor.readLatencyHist::samples 1666397 # Read request-response latency -system.monitor.readLatencyHist::mean 75229.617239 # Read request-response latency -system.monitor.readLatencyHist::gmean 69644.568825 # Read request-response latency -system.monitor.readLatencyHist::stdev 40693.683003 # Read request-response latency +system.monitor.readLatencyHist::mean 78736.863581 # Read request-response latency +system.monitor.readLatencyHist::gmean 73318.978124 # Read request-response latency +system.monitor.readLatencyHist::stdev 40691.515724 # Read request-response latency system.monitor.readLatencyHist::0-32767 22 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 444791 26.69% 26.69% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 1023501 61.42% 88.11% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 76998 4.62% 92.73% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 56964 3.42% 96.15% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 25239 1.51% 97.67% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 9180 0.55% 98.22% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 7794 0.47% 98.69% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 7780 0.47% 99.15% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 7547 0.45% 99.61% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 3313 0.20% 99.80% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 1429 0.09% 99.89% # Read request-response latency -system.monitor.readLatencyHist::393216-425983 850 0.05% 99.94% # Read request-response latency -system.monitor.readLatencyHist::425984-458751 662 0.04% 99.98% # Read request-response latency -system.monitor.readLatencyHist::458752-491519 284 0.02% 100.00% # Read request-response latency -system.monitor.readLatencyHist::491520-524287 42 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::524288-557055 1 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 439224 26.36% 26.36% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 1018381 61.11% 87.47% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 80826 4.85% 92.32% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 59766 3.59% 95.91% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 27643 1.66% 97.57% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 9933 0.60% 98.16% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 7785 0.47% 98.63% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 7834 0.47% 99.10% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 7851 0.47% 99.57% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 3709 0.22% 99.79% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1488 0.09% 99.88% # Read request-response latency +system.monitor.readLatencyHist::393216-425983 851 0.05% 99.93% # Read request-response latency +system.monitor.readLatencyHist::425984-458751 701 0.04% 99.98% # Read request-response latency +system.monitor.readLatencyHist::458752-491519 330 0.02% 100.00% # Read request-response latency +system.monitor.readLatencyHist::491520-524287 51 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::524288-557055 2 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1666397 # Read request-response latency -system.monitor.writeLatencyHist::samples 1666879 # Write request-response latency -system.monitor.writeLatencyHist::mean 10556.022655 # Write request-response latency -system.monitor.writeLatencyHist::gmean 10498.307841 # Write request-response latency -system.monitor.writeLatencyHist::stdev 1185.079839 # Write request-response latency -system.monitor.writeLatencyHist::0-1023 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::1024-2047 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::2048-3071 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::3072-4095 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::4096-5119 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::5120-6143 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::6144-7167 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::7168-8191 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::8192-9215 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::9216-10239 1276777 76.60% 76.60% # Write request-response latency -system.monitor.writeLatencyHist::10240-11263 91385 5.48% 82.08% # Write request-response latency -system.monitor.writeLatencyHist::11264-12287 111087 6.66% 88.74% # Write request-response latency -system.monitor.writeLatencyHist::12288-13311 90448 5.43% 94.17% # Write request-response latency -system.monitor.writeLatencyHist::13312-14335 61415 3.68% 97.85% # Write request-response latency -system.monitor.writeLatencyHist::14336-15359 31809 1.91% 99.76% # Write request-response latency -system.monitor.writeLatencyHist::15360-16383 3958 0.24% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::16384-17407 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::17408-18431 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::18432-19455 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::19456-20479 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::total 1666879 # Write request-response latency +system.monitor.writeLatencyHist::samples 1666878 # Write request-response latency +system.monitor.writeLatencyHist::mean 17579.367741 # Write request-response latency +system.monitor.writeLatencyHist::gmean 17571.346759 # Write request-response latency +system.monitor.writeLatencyHist::stdev 555.431458 # Write request-response latency +system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::6144-8191 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::8192-10239 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::10240-12287 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::12288-14335 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::14336-16383 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::16384-18431 1620268 97.20% 97.20% # Write request-response latency +system.monitor.writeLatencyHist::18432-20479 30675 1.84% 99.04% # Write request-response latency +system.monitor.writeLatencyHist::20480-22527 12936 0.78% 99.82% # Write request-response latency +system.monitor.writeLatencyHist::22528-24575 2999 0.18% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::24576-26623 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::26624-28671 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::28672-30719 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::30720-32767 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::38912-40959 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::total 1666878 # Write request-response latency system.monitor.ittReadRead::samples 1666396 # Read-to-read inter transaction time system.monitor.ittReadRead::mean 60009.683149 # Read-to-read inter transaction time system.monitor.ittReadRead::stdev 42949.620471 # Read-to-read inter transaction time @@ -526,12 +526,12 @@ system.monitor.ittReqReq::min_value 28000 # Re system.monitor.ittReqReq::max_value 1041309 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333275 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1.210000 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.260000 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 1.281532 # Outstanding read transactions -system.monitor.outstandingReadsHist::0 27 27.00% 27.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 46 46.00% 73.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 18 18.00% 91.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.284091 # Outstanding read transactions +system.monitor.outstandingReadsHist::0 26 26.00% 26.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 43 43.00% 69.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 22 22.00% 91.00% # Outstanding read transactions system.monitor.outstandingReadsHist::3 4 4.00% 95.00% # Outstanding read transactions system.monitor.outstandingReadsHist::4 1 1.00% 96.00% # Outstanding read transactions system.monitor.outstandingReadsHist::5 3 3.00% 99.00% # Outstanding read transactions @@ -551,11 +551,11 @@ system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Ou system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions -system.monitor.outstandingWritesHist::mean 0.190000 # Outstanding write transactions +system.monitor.outstandingWritesHist::mean 0.320000 # Outstanding write transactions system.monitor.outstandingWritesHist::gmean 0 # Outstanding write transactions -system.monitor.outstandingWritesHist::stdev 0.394277 # Outstanding write transactions -system.monitor.outstandingWritesHist::0 81 81.00% 81.00% # Outstanding write transactions -system.monitor.outstandingWritesHist::1 19 19.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::stdev 0.468826 # Outstanding write transactions +system.monitor.outstandingWritesHist::0 68 68.00% 68.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::1 32 32.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions |