diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:31 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:31 -0500 |
| commit | b20e92e1ca36486b9f01fa7df7e8cc8a87d17dcb (patch) | |
| tree | e391e796f376b0401ce34e724bad675b80345b68 /tests/quick | |
| parent | 8af1eeec6f28d9722802bf1588c911711db07ddd (diff) | |
| download | gem5-b20e92e1ca36486b9f01fa7df7e8cc8a87d17dcb.tar.xz | |
ARM: Update stats for previous changes.
Diffstat (limited to 'tests/quick')
15 files changed, 629 insertions, 641 deletions
diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini index 82f1d72df..69223be2f 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini @@ -25,6 +25,8 @@ BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 RASSize=16 SQEntries=32 SSITSize=1024 @@ -496,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout index bd4c923a3..8947d803a 100755 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/simout @@ -5,11 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 18 2011 20:12:03 -M5 started Mar 18 2011 21:02:41 -M5 executing on zizzer -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 19:31:16 +M5 executing on u200439-lin.austin.arm.com +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10827000 because target called exit() +Exiting @ tick 10803500 because target called exit() diff --git a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt index 7a0a94c69..f9b43ff41 100644 --- a/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 64369 # Simulator instruction rate (inst/s) -host_mem_usage 217368 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -host_tick_rate 121073299 # Simulator tick rate (ticks/s) +host_inst_rate 40713 # Simulator instruction rate (inst/s) +host_mem_usage 251964 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 76493621 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5739 # Number of instructions simulated sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10827000 # Number of ticks simulated +sim_ticks 10803500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 638 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 1727 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 701 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 388 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 1625 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 2128 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 927 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 60 # number cycles where commit BW limit reached +system.cpu.BPredUnit.condIncorrect 406 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 1671 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 2180 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 242 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 945 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 62 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 11088 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.517587 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.238879 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 11008 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.521348 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.245214 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 8513 76.78% 76.78% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 1240 11.18% 87.96% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 548 4.94% 92.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 324 2.92% 95.82% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 182 1.64% 97.47% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 135 1.22% 98.68% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 54 0.49% 99.17% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 32 0.29% 99.46% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 60 0.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 8442 76.69% 76.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 1229 11.16% 87.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 550 5.00% 92.85% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 321 2.92% 95.77% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 184 1.67% 97.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 137 1.24% 98.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 51 0.46% 99.15% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 32 0.29% 99.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 62 0.56% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 11088 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 11008 # Number of insts commited each cycle system.cpu.commit.COM:count 5739 # Number of instructions committed system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.COM:function_calls 82 # Number of function calls committed. @@ -44,14 +44,14 @@ system.cpu.commit.COM:loads 1201 # Nu system.cpu.commit.COM:membars 12 # Number of memory barriers committed system.cpu.commit.COM:refs 2139 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 318 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 317 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 24 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 4548 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4490 # The number of squashed insts skipped by commit system.cpu.committedInsts 5739 # Number of Instructions Simulated system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.773305 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.773305 # CPI: Total CPI of All Threads +system.cpu.cpi 3.765116 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.765116 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits @@ -59,84 +59,84 @@ system.cpu.dcache.LoadLockedReq_miss_latency 76500 system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.ReadReq_accesses 1838 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 32906.832298 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1677 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5298000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.087595 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 52 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 3270000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.059304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 109 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 1818 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33323.717949 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30423.809524 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1662 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5198500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.085809 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 156 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 51 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 3194500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.057756 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 105 # number of ReadReq MSHR misses system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35365.979381 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35785.714286 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_miss_latency 35788.659794 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_hits 622 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 10291500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 10414500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.318729 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses system.cpu.dcache.WriteReq_mshr_hits 249 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 1503000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 15.357616 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 15.673469 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 2751 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 34490.044248 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 31609.271523 # average overall mshr miss latency -system.cpu.dcache.demand_hits 2299 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 15589500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.164304 # miss rate for demand accesses -system.cpu.dcache.demand_misses 452 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4773000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.054889 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 2731 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34928.411633 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 31969.387755 # average overall mshr miss latency +system.cpu.dcache.demand_hits 2284 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 15613000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.163676 # miss rate for demand accesses +system.cpu.dcache.demand_misses 447 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 300 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4699500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.053826 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 147 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.022173 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 90.822117 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 2751 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 34490.044248 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 31609.271523 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.021822 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 89.381733 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 2731 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34928.411633 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 31969.387755 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 2299 # number of overall hits -system.cpu.dcache.overall_miss_latency 15589500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.164304 # miss rate for overall accesses -system.cpu.dcache.overall_misses 452 # number of overall misses -system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4773000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.054889 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses +system.cpu.dcache.overall_hits 2284 # number of overall hits +system.cpu.dcache.overall_miss_latency 15613000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.163676 # miss rate for overall accesses +system.cpu.dcache.overall_misses 447 # number of overall misses +system.cpu.dcache.overall_mshr_hits 300 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4699500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.053826 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 151 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 90.822117 # Cycle average of tags in use -system.cpu.dcache.total_refs 2319 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 89.381733 # Cycle average of tags in use +system.cpu.dcache.total_refs 2304 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 1287 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 156 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 338 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 12224 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 7477 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 2264 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 778 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 556 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 59 # Number of cycles decode is unblocking +system.cpu.decode.DECODE:BlockedCycles 1281 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 158 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 346 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 12207 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 7419 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 2259 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 770 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 557 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 48 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -158,242 +158,242 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.fetch.Branches 2128 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 1580 # Number of cache lines fetched -system.cpu.fetch.Cycles 2383 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 231 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 11094 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 497 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.098268 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 1580 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 875 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.512307 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 11865 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.163675 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.580533 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Branches 2180 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 1601 # Number of cache lines fetched +system.cpu.fetch.Cycles 2402 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 236 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 11132 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 496 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.100889 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 1601 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 943 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.515180 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 11777 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.177210 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.592697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9482 79.92% 79.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214 1.80% 81.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 146 1.23% 82.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 197 1.66% 84.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 189 1.59% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 268 2.26% 88.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 115 0.97% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 108 0.91% 90.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1146 9.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9375 79.60% 79.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 224 1.90% 81.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 149 1.27% 82.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 204 1.73% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 190 1.61% 86.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 260 2.21% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 117 0.99% 89.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 96 0.82% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1162 9.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11865 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 11777 # Number of instructions fetched each cycle (Total) system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.icache.ReadReq_accesses 1580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 34689.349112 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33338.541667 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 1242 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 11725000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.213924 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 338 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 9601500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.182278 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 288 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 1601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 34737.313433 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 33334.494774 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 1266 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 11637000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.209244 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 335 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 9567000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.179263 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 287 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 4.312500 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.411150 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 1580 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 34689.349112 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33338.541667 # average overall mshr miss latency -system.cpu.icache.demand_hits 1242 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 11725000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.213924 # miss rate for demand accesses -system.cpu.icache.demand_misses 338 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 50 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 9601500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.182278 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 288 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 1601 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 34737.313433 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 33334.494774 # average overall mshr miss latency +system.cpu.icache.demand_hits 1266 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 11637000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.209244 # miss rate for demand accesses +system.cpu.icache.demand_misses 335 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 9567000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.179263 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 287 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.071625 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 146.687091 # Average occupied blocks per context -system.cpu.icache.overall_accesses 1580 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 34689.349112 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33338.541667 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.071283 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 145.986730 # Average occupied blocks per context +system.cpu.icache.overall_accesses 1601 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 34737.313433 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 33334.494774 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 1242 # number of overall hits -system.cpu.icache.overall_miss_latency 11725000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.213924 # miss rate for overall accesses -system.cpu.icache.overall_misses 338 # number of overall misses -system.cpu.icache.overall_mshr_hits 50 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 9601500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.182278 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 288 # number of overall MSHR misses +system.cpu.icache.overall_hits 1266 # number of overall hits +system.cpu.icache.overall_miss_latency 11637000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.209244 # miss rate for overall accesses +system.cpu.icache.overall_misses 335 # number of overall misses +system.cpu.icache.overall_mshr_hits 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 9567000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.179263 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 287 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.sampled_refs 288 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 287 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 146.687091 # Cycle average of tags in use -system.cpu.icache.total_refs 1242 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 145.986730 # Cycle average of tags in use +system.cpu.icache.total_refs 1266 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 9790 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 1278 # Number of branches executed -system.cpu.iew.EXEC:nop 18 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.379774 # Inst execution rate -system.cpu.iew.EXEC:refs 3122 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 1148 # Number of stores executed +system.cpu.idleCycles 9831 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 1296 # Number of branches executed +system.cpu.iew.EXEC:nop 3 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.372316 # Inst execution rate +system.cpu.iew.EXEC:refs 3091 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 1139 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 7311 # num instructions consuming a value -system.cpu.iew.WB:count 7762 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.493093 # average fanout of values written-back +system.cpu.iew.WB:consumers 7215 # num instructions consuming a value +system.cpu.iew.WB:count 7676 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.492862 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 3605 # num instructions producing a value -system.cpu.iew.WB:rate 0.358439 # insts written-back per cycle -system.cpu.iew.WB:sent 7965 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 367 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 201 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 2382 # Number of dispatched load instructions +system.cpu.iew.WB:producers 3556 # num instructions producing a value +system.cpu.iew.WB:rate 0.355239 # insts written-back per cycle +system.cpu.iew.WB:sent 7793 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 365 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 209 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 2372 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 1514 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 10450 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 1974 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 8224 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 1498 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 10370 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 1952 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 334 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 8045 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 778 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking +system.cpu.iew.iewSquashCycles 770 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 26 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 51 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.forwLoads 52 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1181 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 576 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 272 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 95 # Number of branches that were predicted taken incorrectly -system.cpu.int_regfile_reads 18651 # number of integer regfile reads -system.cpu.int_regfile_writes 5571 # number of integer regfile writes -system.cpu.ipc 0.265020 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.265020 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 1171 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 560 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 246 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 119 # Number of branches that were predicted taken incorrectly +system.cpu.int_regfile_reads 18334 # number of integer regfile reads +system.cpu.int_regfile_writes 5507 # number of integer regfile writes +system.cpu.ipc 0.265596 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.265596 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 5254 61.43% 61.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6 0.07% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 61.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.04% 61.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.53% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 2109 24.66% 86.19% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 1181 13.81% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 5116 61.06% 61.06% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6 0.07% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 61.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.04% 61.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 2082 24.85% 86.01% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 1172 13.99% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 8553 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 186 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.021747 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 8379 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 180 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.021482 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 6 3.23% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 3.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 120 64.52% 67.74% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 60 32.26% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 2 1.11% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 1.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 119 66.11% 67.22% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 59 32.78% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 11865 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.720860 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.364573 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 11777 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.711472 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.348484 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 8254 69.57% 69.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 1404 11.83% 81.40% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 840 7.08% 88.48% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 572 4.82% 93.30% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 408 3.44% 96.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 241 2.03% 98.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 114 0.96% 99.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 24 0.20% 99.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 8190 69.54% 69.54% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 1436 12.19% 81.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 830 7.05% 88.78% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 533 4.53% 93.31% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 422 3.58% 96.89% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 239 2.03% 98.92% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 96 0.82% 99.74% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 23 0.20% 99.93% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::8 8 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 11865 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.394967 # Inst issue rate +system.cpu.iq.ISSUE:issued_per_cycle::total 11777 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.387773 # Inst issue rate system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.int_alu_accesses 8719 # Number of integer alu accesses -system.cpu.iq.int_inst_queue_reads 29141 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_wakeup_accesses 7746 # Number of integer instruction queue wakeup accesses -system.cpu.iq.int_inst_queue_writes 14669 # Number of integer instruction queue writes -system.cpu.iq.iqInstsAdded 10407 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 8553 # Number of instructions issued +system.cpu.iq.int_alu_accesses 8539 # Number of integer alu accesses +system.cpu.iq.int_inst_queue_reads 28698 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_wakeup_accesses 7660 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_writes 14568 # Number of integer instruction queue writes +system.cpu.iq.iqInstsAdded 10342 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 8379 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 4242 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4207 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6639 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 6956 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -416,99 +416,99 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34416.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 1445500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 34392.857143 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31261.904762 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 1444500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1313500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1313000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34356.545961 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31244.318182 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 38 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 12334000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.904282 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 359 # number of ReadReq misses +system.cpu.l2cache.ReadReq_accesses 392 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34365.168539 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31250.716332 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 36 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 12234000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.908163 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 356 # number of ReadReq misses system.cpu.l2cache.ReadReq_mshr_hits 7 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_miss_latency 10998000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.886650 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 10906500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.890306 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 349 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.107955 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.103152 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34362.842893 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31247.461929 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 38 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 13779500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.913440 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 401 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 434 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34368.090452 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.918159 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 36 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 13678500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.917051 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 398 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 7 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 12311500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.897494 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 394 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 12219500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.900922 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 391 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005707 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 187.002555 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34362.842893 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31247.461929 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005656 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 185.350735 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 434 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34368.090452 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.918159 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 38 # number of overall hits -system.cpu.l2cache.overall_miss_latency 13779500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.913440 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 401 # number of overall misses +system.cpu.l2cache.overall_hits 36 # number of overall hits +system.cpu.l2cache.overall_miss_latency 13678500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.917051 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 398 # number of overall misses system.cpu.l2cache.overall_mshr_hits 7 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 12311500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.897494 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 394 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 12219500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.900922 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 391 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 349 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 187.002555 # Cycle average of tags in use -system.cpu.l2cache.total_refs 38 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 185.350735 # Cycle average of tags in use +system.cpu.l2cache.total_refs 36 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 2382 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1514 # Number of stores inserted to the mem dependence unit. -system.cpu.misc_regfile_reads 13955 # number of misc regfile reads -system.cpu.misc_regfile_writes 4 # number of misc regfile writes -system.cpu.numCycles 21655 # number of cpu cycles simulated +system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 2372 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1498 # Number of stores inserted to the mem dependence unit. +system.cpu.misc_regfile_reads 13984 # number of misc regfile reads +system.cpu.misc_regfile_writes 26 # number of misc regfile writes +system.cpu.numCycles 21608 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.rename.RENAME:BlockCycles 331 # Number of cycles rename is blocking +system.cpu.rename.RENAME:BlockCycles 329 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 4124 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 31 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 7738 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 132 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 29900 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 11466 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 8204 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 2060 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 778 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 198 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 4077 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:IQFullEvents 48 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 7684 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 118 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 30009 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 11406 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 8239 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 2041 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 770 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 193 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 4112 # Number of HB maps that are undone due to squashing system.cpu.rename.RENAME:fp_rename_lookups 390 # Number of floating rename lookups -system.cpu.rename.RENAME:int_rename_lookups 29510 # Number of integer rename lookups +system.cpu.rename.RENAME:int_rename_lookups 29619 # Number of integer rename lookups system.cpu.rename.RENAME:serializeStallCycles 760 # count of cycles rename stalled for serializing inst system.cpu.rename.RENAME:serializingInsts 16 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 569 # count of insts added to the skid buffer +system.cpu.rename.RENAME:skidInsts 508 # count of insts added to the skid buffer system.cpu.rename.RENAME:tempSerializingInsts 14 # count of temporary serializing insts renamed -system.cpu.rob.rob_reads 21158 # The number of ROB reads -system.cpu.rob.rob_writes 21364 # The number of ROB writes +system.cpu.rob.rob_reads 21018 # The number of ROB reads +system.cpu.rob.rob_writes 21240 # The number of ROB writes system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 13 # Number of system calls diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout index 9914f72a8..716a43c24 100755 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 21:03:49 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 19:31:27 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt index 95e8b4e85..41570e285 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 642377 # Simulator instruction rate (inst/s) -host_mem_usage 242352 # Number of bytes of host memory used +host_inst_rate 507203 # Simulator instruction rate (inst/s) +host_mem_usage 243076 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host -host_tick_rate 312928501 # Simulator tick rate (ticks/s) +host_tick_rate 248530683 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5739 # Number of instructions simulated sim_seconds 0.000003 # Number of seconds simulated @@ -56,7 +56,7 @@ system.cpu.numCycles 5752 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 5752 # Number of busy cycles -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_fp_register_reads 16 # number of times the floating registers were read diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout index 567715f28..c22e81711 100755 --- a/tests/quick/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 11 2011 20:10:09 -M5 revision 4decc284606a 8095 default qtip tip ext/update_add_stats.patch -M5 started Mar 11 2011 20:10:13 +M5 compiled Mar 30 2011 17:47:57 +M5 started Mar 30 2011 19:31:37 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-timing +command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt index c331a990a..06b8ada90 100644 --- a/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4300 # Simulator instruction rate (inst/s) -host_mem_usage 250076 # Number of bytes of host memory used -host_seconds 1.32 # Real time elapsed on the host -host_tick_rate 19945674 # Simulator tick rate (ticks/s) +host_inst_rate 270959 # Simulator instruction rate (inst/s) +host_mem_usage 250792 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 1240926423 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5682 # Number of instructions simulated sim_seconds 0.000026 # Number of seconds simulated @@ -244,7 +244,7 @@ system.cpu.numCycles 52722 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 52722 # Number of busy cycles -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 793 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_fp_register_reads 16 # number of times the floating registers were read diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 725f5e8b2..55937ba29 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -5,11 +5,10 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 8 2011 18:03:23 -M5 revision bc33117f65cf 8095 default qtip tip ext/m5threads_regs_stats_2.patch -M5 started Mar 8 2011 18:03:32 +M5 compiled Mar 31 2011 10:39:48 +M5 started Mar 31 2011 10:41:48 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index ee0ac0aeb..f07a8b73e 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1902387 # Simulator instruction rate (inst/s) -host_mem_usage 375352 # Number of bytes of host memory used -host_seconds 27.39 # Real time elapsed on the host -host_tick_rate 964164912 # Simulator tick rate (ticks/s) +host_inst_rate 2149518 # Simulator instruction rate (inst/s) +host_mem_usage 377184 # Number of bytes of host memory used +host_seconds 24.24 # Real time elapsed on the host +host_tick_rate 1089414447 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 52098748 # Number of instructions simulated sim_seconds 0.026405 # Number of seconds simulated @@ -228,20 +228,20 @@ system.cpu.numCycles 52809606 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 52809606 # Number of busy cycles -system.cpu.num_conditional_control_insts 6951306 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 7028794 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses system.cpu.num_fp_insts 6058 # number of float instructions system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written -system.cpu.num_func_calls 1111841 # number of times a function call or return occured +system.cpu.num_func_calls 1109315 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_insts 52098748 # Number of instructions executed system.cpu.num_int_alu_accesses 42510432 # Number of integer alu accesses system.cpu.num_int_insts 42510432 # number of integer instructions -system.cpu.num_int_register_reads 131106249 # number of times the integer registers were read -system.cpu.num_int_register_writes 34920214 # number of times the integer registers were written -system.cpu.num_load_insts 9214448 # Number of load instructions -system.cpu.num_mem_refs 16301436 # number of memory refs +system.cpu.num_int_register_reads 131106250 # number of times the integer registers were read +system.cpu.num_int_register_writes 34554090 # number of times the integer registers were written +system.cpu.num_load_insts 9208607 # Number of load instructions +system.cpu.num_mem_refs 16295595 # number of memory refs system.cpu.num_store_insts 7086988 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status index 53b01d583..586cb6b73 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status @@ -1 +1 @@ -build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED! +build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED! diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index 1cff4671c..63ac398c9 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -32,14 +32,8 @@ warn: Returning thumbEE disabled for now since we don't support CP14config regis For more information see: http://www.m5sim.org/warn/7998f2ea warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 warn: instruction 'mcr bpiall' unimplemented For more information see: http://www.m5sim.org/warn/21b09adb -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 -warn: Complete acc isn't called on normal stores in O3. -For more information see: http://www.m5sim.org/warn/138d8573 warn: Need to flush all TLBs in MP For more information see: http://www.m5sim.org/warn/6cccf999 warn: instruction 'mcr bpiall' unimplemented diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 231e421ce..d825514be 100755 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -5,12 +5,11 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Mar 8 2011 18:03:23 -M5 revision bc33117f65cf 8095 default qtip tip ext/m5threads_regs_stats_2.patch -M5 started Mar 8 2011 18:03:32 +M5 compiled Mar 31 2011 10:39:48 +M5 started Mar 31 2011 10:41:48 M5 executing on u200439-lin.austin.arm.com -command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing +command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 114726567000 because m5_exit instruction encountered +Exiting @ tick 114396880000 because m5_exit instruction encountered diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index b7164e421..8519551d7 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,254 +1,252 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1109216 # Simulator instruction rate (inst/s) -host_mem_usage 375472 # Number of bytes of host memory used -host_seconds 46.19 # Real time elapsed on the host -host_tick_rate 2483966419 # Simulator tick rate (ticks/s) +host_inst_rate 978936 # Simulator instruction rate (inst/s) +host_mem_usage 377208 # Number of bytes of host memory used +host_seconds 52.33 # Real time elapsed on the host +host_tick_rate 2185988851 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 51230867 # Number of instructions simulated -sim_seconds 0.114727 # Number of seconds simulated -sim_ticks 114726567000 # Number of ticks simulated -system.cpu.dcache.LoadLockedReq_accesses::0 100290 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 100290 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14562.978560 # average LoadLockedReq miss latency +sim_insts 51229325 # Number of instructions simulated +sim_seconds 0.114397 # Number of seconds simulated +sim_ticks 114396880000 # Number of ticks simulated +system.cpu.dcache.LoadLockedReq_accesses::0 100300 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 100300 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14571.455939 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11562.978560 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.cpu.dcache.LoadLockedReq_hits::0 95066 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 95066 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 76077000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052089 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 5224 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 5224 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60405000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052089 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11571.455939 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 95080 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 95080 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 76063000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052044 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 5220 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 5220 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 60403000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052044 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 5224 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310532000 # number of LoadLockedReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_accesses::0 7828656 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 7828656 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 15679.539912 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 5220 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 7828326 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 7828326 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 15676.806243 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12679.195749 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12676.464295 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7590397 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7590397 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 3735791500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.030434 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 238259 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 238259 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3020932500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030434 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7589986 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7589986 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 3736410000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.030446 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 238340 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 238340 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 3021308500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030446 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 238259 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191771500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 100289 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 100289 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_hits::0 100289 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 100289 # number of StoreCondReq hits -system.cpu.dcache.WriteReq_accesses::0 6674369 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6674369 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 40728.962545 # average WriteReq miss latency +system.cpu.dcache.ReadReq_mshr_misses 238340 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 38191118000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 100299 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 100299 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_hits::0 100299 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 100299 # number of StoreCondReq hits +system.cpu.dcache.WriteReq_accesses::0 6674054 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6674054 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 40732.768985 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37728.712808 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37732.519239 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 6502188 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6502188 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7012753500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.025797 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 172181 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 172181 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 6496167500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025797 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 6501879 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6501879 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 7013164500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.025798 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 172175 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 172175 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 6496596500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025798 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 172181 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927436000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_misses 172175 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 927308500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 34.529769 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 34.522937 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 14503025 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 14502380 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 14503025 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26187.859370 # average overall miss latency +system.cpu.dcache.demand_accesses::total 14502380 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26185.582744 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 14092585 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23185.279466 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 14091865 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 14092585 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 10748545000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.028300 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 14091865 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10749574500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.028307 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 410440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 410515 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 410440 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 410515 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9517100000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.028300 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_latency 9517905000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.028307 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 410440 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 410515 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.994530 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 509.199247 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 14503025 # number of overall (read+write) accesses +system.cpu.dcache.occ_%::0 0.994514 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 509.191175 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 14502380 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 14503025 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26187.859370 # average overall miss latency +system.cpu.dcache.overall_accesses::total 14502380 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26185.582744 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23187.554819 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23185.279466 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 14092585 # number of overall hits +system.cpu.dcache.overall_hits::0 14091865 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 14092585 # number of overall hits -system.cpu.dcache.overall_miss_latency 10748545000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.028300 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 14091865 # number of overall hits +system.cpu.dcache.overall_miss_latency 10749574500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.028307 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 410440 # number of overall misses +system.cpu.dcache.overall_misses::0 410515 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 410440 # number of overall misses +system.cpu.dcache.overall_misses::total 410515 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9517100000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.028300 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_latency 9517905000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.028307 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 410440 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 39119207500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 410515 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 39118426500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 413327 # number of replacements -system.cpu.dcache.sampled_refs 413839 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 413389 # number of replacements +system.cpu.dcache.sampled_refs 413901 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 509.199247 # Cycle average of tags in use -system.cpu.dcache.total_refs 14289765 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 509.191175 # Cycle average of tags in use +system.cpu.dcache.total_refs 14289078 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 658097000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 381698 # number of writebacks -system.cpu.dtb.accesses 15531532 # DTB accesses +system.cpu.dcache.writebacks 381928 # number of writebacks +system.cpu.dtb.accesses 15530893 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.flush_entries 2220 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 2229 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.hits 15525999 # DTB hits +system.cpu.dtb.hits 15525358 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.misses 5533 # DTB misses +system.cpu.dtb.misses 5535 # DTB misses system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.prefetch_faults 757 # Number of TLB faults due to prefetch -system.cpu.dtb.read_accesses 8744287 # DTB read accesses -system.cpu.dtb.read_hits 8739733 # DTB read hits +system.cpu.dtb.prefetch_faults 763 # Number of TLB faults due to prefetch +system.cpu.dtb.read_accesses 8743955 # DTB read accesses +system.cpu.dtb.read_hits 8739401 # DTB read hits system.cpu.dtb.read_misses 4554 # DTB read misses -system.cpu.dtb.write_accesses 6787245 # DTB write accesses -system.cpu.dtb.write_hits 6786266 # DTB write hits -system.cpu.dtb.write_misses 979 # DTB write misses -system.cpu.icache.ReadReq_accesses::0 41555414 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41555414 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14790.398445 # average ReadReq miss latency +system.cpu.dtb.write_accesses 6786938 # DTB write accesses +system.cpu.dtb.write_hits 6785957 # DTB write hits +system.cpu.dtb.write_misses 981 # DTB write misses +system.cpu.icache.ReadReq_accesses::0 41554370 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 41554370 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14791.166028 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11789.103925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11789.867728 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_hits::0 41121276 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41121276 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 6421074000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.010447 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 434138 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 434138 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 5118098000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010447 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_hits::0 41120341 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 41120341 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 6419795000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.010445 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 434029 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 434029 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 5117144500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.010445 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 434138 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 434029 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable_latency 349111000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 94.719366 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 94.740999 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 41555414 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 41554370 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41555414 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14790.398445 # average overall miss latency +system.cpu.icache.demand_accesses::total 41554370 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14791.166028 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 41121276 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11789.867728 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 41120341 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41121276 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 6421074000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.010447 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 41120341 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 6419795000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.010445 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 434138 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 434029 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 434138 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 434029 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 5118098000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.010447 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_latency 5117144500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.010445 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 434138 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 434029 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.946115 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 484.411008 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 41555414 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.945960 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 484.331512 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 41554370 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41555414 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14790.398445 # average overall miss latency +system.cpu.icache.overall_accesses::total 41554370 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14791.166028 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11789.103925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11789.867728 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 41121276 # number of overall hits +system.cpu.icache.overall_hits::0 41120341 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 41121276 # number of overall hits -system.cpu.icache.overall_miss_latency 6421074000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.010447 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 41120341 # number of overall hits +system.cpu.icache.overall_miss_latency 6419795000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.010445 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 434138 # number of overall misses +system.cpu.icache.overall_misses::0 434029 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 434138 # number of overall misses +system.cpu.icache.overall_misses::total 434029 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 5118098000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.010447 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_latency 5117144500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.010445 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 434138 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 434029 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 349111000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 433626 # number of replacements -system.cpu.icache.sampled_refs 434138 # Sample count of references to valid blocks. +system.cpu.icache.replacements 433517 # number of replacements +system.cpu.icache.sampled_refs 434029 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 484.411008 # Cycle average of tags in use -system.cpu.icache.total_refs 41121276 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 14253306000 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 34007 # number of writebacks +system.cpu.icache.tagsinuse 484.331512 # Cycle average of tags in use +system.cpu.icache.total_refs 41120341 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 14252346000 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 33990 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.accesses 41558233 # DTB accesses +system.cpu.itb.accesses 41557189 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB @@ -256,9 +254,9 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.hits 41555414 # DTB hits -system.cpu.itb.inst_accesses 41558233 # ITB inst accesses -system.cpu.itb.inst_hits 41555414 # ITB inst hits +system.cpu.itb.hits 41554370 # DTB hits +system.cpu.itb.inst_accesses 41557189 # ITB inst accesses +system.cpu.itb.inst_hits 41554370 # ITB inst hits system.cpu.itb.inst_misses 2819 # ITB inst misses system.cpu.itb.misses 2819 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions @@ -272,25 +270,25 @@ system.cpu.itb.write_misses 0 # DT system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 229453134 # number of cpu cycles simulated +system.cpu.numCycles 228793760 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.num_busy_cycles 229453134 # Number of busy cycles -system.cpu.num_conditional_control_insts 6949779 # number of instructions that are conditional controls +system.cpu.num_busy_cycles 228793760 # Number of busy cycles +system.cpu.num_conditional_control_insts 7027251 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses system.cpu.num_fp_insts 6058 # number of float instructions system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written -system.cpu.num_func_calls 1112296 # number of times a function call or return occured +system.cpu.num_func_calls 1109649 # number of times a function call or return occured system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_insts 51230867 # Number of instructions executed -system.cpu.num_int_alu_accesses 42501566 # Number of integer alu accesses -system.cpu.num_int_insts 42501566 # number of integer instructions -system.cpu.num_int_register_reads 139355134 # number of times the integer registers were read -system.cpu.num_int_register_writes 34914798 # number of times the integer registers were written -system.cpu.num_load_insts 9211791 # Number of load instructions -system.cpu.num_mem_refs 16296219 # number of memory refs -system.cpu.num_store_insts 7084428 # Number of store instructions +system.cpu.num_insts 51229325 # Number of instructions executed +system.cpu.num_int_alu_accesses 42499970 # Number of integer alu accesses +system.cpu.num_int_insts 42499970 # number of integer instructions +system.cpu.num_int_register_reads 139350355 # number of times the integer registers were read +system.cpu.num_int_register_writes 34546681 # number of times the integer registers were written +system.cpu.num_load_insts 9205633 # Number of load instructions +system.cpu.num_mem_refs 16289741 # number of memory refs +system.cpu.num_store_insts 7084108 # Number of store instructions system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs no_value # Average number of references to valid blocks. @@ -358,142 +356,140 @@ system.iocache.tagsinuse 0 # Cy system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.writebacks 0 # number of writebacks -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_mshr_uncacheable_latency 234360000 # number of LoadLockedReq MSHR uncacheable cycles -system.l2c.ReadExReq_accesses::0 170356 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 170356 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 170341 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 170341 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 62546 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 62546 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 5606120000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.632851 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 107810 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 107810 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4312400000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.632851 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_hits::0 62528 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 62528 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 5606276000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.632925 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 107813 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107813 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4312520000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.632925 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 107810 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 675489 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 5600 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 681089 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52080.437900 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 33725803.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 33777884.009328 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 107813 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 675455 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 5724 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 681179 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52080.460087 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 33716517.857143 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 33768598.317230 # average ReadReq miss latency system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 657357 # number of ReadReq hits -system.l2c.ReadReq_hits::1 5572 # number of ReadReq hits -system.l2c.ReadReq_hits::total 662929 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 944322500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.026843 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.005000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.031843 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 18132 # number of ReadReq misses +system.l2c.ReadReq_hits::0 657328 # number of ReadReq hits +system.l2c.ReadReq_hits::1 5696 # number of ReadReq hits +system.l2c.ReadReq_hits::total 663024 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 944062500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.026837 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.004892 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.031728 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 18127 # number of ReadReq misses system.l2c.ReadReq_misses::1 28 # number of ReadReq misses -system.l2c.ReadReq_misses::total 18160 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 726400000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026884 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 3.242857 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.269741 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 18160 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 29200446000 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 1825 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 489.208633 # average UpgradeReq miss latency +system.l2c.ReadReq_misses::total 18155 # number of ReadReq misses +system.l2c.ReadReq_mshr_miss_latency 726200000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026878 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 3.171733 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 3.198611 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 18155 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 29199871000 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 1834 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1834 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 486.784141 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits system.l2c.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.990137 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 1807 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1807 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 72280000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.990137 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.990185 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 1816 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1816 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 72640000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.990185 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 1807 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 1816 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 740884000 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 415705 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 415705 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 415705 # number of Writeback hits -system.l2c.Writeback_hits::total 415705 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 740804000 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 415918 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 415918 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 415918 # number of Writeback hits +system.l2c.Writeback_hits::total 415918 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 7.060757 # Average number of references to valid blocks. +system.l2c.avg_refs 7.061430 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 845845 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 5600 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 851445 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52011.580728 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 233944375 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 233996386.580728 # average overall miss latency +system.l2c.demand_accesses::0 845796 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 5724 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 851520 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52011.580912 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 233940660.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 233992672.295197 # average overall miss latency system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.l2c.demand_hits::0 719903 # number of demand (read+write) hits -system.l2c.demand_hits::1 5572 # number of demand (read+write) hits -system.l2c.demand_hits::total 725475 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6550442500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.148895 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.005000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.153895 # miss rate for demand accesses -system.l2c.demand_misses::0 125942 # number of demand (read+write) misses +system.l2c.demand_hits::0 719856 # number of demand (read+write) hits +system.l2c.demand_hits::1 5696 # number of demand (read+write) hits +system.l2c.demand_hits::total 725552 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6550338500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.148901 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.004892 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.153793 # miss rate for demand accesses +system.l2c.demand_misses::0 125940 # number of demand (read+write) misses system.l2c.demand_misses::1 28 # number of demand (read+write) misses -system.l2c.demand_misses::total 125970 # number of demand (read+write) misses +system.l2c.demand_misses::total 125968 # number of demand (read+write) misses system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 5038800000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.148928 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 22.494643 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 22.643571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 125970 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_miss_latency 5038720000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.148934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 22.006988 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 22.155922 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 125968 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.081481 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.477898 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 5339.953820 # Average occupied blocks per context -system.l2c.occ_blocks::1 31319.548737 # Average occupied blocks per context -system.l2c.overall_accesses::0 845845 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 5600 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 851445 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52011.580728 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 233944375 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 233996386.580728 # average overall miss latency +system.l2c.occ_%::0 0.081501 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.478004 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 5341.251518 # Average occupied blocks per context +system.l2c.occ_blocks::1 31326.461137 # Average occupied blocks per context +system.l2c.overall_accesses::0 845796 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 5724 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 851520 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52011.580912 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 233940660.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 233992672.295197 # average overall miss latency system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 719903 # number of overall hits -system.l2c.overall_hits::1 5572 # number of overall hits -system.l2c.overall_hits::total 725475 # number of overall hits -system.l2c.overall_miss_latency 6550442500 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.148895 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.005000 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.153895 # miss rate for overall accesses -system.l2c.overall_misses::0 125942 # number of overall misses +system.l2c.overall_hits::0 719856 # number of overall hits +system.l2c.overall_hits::1 5696 # number of overall hits +system.l2c.overall_hits::total 725552 # number of overall hits +system.l2c.overall_miss_latency 6550338500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.148901 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.004892 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.153793 # miss rate for overall accesses +system.l2c.overall_misses::0 125940 # number of overall misses system.l2c.overall_misses::1 28 # number of overall misses -system.l2c.overall_misses::total 125970 # number of overall misses +system.l2c.overall_misses::total 125968 # number of overall misses system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 5038800000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.148928 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 22.494643 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 22.643571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 125970 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 29941330000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency 5038720000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.148934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 22.006988 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 22.155922 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 125968 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 29940675000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 93233 # number of replacements -system.l2c.sampled_refs 124676 # Sample count of references to valid blocks. +system.l2c.replacements 93229 # number of replacements +system.l2c.sampled_refs 124678 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 36659.502556 # Cycle average of tags in use -system.l2c.total_refs 880307 # Total number of references to valid blocks. +system.l2c.tagsinuse 36667.712655 # Cycle average of tags in use +system.l2c.total_refs 880405 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 87349 # number of writebacks +system.l2c.writebacks 87341 # number of writebacks ---------- End Simulation Statistics ---------- diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status index 624e9a5f7..8953751c2 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status @@ -1 +1 @@ -build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED! +build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED! diff --git a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal Binary files differindex 3921585df..26233ccc0 100644 --- a/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal +++ b/tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal |